derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu: Remove duplicated commit stats

Browse Source 
This removes committedInstType and comittedControl from minor CPU,
stat branches from O3 commit stage, and O3 commit stats floating,
integer, loads, memRefs, and vectorInstructions.

Change-Id: I57abea0881eaaea52da3f365078d6b0e2ea1bfeb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/69106
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Melissa Jost
2023-03-20 00:17:38 -07:00
committed by Bobby Bruce
parent 19323c8bd7
commit 1cf1867ffa
7 changed files with 1 additions and 177 deletions
Download Patch File Download Diff File Expand all files Collapse all files

36
src/cpu/minor/execute.cc
View File

@@ -882,46 +882,10 @@ Execute::doInstCommitAccounting(MinorDynInstPtr inst)
thread->numOp++;
thread->threadStats.numOps++;
cpu.stats.numOps++;
// update both old and new stats
cpu.commitStats[inst->id.threadId]->numOps++;
cpu.baseStats.numOps++;
cpu.commitStats[inst->id.threadId]
->committedInstType[inst->staticInst->opClass()]++;
cpu.stats.committedInstType[inst->id.threadId]
[inst->staticInst->opClass()]++;
/** Add a count for every control instruction */
if (inst->staticInst->isControl()) {
if (inst->staticInst->isReturn()) {
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsReturn]++;
}
if (inst->staticInst->isCall()) {
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsCall]++;
}
if (inst->staticInst->isDirectCtrl()) {
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsDirectControl]++;
}
if (inst->staticInst->isIndirectCtrl()) {
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsIndirectControl]++;
}
if (inst->staticInst->isCondCtrl()) {
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsCondControl]++;
}
if (inst->staticInst->isUncondCtrl()) {
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsUncondControl]++;
}
cpu.stats.committedControl[inst->id.threadId]
[gem5::StaticInstFlags::Flags::IsControl]++;
}
/* Set the CP SeqNum to the numOps commit number */
if (inst->traceData)

16
src/cpu/minor/stats.cc
View File

@@ -60,11 +60,7 @@ MinorStats::MinorStats(BaseCPU *base_cpu)
"CPI: cycles per instruction"),
ADD_STAT(ipc, statistics::units::Rate<
statistics::units::Count, statistics::units::Cycle>::get(),
"IPC: instructions per cycle"),
ADD_STAT(committedInstType, statistics::units::Count::get(),
"Class of committed instruction"),
ADD_STAT(committedControl, statistics::units::Count::get(),
"Class of control type instructions committed")
"IPC: instructions per cycle")
{
quiesceCycles.prereq(quiesceCycles);
@@ -74,16 +70,6 @@ MinorStats::MinorStats(BaseCPU *base_cpu)
ipc.precision(6);
ipc = numInsts / base_cpu->baseStats.numCycles;
committedInstType
.init(base_cpu->numThreads, enums::Num_OpClass)
.flags(statistics::total | statistics::pdf | statistics::dist);
committedInstType.ysubnames(enums::OpClassStrings);
committedControl
.init(base_cpu->numThreads, StaticInstFlags::Flags::Num_Flags)
.flags(statistics::nozero);
committedControl.ysubnames(StaticInstFlags::FlagsStrings);
}
} // namespace minor

6
src/cpu/minor/stats.hh
View File

@@ -75,12 +75,6 @@ struct MinorStats : public statistics::Group
statistics::Formula cpi;
statistics::Formula ipc;
/** Number of instructions by type (OpClass) */
statistics::Vector2d committedInstType;
/** Number of branches commited */
statistics::Vector2d committedControl;
};
} // namespace minor

52
src/cpu/o3/commit.cc
View File

@@ -160,21 +160,10 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit)
"Number of instructions committed"),
ADD_STAT(opsCommitted, statistics::units::Count::get(),
"Number of ops (including micro ops) committed"),
ADD_STAT(memRefs, statistics::units::Count::get(),
"Number of memory references committed"),
ADD_STAT(loads, statistics::units::Count::get(), "Number of loads committed"),
ADD_STAT(amos, statistics::units::Count::get(),
"Number of atomic instructions committed"),
ADD_STAT(membars, statistics::units::Count::get(),
"Number of memory barriers committed"),
ADD_STAT(branches, statistics::units::Count::get(),
"Number of branches committed"),
ADD_STAT(vectorInstructions, statistics::units::Count::get(),
"Number of committed Vector instructions."),
ADD_STAT(floating, statistics::units::Count::get(),
"Number of committed floating point instructions."),
ADD_STAT(integer, statistics::units::Count::get(),
"Number of committed integer instructions."),
ADD_STAT(functionCalls, statistics::units::Count::get(),
"Number of function calls committed."),
ADD_STAT(committedInstType, statistics::units::Count::get(),
@@ -200,14 +189,6 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit)
.init(cpu->numThreads)
.flags(total);
memRefs
.init(cpu->numThreads)
.flags(total);
loads
.init(cpu->numThreads)
.flags(total);
amos
.init(cpu->numThreads)
.flags(total);
@@ -216,22 +197,6 @@ Commit::CommitStats::CommitStats(CPU *cpu, Commit *commit)
.init(cpu->numThreads)
.flags(total);
branches
.init(cpu->numThreads)
.flags(total);
vectorInstructions
.init(cpu->numThreads)
.flags(total);
floating
.init(cpu->numThreads)
.flags(total);
integer
.init(cpu->numThreads)
.flags(total);
functionCalls
.init(commit->numThreads)
.flags(total);
@@ -1405,29 +1370,18 @@ Commit::updateComInstStats(const DynInstPtr &inst)
//
// Control Instructions
//
// update both old and new stats
cpu->commitStats[tid]->updateComCtrlStats(inst->staticInst);
if (inst->isControl())
stats.branches[tid]++;
//
// Memory references
//
if (inst->isMemRef()) {
// update both old and new stats
stats.memRefs[tid]++;
cpu->commitStats[tid]->numMemRefs++;
if (inst->isLoad()) {
// update both old and new stats
stats.loads[tid]++;
cpu->commitStats[tid]->numLoadInsts++;
}
if (inst->isAtomic()) {
stats.amos[tid]++;
}
if (inst->isStore()) {
cpu->commitStats[tid]->numStoreInsts++;
}
@@ -1439,22 +1393,16 @@ Commit::updateComInstStats(const DynInstPtr &inst)
// Integer Instruction
if (inst->isInteger()) {
// update both old and new stats
cpu->commitStats[tid]->numIntInsts++;
stats.integer[tid]++;
}
// Floating Point Instruction
if (inst->isFloating()) {
// update both old and new stats
cpu->commitStats[tid]->numFpInsts++;
stats.floating[tid]++;
}
// Vector Instruction
if (inst->isVector()) {
// update both old and new stats
cpu->commitStats[tid]->numVecInsts++;
stats.vectorInstructions[tid]++;
}
// Function Calls

12
src/cpu/o3/commit.hh
View File

@@ -483,22 +483,10 @@ class Commit
statistics::Vector instsCommitted;
/** Total number of ops (including micro ops) committed. */
statistics::Vector opsCommitted;
/** Stat for the total number of committed memory references. */
statistics::Vector memRefs;
/** Stat for the total number of committed loads. */
statistics::Vector loads;
/** Stat for the total number of committed atomics. */
statistics::Vector amos;
/** Total number of committed memory barriers. */
statistics::Vector membars;
/** Total number of committed branches. */
statistics::Vector branches;
/** Total number of vector instructions */
statistics::Vector vectorInstructions;
/** Total number of floating point instructions */
statistics::Vector floating;
/** Total number of integer instructions */
statistics::Vector integer;
/** Total number of function calls */
statistics::Vector functionCalls;
/** Committed instructions by instruction type (OpClass) */

17
src/cpu/simple/base.cc
View File

@@ -437,29 +437,23 @@ BaseSimpleCPU::postExecute()
/* Power model statistics */
//integer alu accesses
if (curStaticInst->isInteger()){
// update both old and new stats
executeStats[t_info.thread->threadId()]->numIntAluAccesses++;
commitStats[t_info.thread->threadId()]->numIntInsts++;
t_info.execContextStats.numIntAluAccesses++;
t_info.execContextStats.numIntInsts++;
}
//float alu accesses
if (curStaticInst->isFloating()){
// update both old and new stats
executeStats[t_info.thread->threadId()]->numFpAluAccesses++;
commitStats[t_info.thread->threadId()]->numFpInsts++;
t_info.execContextStats.numFpAluAccesses++;
t_info.execContextStats.numFpInsts++;
}
//vector alu accesses
if (curStaticInst->isVector()){
// update both old and new stats
executeStats[t_info.thread->threadId()]->numVecAluAccesses++;
commitStats[t_info.thread->threadId()]->numVecInsts++;
t_info.execContextStats.numVecAluAccesses++;
t_info.execContextStats.numVecInsts++;
}
//Matrix alu accesses
@@ -473,30 +467,19 @@ BaseSimpleCPU::postExecute()
t_info.execContextStats.numCallsReturns++;
}
//the number of branch predictions that will be made
if (curStaticInst->isCondCtrl()){
t_info.execContextStats.numCondCtrlInsts++;
}
//result bus acceses
if (curStaticInst->isLoad()){
// update both old and new stats
commitStats[t_info.thread->threadId()]->numLoadInsts++;
t_info.execContextStats.numLoadInsts++;
}
if (curStaticInst->isStore() || curStaticInst->isAtomic()){
// update both old and new stats
commitStats[t_info.thread->threadId()]->numStoreInsts++;
t_info.execContextStats.numStoreInsts++;
}
/* End power model statistics */
// update both old and new stats
commitStats[t_info.thread->threadId()]
->committedInstType[curStaticInst->opClass()]++;
commitStats[t_info.thread->threadId()]->updateComCtrlStats(curStaticInst);
t_info.execContextStats.statExecutedInstType[curStaticInst->opClass()]++;
/* increment the committed numInsts and numOps stats */
countCommitInst();

39
src/cpu/simple/exec_context.hh
View File

@@ -100,14 +100,6 @@ class SimpleExecContext : public ExecContext
"Number of matrix alu accesses"),
ADD_STAT(numCallsReturns, statistics::units::Count::get(),
"Number of times a function call or return occured"),
ADD_STAT(numCondCtrlInsts, statistics::units::Count::get(),
"Number of instructions that are conditional controls"),
ADD_STAT(numIntInsts, statistics::units::Count::get(),
"Number of integer instructions"),
ADD_STAT(numFpInsts, statistics::units::Count::get(),
"Number of float instructions"),
ADD_STAT(numVecInsts, statistics::units::Count::get(),
"Number of vector instructions"),
ADD_STAT(numMatInsts, statistics::units::Count::get(),
"Number of matrix instructions"),
ADD_STAT(numIntRegReads, statistics::units::Count::get(),
@@ -136,10 +128,6 @@ class SimpleExecContext : public ExecContext
"Number of times the Misc registers were written"),
ADD_STAT(numMemRefs, statistics::units::Count::get(),
"Number of memory refs"),
ADD_STAT(numLoadInsts, statistics::units::Count::get(),
"Number of load instructions"),
ADD_STAT(numStoreInsts, statistics::units::Count::get(),
"Number of store instructions"),
ADD_STAT(numIdleCycles, statistics::units::Cycle::get(),
"Number of idle cycles"),
ADD_STAT(numBusyCycles, statistics::units::Cycle::get(),
@@ -156,8 +144,6 @@ class SimpleExecContext : public ExecContext
"Number of branches predicted as taken"),
ADD_STAT(numBranchMispred, statistics::units::Count::get(),
"Number of branch mispredictions"),
ADD_STAT(statExecutedInstType, statistics::units::Count::get(),
"Class of executed instruction."),
numRegReads{
&(cpu->executeStats[thread->threadId()]->numIntRegReads),
&(cpu->executeStats[thread->threadId()]->numFpRegReads),
@@ -190,14 +176,6 @@ class SimpleExecContext : public ExecContext
dcacheStallCycles
.prereq(dcacheStallCycles);
statExecutedInstType
.init(enums::Num_OpClass)
.flags(statistics::total | statistics::pdf | statistics::dist);
for (unsigned i = 0; i < Num_OpClasses; ++i) {
statExecutedInstType.subname(i, enums::OpClassStrings[i]);
}
idleFraction = statistics::constant(1.0) - notIdleFraction;
numIdleCycles = idleFraction * cpu->baseStats.numCycles;
numBusyCycles = notIdleFraction * cpu->baseStats.numCycles;
@@ -228,18 +206,6 @@ class SimpleExecContext : public ExecContext
// Number of function calls/returns
statistics::Scalar numCallsReturns;
// Conditional control instructions;
statistics::Scalar numCondCtrlInsts;
// Number of int instructions
statistics::Scalar numIntInsts;
// Number of float instructions
statistics::Scalar numFpInsts;
// Number of vector instructions
statistics::Scalar numVecInsts;
// Number of matrix instructions
statistics::Scalar numMatInsts;
@@ -273,8 +239,6 @@ class SimpleExecContext : public ExecContext
// Number of simulated memory references
statistics::Scalar numMemRefs;
statistics::Scalar numLoadInsts;
statistics::Scalar numStoreInsts;
// Number of idle cycles
statistics::Formula numIdleCycles;
@@ -299,9 +263,6 @@ class SimpleExecContext : public ExecContext
statistics::Scalar numBranchMispred;
/// @}
// Instruction mix histogram by OpClass
statistics::Vector statExecutedInstType;
std::array<statistics::Scalar *, CCRegClass + 1> numRegReads;
std::array<statistics::Scalar *, CCRegClass + 1> numRegWrites;