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arch-arm, dev-arm: Use PageTableOps in Arm TableWalker

Browse Source 
As the VMSA is shared between the CPU MMU and the SMMU, we move the
PageTableOps data structures to the arch/arm/pagetable.hh/cc sources.

Both MMUs will make use of them

Change-Id: I3a1113f6ef56f8d879aff2df50a01037baca82ff
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51672
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-08-02 18:06:51 +01:00
parent 526b03407a
commit 1b6c050ebf
11 changed files with 204 additions and 239 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/dev/arm/SConscript
View File

@@ -76,7 +76,6 @@ Source('smmu_v3_cmdexec.cc', tags='arm isa');
Source('smmu_v3_events.cc', tags='arm isa');
Source('smmu_v3_ports.cc', tags='arm isa');
Source('smmu_v3_proc.cc', tags='arm isa');
Source('smmu_v3_ptops.cc', tags='arm isa');
Source('smmu_v3_deviceifc.cc', tags='arm isa');
Source('smmu_v3_transl.cc', tags='arm isa');
Source('timer_sp804.cc', tags='arm isa')

16
src/dev/arm/smmu_v3.cc
View File

@@ -567,22 +567,6 @@ SMMUv3::processCommand(const SMMUCommand &cmd)
}
}
const PageTableOps*
SMMUv3::getPageTableOps(uint8_t trans_granule)
{
static V8PageTableOps4k ptOps4k;
static V8PageTableOps16k ptOps16k;
static V8PageTableOps64k ptOps64k;
switch (trans_granule) {
case TRANS_GRANULE_4K: return &ptOps4k;
case TRANS_GRANULE_16K: return &ptOps16k;
case TRANS_GRANULE_64K: return &ptOps64k;
default:
panic("Unknown translation granule size %d", trans_granule);
}
}
Tick
SMMUv3::readControl(PacketPtr pkt)
{

3
src/dev/arm/smmu_v3.hh
View File

@@ -52,7 +52,6 @@
#include "dev/arm/smmu_v3_events.hh"
#include "dev/arm/smmu_v3_ports.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "dev/arm/smmu_v3_ptops.hh"
#include "mem/packet.hh"
#include "params/SMMUv3.hh"
#include "sim/clocked_object.hh"
@@ -172,8 +171,6 @@ class SMMUv3 : public ClockedObject
void processCommand(const SMMUCommand &cmd);
const PageTableOps *getPageTableOps(uint8_t trans_granule);
public:
SMMUv3(const SMMUv3Params &p);
virtual ~SMMUv3() {}

428
src/dev/arm/smmu_v3_ptops.cc
View File

@@ -1,428 +0,0 @@
/*
* Copyright (c) 2013, 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "dev/arm/smmu_v3_ptops.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
namespace gem5
{
bool
V7LPageTableOps::isValid(pte_t pte, unsigned level) const
{
switch (level) {
case 1: return pte & 0x1;
case 2: return pte & 0x1;
case 3: return (pte & 0x1) && (pte & 0x2);
default: panic("bad level %d", level);
}
}
bool
V7LPageTableOps::isLeaf(pte_t pte, unsigned level) const
{
switch (level) {
case 1: return !(pte & 0x2);
case 2: return !(pte & 0x2);
case 3: return true;
default: panic("bad level %d", level);
}
}
bool
V7LPageTableOps::isWritable(pte_t pte, unsigned level, bool stage2) const
{
return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
}
Addr
V7LPageTableOps::nextLevelPointer(pte_t pte, unsigned level) const
{
if (isLeaf(pte, level)) {
switch (level) {
case 1: return mbits(pte, 39, 30);
case 2: return mbits(pte, 39, 21);
case 3: return mbits(pte, 39, 12);
default: panic("bad level %d", level);
}
} else {
return mbits(pte, 39, 12);
}
}
Addr
V7LPageTableOps::index(Addr va, unsigned level) const
{
// In theory this should be configurable...
const int n = 12;
switch (level) {
case 1: return bits(va, 26+n, 30) << 3; break;
case 2: return bits(va, 29, 21) << 3; break;
case 3: return bits(va, 20, 12) << 3; break;
default: panic("bad level %d", level);
}
}
Addr
V7LPageTableOps::pageMask(pte_t pte, unsigned level) const
{
switch (level) {
case 1: return ~mask(30);
case 2: return ~mask(21);
case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12);
default: panic("bad level %d", level);
}
}
Addr
V7LPageTableOps::walkMask(unsigned level) const
{
switch (level) {
case 1: return ~mask(30);
case 2: return ~mask(21);
case 3: return ~mask(12);
default: panic("bad level %d", level);
}
}
unsigned
V7LPageTableOps::firstLevel(uint8_t tsz) const
{
return 1;
}
unsigned
V7LPageTableOps::lastLevel() const
{
return 3;
}
bool
V8PageTableOps4k::isValid(pte_t pte, unsigned level) const
{
switch (level) {
case 0: return pte & 0x1;
case 1: return pte & 0x1;
case 2: return pte & 0x1;
case 3: return (pte & 0x1) && (pte & 0x2);
default: panic("bad level %d", level);
}
}
bool
V8PageTableOps4k::isLeaf(pte_t pte, unsigned level) const
{
switch (level) {
case 0: return false;
case 1: return !(pte & 0x2);
case 2: return !(pte & 0x2);
case 3: return true;
default: panic("bad level %d", level);
}
}
bool
V8PageTableOps4k::isWritable(pte_t pte, unsigned level, bool stage2) const
{
return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
}
Addr
V8PageTableOps4k::nextLevelPointer(pte_t pte, unsigned level) const
{
if (isLeaf(pte, level)) {
switch (level) {
// no level 0 here
case 1: return mbits(pte, 47, 30);
case 2: return mbits(pte, 47, 21);
case 3: return mbits(pte, 47, 12);
default: panic("bad level %d", level);
}
} else {
return mbits(pte, 47, 12);
}
}
Addr
V8PageTableOps4k::index(Addr va, unsigned level) const
{
switch (level) {
case 0: return bits(va, 47, 39) << 3; break;
case 1: return bits(va, 38, 30) << 3; break;
case 2: return bits(va, 29, 21) << 3; break;
case 3: return bits(va, 20, 12) << 3; break;
default: panic("bad level %d", level);
}
}
Addr
V8PageTableOps4k::pageMask(pte_t pte, unsigned level) const
{
switch (level) {
// no level 0 here
case 1: return ~mask(30);
case 2: return ~mask(21);
case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12);
default: panic("bad level %d", level);
}
}
Addr
V8PageTableOps4k::walkMask(unsigned level) const
{
switch (level) {
case 0: return ~mask(39);
case 1: return ~mask(30);
case 2: return ~mask(21);
case 3: return ~mask(12);
default: panic("bad level %d", level);
}
}
unsigned
V8PageTableOps4k::firstLevel(uint8_t tsz) const
{
if (tsz >= 16 && tsz <= 24) return 0;
if (tsz >= 25 && tsz <= 33) return 1;
if (tsz >= 34 && tsz <= 39) return 2;
panic("Unsupported TnSZ: %d\n", tsz);
}
unsigned
V8PageTableOps4k::lastLevel() const
{
return 3;
}
bool
V8PageTableOps16k::isValid(pte_t pte, unsigned level) const
{
switch (level) {
case 0: return pte & 0x1;
case 1: return pte & 0x1;
case 2: return pte & 0x1;
case 3: return (pte & 0x1) && (pte & 0x2);
default: panic("bad level %d", level);
}
}
bool
V8PageTableOps16k::isLeaf(pte_t pte, unsigned level) const
{
switch (level) {
case 0: return false;
case 1: return false;
case 2: return !(pte & 0x2);
case 3: return true;
default: panic("bad level %d", level);
}
}
bool
V8PageTableOps16k::isWritable(pte_t pte, unsigned level, bool stage2) const
{
return stage2 ? bits(pte, 7, 6) == 3 : bits(pte, 7) == 0;
}
Addr
V8PageTableOps16k::nextLevelPointer(pte_t pte, unsigned level) const
{
if (isLeaf(pte, level)) {
switch (level) {
// no level 0 here
case 1: return mbits(pte, 47, 36);
case 2: return mbits(pte, 47, 25);
case 3: return mbits(pte, 47, 14);
default: panic("bad level %d", level);
}
} else {
return mbits(pte, 47, 14);
}
}
Addr
V8PageTableOps16k::index(Addr va, unsigned level) const
{
switch (level) {
case 0: return bits(va, 47, 47) << 3; break;
case 1: return bits(va, 46, 36) << 3; break;
case 2: return bits(va, 35, 25) << 3; break;
case 3: return bits(va, 24, 14) << 3; break;
default: panic("bad level %d", level);
}
}
Addr
V8PageTableOps16k::pageMask(pte_t pte, unsigned level) const
{
switch (level) {
// no level 0 here
case 1: return ~mask(36);
// 16K granule supports contiguous entries also at L2; - 1G
case 2: return bits(pte, 52) ? ~mask(30) : ~mask(25);
// as well as at L3; - 2M
case 3: return bits(pte, 52) ? ~mask(21) : ~mask(14);
default: panic("bad level %d", level);
}
}
Addr
V8PageTableOps16k::walkMask(unsigned level) const
{
switch (level) {
case 0: return ~mask(47);
case 1: return ~mask(36);
case 2: return ~mask(25);
case 3: return ~mask(14);
default: panic("bad level %d", level);
}
}
unsigned
V8PageTableOps16k::firstLevel(uint8_t tsz) const
{
if (tsz == 16) return 0;
if (tsz >= 17 && tsz <= 27) return 1;
if (tsz >= 28 && tsz <= 38) return 2;
if (tsz == 39) return 3;
panic("Unsupported TnSZ: %d\n", tsz);
}
unsigned
V8PageTableOps16k::lastLevel() const
{
return 3;
}
bool
V8PageTableOps64k::isValid(pte_t pte, unsigned level) const
{
switch (level) {
case 1: return pte & 0x1;
case 2: return pte & 0x1;
case 3: return (pte & 0x1) && (pte & 0x2);
default: panic("bad level %d", level);
}
}
bool
V8PageTableOps64k::isLeaf(pte_t pte, unsigned level) const
{
switch (level) {
case 1: return false;
case 2: return !(pte & 0x2);
case 3: return true;
default: panic("bad level %d", level);
}
}
bool
V8PageTableOps64k::isWritable(pte_t pte, unsigned level, bool stage2) const
{
return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
}
Addr
V8PageTableOps64k::nextLevelPointer(pte_t pte, unsigned level) const
{
if (isLeaf(pte, level)) {
switch (level) {
// no level 1 here
case 2: return mbits(pte, 47, 29);
case 3: return mbits(pte, 47, 16);
default: panic("bad level %d", level);
}
} else {
return mbits(pte, 47, 16);
}
}
Addr
V8PageTableOps64k::index(Addr va, unsigned level) const
{
switch (level) {
case 1: return bits(va, 47, 42) << 3; break;
case 2: return bits(va, 41, 29) << 3; break;
case 3: return bits(va, 28, 16) << 3; break;
default: panic("bad level %d", level);
}
}
Addr
V8PageTableOps64k::pageMask(pte_t pte, unsigned level) const
{
switch (level) {
// no level 1 here
case 2: return ~mask(29);
case 3: return bits(pte, 52) ? ~mask(21) : ~mask(16);
default: panic("bad level %d", level);
}
}
Addr
V8PageTableOps64k::walkMask(unsigned level) const
{
switch (level) {
case 1: return ~mask(42);
case 2: return ~mask(29);
case 3: return ~mask(16);
default: panic("bad level %d", level);
}
}
unsigned
V8PageTableOps64k::firstLevel(uint8_t tsz) const
{
if (tsz >= 12 && tsz <= 21) return 1;
if (tsz >= 22 && tsz <= 34) return 2;
if (tsz >= 35 && tsz <= 39) return 3;
panic("Unsupported TnSZ: %d\n", tsz);
}
unsigned
V8PageTableOps64k::lastLevel() const
{
return 3;
}
} // namespace gem5

117
src/dev/arm/smmu_v3_ptops.hh
View File

@@ -1,117 +0,0 @@
/*
* Copyright (c) 2013, 2018-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DEV_ARM_SMMU_V3_PTOPS_HH__
#define __DEV_ARM_SMMU_V3_PTOPS_HH__
#include <stdint.h>
#include "base/types.hh"
namespace gem5
{
struct PageTableOps
{
typedef int64_t pte_t;
virtual bool isValid(pte_t pte, unsigned level) const = 0;
virtual bool isLeaf(pte_t pte, unsigned level) const = 0;
virtual bool isWritable(pte_t pte, unsigned level, bool stage2) const = 0;
virtual Addr nextLevelPointer(pte_t pte, unsigned level) const = 0;
virtual Addr index(Addr va, unsigned level) const = 0;
virtual Addr pageMask(pte_t pte, unsigned level) const = 0;
virtual Addr walkMask(unsigned level) const = 0;
virtual unsigned firstLevel(uint8_t tsz) const = 0;
virtual unsigned lastLevel() const = 0;
};
struct V7LPageTableOps : public PageTableOps
{
bool isValid(pte_t pte, unsigned level) const override;
bool isLeaf(pte_t pte, unsigned level) const override;
bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
Addr nextLevelPointer(pte_t pte, unsigned level) const override;
Addr index(Addr va, unsigned level) const override;
Addr pageMask(pte_t pte, unsigned level) const override;
Addr walkMask(unsigned level) const override;
unsigned firstLevel(uint8_t tsz) const override;
unsigned lastLevel() const override;
};
struct V8PageTableOps4k : public PageTableOps
{
bool isValid(pte_t pte, unsigned level) const override;
bool isLeaf(pte_t pte, unsigned level) const override;
bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
Addr nextLevelPointer(pte_t pte, unsigned level) const override;
Addr index(Addr va, unsigned level) const override;
Addr pageMask(pte_t pte, unsigned level) const override;
Addr walkMask(unsigned level) const override;
unsigned firstLevel(uint8_t tsz) const override;
unsigned lastLevel() const override;
};
struct V8PageTableOps16k : public PageTableOps
{
bool isValid(pte_t pte, unsigned level) const override;
bool isLeaf(pte_t pte, unsigned level) const override;
bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
Addr nextLevelPointer(pte_t pte, unsigned level) const override;
Addr index(Addr va, unsigned level) const override;
Addr pageMask(pte_t pte, unsigned level) const override;
Addr walkMask(unsigned level) const override;
unsigned firstLevel(uint8_t tsz) const override;
unsigned lastLevel() const override;
};
struct V8PageTableOps64k : public PageTableOps
{
bool isValid(pte_t pte, unsigned level) const override;
bool isLeaf(pte_t pte, unsigned level) const override;
bool isWritable(pte_t pte, unsigned level, bool stage2) const override;
Addr nextLevelPointer(pte_t pte, unsigned level) const override;
Addr index(Addr va, unsigned level) const override;
Addr pageMask(pte_t pte, unsigned level) const override;
Addr walkMask(unsigned level) const override;
unsigned firstLevel(uint8_t tsz) const override;
unsigned lastLevel() const override;
};
} // namespace gem5
#endif /* __DEV_ARM_SMMU_V3_PTOPS_HH__ */

22
src/dev/arm/smmu_v3_transl.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013, 2018-2019 ARM Limited
* Copyright (c) 2013, 2018-2019, 2021 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -37,6 +37,7 @@
#include "dev/arm/smmu_v3_transl.hh"
#include "arch/arm/pagetable.hh"
#include "debug/SMMUv3.hh"
#include "debug/SMMUv3Hazard.hh"
#include "dev/arm/amba.hh"
@@ -46,6 +47,8 @@
namespace gem5
{
using namespace ArmISA;
SMMUTranslRequest
SMMUTranslRequest::fromPacket(PacketPtr pkt, bool ats)
{
@@ -657,10 +660,11 @@ SMMUTranslationProcess::walkCacheLookup(
const char *indent = stage==2 ? " " : "";
(void) indent; // this is only used in DPRINTFs
const PageTableOps *pt_ops =
stage == 1 ?
smmu.getPageTableOps(context.stage1TranslGranule) :
smmu.getPageTableOps(context.stage2TranslGranule);
const auto tg = stage == 1 ?
GrainMap_tg0[context.stage1TranslGranule] :
GrainMap_tg0[context.stage2TranslGranule];
const auto *pt_ops = getPageTableOps(tg);
unsigned walkCacheLevels =
smmu.walkCacheEnable ?
@@ -882,8 +886,8 @@ SMMUTranslationProcess::walkStage2(Yield &yield, Addr addr, bool final_tr,
SMMUTranslationProcess::TranslResult
SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
{
const PageTableOps *pt_ops =
smmu.getPageTableOps(context.stage1TranslGranule);
const auto tg = GrainMap_tg0[context.stage1TranslGranule];
const auto *pt_ops = getPageTableOps(tg);
const WalkCache::Entry *walk_ep = NULL;
unsigned level;
@@ -938,8 +942,8 @@ SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
SMMUTranslationProcess::TranslResult
SMMUTranslationProcess::translateStage2(Yield &yield, Addr addr, bool final_tr)
{
const PageTableOps *pt_ops =
smmu.getPageTableOps(context.stage2TranslGranule);
const auto tg = GrainMap_tg0[context.stage2TranslGranule];
const auto *pt_ops = getPageTableOps(tg);
const IPACache::Entry *ipa_ep = NULL;
if (smmu.ipaCacheEnable) {

10
src/dev/arm/smmu_v3_transl.hh
View File

@@ -41,12 +41,16 @@
#include "base/compiler.hh"
#include "dev/arm/smmu_v3_deviceifc.hh"
#include "dev/arm/smmu_v3_proc.hh"
#include "dev/arm/smmu_v3_ptops.hh"
#include "mem/packet.hh"
namespace gem5
{
namespace ArmISA
{
struct PageTableOps;
}
struct SMMUTranslRequest
{
Addr addr;
@@ -129,11 +133,11 @@ class SMMUTranslationProcess : public SMMUProcess
bool leaf, uint8_t permissions);
TranslResult walkStage1And2(Yield &yield, Addr addr,
const PageTableOps *pt_ops,
const ArmISA::PageTableOps *pt_ops,
unsigned level, Addr walkPtr);
TranslResult walkStage2(Yield &yield, Addr addr, bool final_tr,
const PageTableOps *pt_ops,
const ArmISA::PageTableOps *pt_ops,
unsigned level, Addr walkPtr);
TranslResult translateStage1And2(Yield &yield, Addr addr);