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arch-riscv: Move FCSR implementation to isa.cc

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Change-Id: I132edfe2c0ae4caecaa9e6209249662895b5c608
This commit is contained in:
Roger Chang
2024-04-30 11:39:13 +08:00
parent 6ed446e546
commit 1a81144985
3 changed files with 15 additions and 18 deletions
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11
src/arch/riscv/isa.cc
View File

@@ -576,6 +576,11 @@ ISA::readMiscReg(RegIndex idx)
{
return readMiscRegNoEffect(MISCREG_FFLAGS) & FFLAGS_MASK;
}
case MISCREG_FCSR:
{
return readMiscRegNoEffect(MISCREG_FFLAGS) |
(readMiscRegNoEffect(MISCREG_FRM) << FRM_OFFSET);
}
default:
// Try reading HPM counters
// As a placeholder, all HPM counters are just cycle counters
@@ -782,6 +787,12 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
setMiscRegNoEffect(MISCREG_FFLAGS, new_val);
}
break;
case MISCREG_FCSR:
{
setMiscRegNoEffect(MISCREG_FFLAGS, bits(val, 4, 0));
setMiscRegNoEffect(MISCREG_FRM, bits(val, 7, 5));
}
break;
default:
setMiscRegNoEffect(idx, val);
}

18
src/arch/riscv/isa/formats/standard.isa
View File

@@ -389,13 +389,7 @@ def template CSRExecute {{
break;
}
if (csr == CSR_FCSR) {
olddata = xc->readMiscReg(MISCREG_FFLAGS) |
(xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
} else {
olddata = xc->readMiscReg(midx);
}
olddata = rvZext(olddata);
olddata = rvZext(xc->readMiscReg(midx));
auto olddata_all = olddata;
olddata &= maskVal;
@@ -417,15 +411,7 @@ def template CSRExecute {{
newdata_all = (olddata_all & ~maskVal) | data;
DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n",
newdata_all, csrName);
switch (csr) {
case CSR_FCSR:
xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
break;
default:
xc->setMiscReg(midx, newdata_all);
break;
}
xc->setMiscReg(midx, newdata_all);
}
%(op_wb)s;
return NoFault;

4
src/arch/riscv/regs/misc.hh
View File

@@ -250,6 +250,7 @@ enum MiscRegIndex
// This CSR shared the same space with MISCREG_FFLAGS
MISCREG_FFLAGS_EXE = NUM_PHYS_MISCREGS,
MISCREG_FCSR,
NUM_MISCREGS
};
@@ -548,9 +549,8 @@ const std::unordered_map<int, CSRMetadata> CSRData = {
isaExtsFlags('f')}},
{CSR_FRM,
{"frm", MISCREG_FRM, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
// Actually FRM << 5 | FFLAGS
{CSR_FCSR,
{"fcsr", MISCREG_FFLAGS, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
{"fcsr", MISCREG_FCSR, rvTypeFlags(RV64, RV32), isaExtsFlags('f')}},
{CSR_CYCLE,
{"cycle", MISCREG_CYCLE, rvTypeFlags(RV64, RV32), isaExtsFlags()}},
{CSR_TIME,