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inorder: use flattenIdx for reg indexing

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- also use "threadId()" instead of readTid() everywhere
- this will help support more complex ISA indexing
This commit is contained in:
Korey Sewell
2011-06-19 21:43:33 -04:00
parent b2e5152e16
commit 19e3eb2915
9 changed files with 152 additions and 109 deletions
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33
src/cpu/inorder/cpu.cc
View File

@@ -1095,40 +1095,59 @@ InOrderCPU::getPipeStage(int stage_num)
return pipelineStage[stage_num];
}
uint64_t
InOrderCPU::readIntReg(int reg_idx, ThreadID tid)
RegIndex
InOrderCPU::flattenRegIdx(RegIndex reg_idx, ThreadID tid)
{
if (reg_idx < FP_Base_DepTag) {
return isa[tid].flattenIntIndex(reg_idx);
} else if (reg_idx < Ctrl_Base_DepTag) {
reg_idx -= FP_Base_DepTag;
return isa[tid].flattenFloatIndex(reg_idx);
} else {
return reg_idx -= TheISA::Ctrl_Base_DepTag;
}
}
uint64_t
InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
{
DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
tid, reg_idx, intRegs[tid][reg_idx]);
return intRegs[tid][reg_idx];
}
FloatReg
InOrderCPU::readFloatReg(int reg_idx, ThreadID tid)
InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
{
return floatRegs.f[tid][reg_idx];
}
FloatRegBits
InOrderCPU::readFloatRegBits(int reg_idx, ThreadID tid)
InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
{;
return floatRegs.i[tid][reg_idx];
}
void
InOrderCPU::setIntReg(int reg_idx, uint64_t val, ThreadID tid)
InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
{
DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
tid, reg_idx, val);
intRegs[tid][reg_idx] = val;
}
void
InOrderCPU::setFloatReg(int reg_idx, FloatReg val, ThreadID tid)
InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
{
floatRegs.f[tid][reg_idx] = val;
}
void
InOrderCPU::setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid)
InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
{
floatRegs.i[tid][reg_idx] = val;
}

15
src/cpu/inorder/cpu.hh
View File

@@ -80,6 +80,7 @@ class InOrderCPU : public BaseCPU
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::RegIndex RegIndex;
//DynInstPtr TypeDefs
typedef ThePipeline::DynInstPtr DynInstPtr;
@@ -509,17 +510,19 @@ class InOrderCPU : public BaseCPU
}
/** Register file accessors */
uint64_t readIntReg(int reg_idx, ThreadID tid);
uint64_t readIntReg(RegIndex reg_idx, ThreadID tid);
FloatReg readFloatReg(int reg_idx, ThreadID tid);
FloatReg readFloatReg(RegIndex reg_idx, ThreadID tid);
FloatRegBits readFloatRegBits(int reg_idx, ThreadID tid);
FloatRegBits readFloatRegBits(RegIndex reg_idx, ThreadID tid);
void setIntReg(int reg_idx, uint64_t val, ThreadID tid);
void setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid);
void setFloatReg(int reg_idx, FloatReg val, ThreadID tid);
void setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid);
void setFloatRegBits(int reg_idx, FloatRegBits val, ThreadID tid);
void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
RegIndex flattenRegIdx(RegIndex reg_idx, ThreadID tid);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);

16
src/cpu/inorder/reg_dep_map.cc
View File

@@ -64,6 +64,7 @@ void
RegDepMap::setCPU(InOrderCPU *_cpu)
{
cpu = _cpu;
}
void
@@ -97,10 +98,12 @@ RegDepMap::insert(DynInstPtr inst)
void
RegDepMap::insert(unsigned idx, DynInstPtr inst)
{
DPRINTF(RegDepMap, "Inserting [sn:%i] onto dep. list for reg. idx %i.\n",
inst->seqNum, idx);
TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, inst->threadNumber);
regMap[idx].push_back(inst);
DPRINTF(RegDepMap, "Inserting [sn:%i] onto dep. list for reg. idx %i (%i).\n",
inst->seqNum, idx, flat_idx);
regMap[flat_idx].push_back(inst);
inst->setRegDepEntry();
}
@@ -171,7 +174,7 @@ RegDepMap::canRead(unsigned idx, DynInstPtr inst)
}
ThePipeline::DynInstPtr
RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst)
RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst, unsigned clean_idx)
{
std::list<DynInstPtr>::iterator list_it = regMap[reg_idx].begin();
std::list<DynInstPtr>::iterator list_end = regMap[reg_idx].end();
@@ -184,9 +187,12 @@ RegDepMap::canForward(unsigned reg_idx, DynInstPtr inst)
forward_inst = (*list_it);
list_it++;
}
DPRINTF(RegDepMap, "[sn:%i] Found potential forwarding value for reg %i (%i)"
" w/ [sn:%i]\n",
inst->seqNum, reg_idx, clean_idx, inst->seqNum);
if (forward_inst) {
int dest_reg_idx = forward_inst->getDestIdxNum(reg_idx);
int dest_reg_idx = forward_inst->getDestIdxNum(clean_idx);
assert(dest_reg_idx != -1);
if (forward_inst->isExecuted() &&

2
src/cpu/inorder/reg_dep_map.hh
View File

@@ -82,7 +82,7 @@ class RegDepMap
/** Is the current instruction able to get a forwarded value from
* another instruction for this destination register?
*/
DynInstPtr canForward(unsigned reg_idx, DynInstPtr inst);
DynInstPtr canForward(unsigned reg_idx, DynInstPtr inst, unsigned clean_idx);
/** find an instruction to forward/bypass a value from */
DynInstPtr findBypassInst(unsigned idx);

126
src/cpu/inorder/resources/use_def.cc
View File

@@ -167,48 +167,49 @@ UseDefUnit::execute(int slot_idx)
{
case ReadSrcReg:
{
int reg_idx = inst->_srcRegIdx[ud_idx];
RegIndex reg_idx = inst->_srcRegIdx[ud_idx];
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, tid);
DPRINTF(InOrderUseDef, "[tid:%i]: Attempting to read source "
"register idx %i (reg #%i).\n",
tid, ud_idx, reg_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Attempting to read source "
"register idx %i (reg #%i, flat#%i).\n",
tid, seq_num, ud_idx, reg_idx, flat_idx);
// Ask register dependency map if it is OK to read from Arch.
// Reg. File
if (regDepMap[tid]->canRead(reg_idx, inst)) {
if (regDepMap[tid]->canRead(flat_idx, inst)) {
uniqueRegMap[reg_idx] = true;
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx < FP_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Int Reg %i"
"from Register File:%i.\n",
tid,
reg_idx,
cpu->readIntReg(reg_idx,inst->readTid()));
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Int Reg %i"
" (%i) from Register File:%i.\n",
tid, seq_num,
reg_idx, flat_idx,
cpu->readIntReg(flat_idx,inst->readTid()));
inst->setIntSrc(ud_idx,
cpu->readIntReg(reg_idx,
cpu->readIntReg(flat_idx,
inst->readTid()));
} else if (reg_idx < Ctrl_Base_DepTag) {
reg_idx -= FP_Base_DepTag;
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Float Reg %i"
"from Register File:%x (%08f).\n",
tid,
reg_idx,
cpu->readFloatRegBits(reg_idx,
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Float Reg %i"
" (%i) from Register File:%x (%08f).\n",
tid, seq_num,
reg_idx, flat_idx,
cpu->readFloatRegBits(flat_idx,
inst->readTid()),
cpu->readFloatReg(reg_idx,
cpu->readFloatReg(flat_idx,
inst->readTid()));
inst->setFloatSrc(ud_idx,
cpu->readFloatReg(reg_idx,
cpu->readFloatReg(flat_idx,
inst->readTid()));
} else {
reg_idx -= Ctrl_Base_DepTag;
DPRINTF(InOrderUseDef, "[tid:%i]: Reading Misc Reg %i "
"from Register File:%i.\n",
tid,
reg_idx,
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
" (%i) from Register File:%i.\n",
tid, seq_num,
reg_idx, flat_idx,
cpu->readMiscReg(reg_idx,
inst->readTid()));
inst->setIntSrc(ud_idx,
@@ -220,9 +221,9 @@ UseDefUnit::execute(int slot_idx)
regFileReads++;
ud_req->done();
} else {
DPRINTF(InOrderUseDef, "[tid:%i]: Unable to read because "
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Unable to read because "
"of [sn:%i] hasnt read it's registers yet.\n",
tid, outReadSeqNum[tid]);
tid, seq_num, outReadSeqNum[tid]);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting for "
"[sn:%i] to write\n",
tid, outReadSeqNum[tid]);
@@ -231,8 +232,9 @@ UseDefUnit::execute(int slot_idx)
} else {
// Look for forwarding opportunities
DynInstPtr forward_inst = regDepMap[tid]->canForward(reg_idx,
inst);
DynInstPtr forward_inst = regDepMap[tid]->canForward(flat_idx,
inst,
reg_idx);
if (forward_inst) {
@@ -242,9 +244,9 @@ UseDefUnit::execute(int slot_idx)
if (reg_idx < FP_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
" reg value 0x%x from "
" reg %i (%i), value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
tid,
tid, reg_idx, flat_idx,
forward_inst->readIntResult(dest_reg_idx),
forward_inst->seqNum,
inst->seqNum, ud_idx);
@@ -253,9 +255,9 @@ UseDefUnit::execute(int slot_idx)
readIntResult(dest_reg_idx));
} else if (reg_idx < Ctrl_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
" reg value 0x%x from "
" reg %i (%i) value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
tid,
tid, reg_idx, flat_idx,
forward_inst->readFloatResult(dest_reg_idx),
forward_inst->seqNum, inst->seqNum, ud_idx);
inst->setFloatSrc(ud_idx,
@@ -263,9 +265,9 @@ UseDefUnit::execute(int slot_idx)
readFloatResult(dest_reg_idx));
} else {
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
" reg value 0x%x from "
" reg %i (%i) value 0x%x from "
"[sn:%i] to [sn:%i] source #%i.\n",
tid,
tid, reg_idx, flat_idx,
forward_inst->readIntResult(dest_reg_idx),
forward_inst->seqNum,
inst->seqNum, ud_idx);
@@ -302,69 +304,71 @@ UseDefUnit::execute(int slot_idx)
case WriteDestReg:
{
int reg_idx = inst->_destRegIdx[ud_idx];
RegIndex reg_idx = inst->_destRegIdx[ud_idx];
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, tid);
if (regDepMap[tid]->canWrite(reg_idx, inst)) {
DPRINTF(InOrderUseDef, "[tid:%i]: Flattening register idx %i &"
"Attempting to write to Register File.\n",
tid, reg_idx);
if (regDepMap[tid]->canWrite(flat_idx, inst)) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Flattening register idx %i "
"(%i) and Attempting to write to Register File.\n",
tid, seq_num, reg_idx, flat_idx);
uniqueRegMap[reg_idx] = true;
if (inst->seqNum <= outReadSeqNum[tid]) {
if (reg_idx < FP_Base_DepTag) {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Int. Result "
"0x%x to register idx %i.\n",
tid, inst->readIntResult(ud_idx), reg_idx);
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Int. Result "
"0x%x to register idx %i (%i).\n",
tid, seq_num, inst->readIntResult(ud_idx),
reg_idx, flat_idx);
// Remove Dependencies
regDepMap[tid]->removeFront(reg_idx, inst);
regDepMap[tid]->removeFront(flat_idx, inst);
cpu->setIntReg(reg_idx,
cpu->setIntReg(flat_idx,
inst->readIntResult(ud_idx),
inst->readTid());
} else if(reg_idx < Ctrl_Base_DepTag) {
// Remove Dependencies
regDepMap[tid]->removeFront(reg_idx, inst);
regDepMap[tid]->removeFront(flat_idx, inst);
reg_idx -= FP_Base_DepTag;
if (inst->resultType(ud_idx) ==
InOrderDynInst::Integer) {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing FP-Bits "
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing FP-Bits "
"Result 0x%x (bits:0x%x) to register "
"idx %i.\n",
tid,
"idx %i (%i).\n",
tid, seq_num,
inst->readFloatResult(ud_idx),
inst->readIntResult(ud_idx),
reg_idx);
reg_idx, flat_idx);
// Check for FloatRegBits Here
cpu->setFloatRegBits(reg_idx,
cpu->setFloatRegBits(flat_idx,
inst->readIntResult(ud_idx),
inst->readTid());
} else if (inst->resultType(ud_idx) ==
InOrderDynInst::Float) {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Float "
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Float "
"Result 0x%x (bits:0x%x) to register "
"idx %i.\n",
tid, inst->readFloatResult(ud_idx),
"idx %i (%i).\n",
tid, seq_num, inst->readFloatResult(ud_idx),
inst->readIntResult(ud_idx),
reg_idx);
reg_idx, flat_idx);
cpu->setFloatReg(reg_idx,
cpu->setFloatReg(flat_idx,
inst->readFloatResult(ud_idx),
inst->readTid());
} else if (inst->resultType(ud_idx) ==
InOrderDynInst::Double) {
DPRINTF(InOrderUseDef, "[tid:%i]: Writing Double "
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Writing Double "
"Result 0x%x (bits:0x%x) to register "
"idx %i.\n",
tid,
"idx %i (%i).\n",
tid, seq_num,
inst->readFloatResult(ud_idx),
inst->readIntResult(ud_idx),
reg_idx);
reg_idx, flat_idx);
// Check for FloatRegBits Here
cpu->setFloatReg(reg_idx,
cpu->setFloatReg(flat_idx,
inst->readFloatResult(ud_idx),
inst->readTid());
} else {
@@ -378,7 +382,7 @@ UseDefUnit::execute(int slot_idx)
tid, inst->readIntResult(ud_idx), reg_idx);
// Remove Dependencies
regDepMap[tid]->removeFront(reg_idx, inst);
regDepMap[tid]->removeFront(flat_idx, inst);
reg_idx -= Ctrl_Base_DepTag;
@@ -400,9 +404,9 @@ UseDefUnit::execute(int slot_idx)
ud_req->done(false);
}
} else {
DPRINTF(InOrderUseDef, "[tid:%i]: Dest. register idx: %i is "
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Dest. register idx: %i is "
"not ready to write.\n",
tid, reg_idx);
tid, seq_num, reg_idx);
DPRINTF(InOrderStall, "STALL: [tid:%i]: waiting to write "
"register (idx=%i)\n",
tid, reg_idx);

1
src/cpu/inorder/resources/use_def.hh
View File

@@ -46,6 +46,7 @@
class UseDefUnit : public Resource {
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
typedef TheISA::RegIndex RegIndex;
enum Command {
ReadSrcReg,

38
src/cpu/inorder/thread_context.cc
View File

@@ -117,7 +117,7 @@ InOrderThreadContext::activate(int delay)
thread->setStatus(ThreadContext::Active);
cpu->activateContext(thread->readTid(), delay);
cpu->activateContext(thread->threadId(), delay);
}
@@ -131,7 +131,7 @@ InOrderThreadContext::suspend(int delay)
return;
thread->setStatus(ThreadContext::Suspended);
cpu->suspendContext(thread->readTid(), delay);
cpu->suspendContext(thread->threadId(), delay);
}
void
@@ -144,7 +144,7 @@ InOrderThreadContext::halt(int delay)
return;
thread->setStatus(ThreadContext::Halted);
cpu->haltContext(thread->readTid(), delay);
cpu->haltContext(thread->threadId(), delay);
}
@@ -182,25 +182,33 @@ InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
void
InOrderThreadContext::clearArchRegs()
{}
{
cpu->isa[thread->threadId()].clear();
}
uint64_t
InOrderThreadContext::readIntReg(int reg_idx)
{
return cpu->readIntReg(reg_idx, thread->readTid());
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
return cpu->readIntReg(reg_idx, tid);
}
FloatReg
InOrderThreadContext::readFloatReg(int reg_idx)
{
return cpu->readFloatReg(reg_idx, thread->readTid());
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
return cpu->readFloatReg(reg_idx, tid);
}
FloatRegBits
InOrderThreadContext::readFloatRegBits(int reg_idx)
{
return cpu->readFloatRegBits(reg_idx, thread->readTid());
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
return cpu->readFloatRegBits(reg_idx, tid);
}
uint64_t
@@ -212,19 +220,25 @@ InOrderThreadContext::readRegOtherThread(int reg_idx, ThreadID tid)
void
InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
{
cpu->setIntReg(reg_idx, val, thread->readTid());
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
cpu->setIntReg(reg_idx, val, tid);
}
void
InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
{
cpu->setFloatReg(reg_idx, val, thread->readTid());
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
cpu->setFloatReg(reg_idx, val, tid);
}
void
InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
{
cpu->setFloatRegBits(reg_idx, val, thread->readTid());
ThreadID tid = thread->threadId();
reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
cpu->setFloatRegBits(reg_idx, val, tid);
}
void
@@ -237,11 +251,11 @@ InOrderThreadContext::setRegOtherThread(int misc_reg, const MiscReg &val,
void
InOrderThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
}
void
InOrderThreadContext::setMiscReg(int misc_reg, const MiscReg &val)
{
cpu->setMiscReg(misc_reg, val, thread->readTid());
cpu->setMiscReg(misc_reg, val, thread->threadId());
}

26
src/cpu/inorder/thread_context.hh
View File

@@ -175,7 +175,7 @@ class InOrderThreadContext : public ThreadContext
void unserialize(Checkpoint *cp, const std::string &section);
/** Returns this thread's ID number. */
int getThreadNum() { return thread->readTid(); }
int getThreadNum() { return thread->threadId(); }
/** Copies the architectural registers from another TC into this TC. */
void copyArchRegs(ThreadContext *src_tc);
@@ -205,29 +205,29 @@ class InOrderThreadContext : public ThreadContext
/** Reads this thread's PC. */
TheISA::PCState pcState()
{ return cpu->pcState(thread->readTid()); }
{ return cpu->pcState(thread->threadId()); }
/** Sets this thread's PC. */
void pcState(const TheISA::PCState &val)
{ cpu->pcState(val, thread->readTid()); }
{ cpu->pcState(val, thread->threadId()); }
Addr instAddr()
{ return cpu->instAddr(thread->readTid()); }
{ return cpu->instAddr(thread->threadId()); }
Addr nextInstAddr()
{ return cpu->nextInstAddr(thread->readTid()); }
{ return cpu->nextInstAddr(thread->threadId()); }
MicroPC microPC()
{ return cpu->microPC(thread->readTid()); }
{ return cpu->microPC(thread->threadId()); }
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg)
{ return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
{ return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
MiscReg readMiscReg(int misc_reg)
{ return cpu->readMiscReg(misc_reg, thread->readTid()); }
{ return cpu->readMiscReg(misc_reg, thread->threadId()); }
/** Sets a misc. register. */
void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
@@ -237,16 +237,16 @@ class InOrderThreadContext : public ThreadContext
void setMiscReg(int misc_reg, const MiscReg &val);
int flattenIntIndex(int reg)
{ return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
{ return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
int flattenFloatIndex(int reg)
{ return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
{ return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
void activateContext(int delay)
{ cpu->activateContext(thread->readTid(), delay); }
{ cpu->activateContext(thread->threadId(), delay); }
void deallocateContext()
{ cpu->deallocateContext(thread->readTid()); }
{ cpu->deallocateContext(thread->threadId()); }
/** Returns the number of consecutive store conditional failures. */
// @todo: Figure out where these store cond failures should go.
@@ -268,7 +268,7 @@ class InOrderThreadContext : public ThreadContext
#if !FULL_SYSTEM
/** Executes a syscall in SE mode. */
void syscall(int64_t callnum)
{ return cpu->syscall(callnum, thread->readTid()); }
{ return cpu->syscall(callnum, thread->threadId()); }
#endif
/** Reads the funcExeInst counter. */

4
src/cpu/inorder/thread_state.hh
View File

@@ -104,10 +104,6 @@ class InOrderThreadState : public ThreadState {
/** Returns a pointer to the TC of this thread. */
ThreadContext *getTC() { return tc; }
/** Return the thread id */
int readTid() { return threadId(); }
/** Is last instruction graduated a branch? */
bool lastGradIsBranch;