arch,cpu: Centralize the single arch CPU Simobject files.

The way these were set up, there would be a conflict between SimObject
files with the same name set up for different ISAs.

This change creates a single file which tries to determine how many ISAs
are enabled, and if there is exactly one, it creates a backwards
compatible alias for the ISA specific CPU types.

Change-Id: Iab358c2880d49222e814a98354c81d0f306fe1fc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52493
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/cpu/o3/SConscript

@@ -76,3 +76,7 @@ if not env['CONF']['USE_NULL_ISA']:
 
     SimObject('BaseO3Checker.py', sim_objects=['BaseO3Checker'])
     Source('checker.cc')
+
+    # For backwards compatibility
+    SimObject('O3CPU.py', sim_objects=[])
+    SimObject('O3Checker.py', sim_objects=[])