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arch-x86: Adding LDDQU instruction

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Tested with simple c binaries.

Signed-off-by: marjanfariborz <mfariborz@ucdavis.edu>
Change-Id: I2f0852b136f966381d29af523e8ffdbca795afcd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23262
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
marjanfariborz
2019-12-02 15:03:02 -08:00
committed by Hoa Nguyen
parent f7cb03f493
commit 18cbc34a56
2 changed files with 12 additions and 2 deletions
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2
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View File

@@ -1067,7 +1067,7 @@
}
// repne (0xF2)
0x8: decode OPCODE_OP_BOTTOM3 {
0x0: WarnUnimpl::lddqu_Vo_Mo();
0x0: LDDQU(Vo,Mq);
default: UD2();
}
default: UD2();

12
src/arch/x86/isa/insts/simd128/integer/data_transfer/move.py
View File

@@ -123,5 +123,15 @@ def macroop MOVDQU_P_XMM {
stfp xmml, seg, riprel, "DISPLACEMENT", dataSize=8
stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
};
def macroop LDDQU_XMM_M {
ldfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
};
def macroop LDDQU_XMM_P {
rdip t7
ldfp xmml, seg, sib, "DISPLACEMENT", dataSize=8
ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
};
'''
# LDDQU