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arch-arm: Disable HVC when SCR_EL3.HCE is 0

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This was already implemented for AArch32 but it had been wrongly
removed by:

https://gem5-review.googlesource.com/c/public/gem5/+/31394

Change-Id: Ida303d5ccb5d8568ca4e7faaedf9b4efd1cd88b5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32636
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2020-08-11 14:11:29 +01:00
parent 735cf323b5
commit 1899320462
1 changed files with 4 additions and 1 deletions
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5
src/arch/arm/isa/insts/misc.isa
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@@ -119,12 +119,15 @@ let {{
exec_output += PredOpExecute.subst(smcIop)
hvcCode = '''
HCR hcr = Hcr;
CPSR cpsr = Cpsr;
SCR scr = Scr;
// Filter out the various cases where this instruction isn't defined
if (!FullSystem || !ArmSystem::haveVirtualization(xc->tcBase()) ||
(cpsr.mode == MODE_USER) ||
(isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase()))) {
(isSecure(xc->tcBase()) && !IsSecureEL2Enabled(xc->tcBase())) ||
(ArmSystem::haveSecurity(xc->tcBase()) ? !scr.hce : hcr.hcd)) {
fault = disabledFault();
} else {
fault = std::make_shared<HypervisorCall>(machInst, imm);