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stats: update Minor stats due to PF bug fix

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A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5)
inadvertently fixed a bug in the Minor CPU model which caused it to treat
software prefetches as regular loads.  Prior to this changeset, Minor
did an ad-hoc generation of memory commands that left out the PF check;
because it now uses the common code that the other CPU models use,
it generates prefetches properly.  These stat changes reflect the fact
that the Minor model now issues SoftPFReqs.
This commit is contained in:
Steve Reinhardt
2015-03-19 08:41:32 -04:00
parent f1c3fda965
commit 1483496803
48 changed files with 9893 additions and 10233 deletions
Download Patch File Download Diff File Expand all files Collapse all files

113
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/dist/binaries/boot_emm.arm
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,20 +30,21 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.realview.nvmem system.physmem system.realview.vram
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5.ext/tests/halt.sh
readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -86,7 +87,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/dist/disks/linux-aarch32-ael.img
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -186,6 +187,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -220,6 +222,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
@@ -237,7 +240,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
@@ -645,6 +647,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
@@ -713,6 +716,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
@@ -730,7 +734,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
@@ -755,6 +758,7 @@ children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
@@ -776,19 +780,27 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
cross_pages=false
data_accesses_only=false
degree=8
eventq_index=0
inst_tagged=true
latency=1
on_miss_only=false
on_prefetch=true
on_read_only=false
serial_squash=false
size=100
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
sys=system
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
@@ -805,13 +817,16 @@ size=1048576
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
@@ -906,6 +921,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -940,6 +956,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
@@ -957,7 +974,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
@@ -1365,6 +1381,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
@@ -1433,6 +1450,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
@@ -1450,7 +1468,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
@@ -1475,6 +1492,7 @@ children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
@@ -1496,19 +1514,27 @@ mem_side=system.toL2Bus.slave[1]
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
cross_pages=false
data_accesses_only=false
degree=8
eventq_index=0
inst_tagged=true
latency=1
on_miss_only=false
on_prefetch=true
on_read_only=false
serial_squash=false
size=100
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
sys=system
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
@@ -1525,13 +1551,16 @@ size=1048576
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
@@ -1562,9 +1591,11 @@ sys=system
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
width=8
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -1575,6 +1606,7 @@ children=tags
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
@@ -1610,6 +1642,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -1644,11 +1677,14 @@ type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -1698,7 +1734,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -2409,11 +2445,14 @@ port=3456
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=8
width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side

0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr Normal file → Executable file
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18
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout Normal file → Executable file
View File

@@ -1,17 +1,17 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 31 2014 10:01:44
gem5 started Oct 31 2014 11:28:00
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu0.isa: ISA system set to: 0x5a2b680 0x5a2b680
0: system.cpu1.isa: ISA system set to: 0x5a2b680 0x5a2b680
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu0.isa: ISA system set to: 0x36c6a30 0x36c6a30
0: system.cpu1.isa: ISA system set to: 0x36c6a30 0x36c6a30
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2843665155500 because m5_exit instruction encountered
Exiting @ tick 2846097440000 because m5_exit instruction encountered

4386
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
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File diff suppressed because it is too large Load Diff

8
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal
View File

@@ -158,10 +158,10 @@ ata1.00: 1048320 sectors, multi 0: LBA
hw-breakpoint: Debug register access (0xee003e17) caused undefined instruction on CPU 0
Serial: AMBA PL011 UART driver
1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
console [ttyAMA0] enabled
console [ttyAMA0] enabled
@@ -199,7 +199,7 @@ oprofile: using timer interrupt.
vgaarb: loaded
SCSI subsystem initialized
libata version 3.00 loaded.
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
@@ -209,6 +209,6 @@ Freeing unused kernel memory: 292K (806aa000 - 806f3000)
Switched to clocksource arch_sys_counter
NET: Registered protocol family 2
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP: reno registered
TCP: reno registered

43
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/dist/binaries/boot_emm.arm
boot_loader=/dist/m5/system/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
dtb_filename=/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,20 +30,21 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel=/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.realview.vram system.physmem system.realview.nvmem
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5.ext/tests/halt.sh
readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -86,7 +87,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/dist/disks/linux-aarch32-ael.img
image_file=/dist/m5/system/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
@@ -186,6 +187,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -220,6 +222,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -237,7 +240,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -645,6 +647,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -713,6 +716,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -730,7 +734,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -755,6 +758,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -788,13 +792,16 @@ size=4194304
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -825,9 +832,11 @@ sys=system
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
width=8
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -838,6 +847,7 @@ children=tags
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
@@ -872,11 +882,14 @@ type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -926,7 +939,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8

0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr Normal file → Executable file
View File

16
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout Normal file → Executable file
View File

@@ -1,16 +1,16 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 31 2014 10:01:44
gem5 started Oct 31 2014 11:27:21
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /work/gem5.ext/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu.isa: ISA system set to: 0x5580680 0x5580680
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
0: system.cpu.isa: ISA system set to: 0x3fbcc30 0x3fbcc30
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
info: Loading DTB file: /dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: Read CNTFREQ_EL0 frequency
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
@@ -28,4 +28,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
Exiting @ tick 2852222670000 because m5_exit instruction encountered
Exiting @ tick 2852831758500 because m5_exit instruction encountered

1679
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
View File

File diff suppressed because it is too large Load Diff

6
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal
View File

@@ -193,7 +193,7 @@ oprofile: using timer interrupt.
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
Advanced Linux Sound Architecture Driver Initialized.
Advanced Linux Sound Architecture Driver Initialized.
Switched to clocksource arch_sys_counter
NET: Registered protocol family 2
TCP established hash table entries: 2048 (order: 1, 8192 bytes)
@@ -203,6 +203,6 @@ Freeing unused kernel memory: 292K (806aa000 - 806f3000)
UDP hash table entries: 256 (order: 1, 8192 bytes)
UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
NET: Registered protocol family 1
RPC: Registered named UNIX socket transport module.
RPC: Registered named UNIX socket transport module.
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp transport module.

113
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
boot_loader=/dist/m5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,20 +30,21 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.vram system.realview.nvmem
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5.latest/tests/halt.sh
readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -86,7 +87,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
@@ -186,6 +187,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -220,6 +222,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
@@ -237,7 +240,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
@@ -645,6 +647,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
@@ -713,6 +716,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
@@ -730,7 +734,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
@@ -755,6 +758,7 @@ children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
@@ -776,19 +780,27 @@ mem_side=system.toL2Bus.slave[0]
[system.cpu0.l2cache.prefetcher]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
cross_pages=false
data_accesses_only=false
degree=8
eventq_index=0
inst_tagged=true
latency=1
on_miss_only=false
on_prefetch=true
on_read_only=false
serial_squash=false
size=100
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
sys=system
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
use_master_id=true
[system.cpu0.l2cache.tags]
@@ -805,13 +817,16 @@ size=1048576
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
@@ -906,6 +921,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -940,6 +956,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
@@ -957,7 +974,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
@@ -1365,6 +1381,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
@@ -1433,6 +1450,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
@@ -1450,7 +1468,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
@@ -1475,6 +1492,7 @@ children=prefetcher tags
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
@@ -1496,19 +1514,27 @@ mem_side=system.toL2Bus.slave[1]
[system.cpu1.l2cache.prefetcher]
type=StridePrefetcher
cache_snoop=false
clk_domain=system.cpu_clk_domain
cross_pages=false
data_accesses_only=false
degree=8
eventq_index=0
inst_tagged=true
latency=1
on_miss_only=false
on_prefetch=true
on_read_only=false
serial_squash=false
size=100
max_conf=7
min_conf=0
on_data=true
on_inst=true
on_miss=false
on_read=true
on_write=true
queue_filter=true
queue_size=32
queue_squash=true
start_conf=4
sys=system
table_assoc=4
table_sets=16
tag_prefetch=true
thresh_conf=4
use_master_id=true
[system.cpu1.l2cache.tags]
@@ -1525,13 +1551,16 @@ size=1048576
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
@@ -1562,9 +1591,11 @@ sys=system
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
width=8
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -1575,6 +1606,7 @@ children=tags
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
@@ -1610,6 +1642,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -1644,11 +1677,14 @@ type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
@@ -1698,7 +1734,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -2409,11 +2445,14 @@ port=3456
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=8
width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side

0
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simerr Normal file → Executable file
View File

18
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/simout Normal file → Executable file
View File

@@ -1,17 +1,17 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 29 2014 09:18:22
gem5 started Oct 29 2014 10:35:48
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
0: system.cpu0.isa: ISA system set to: 0x5394b00 0x5394b00
0: system.cpu1.isa: ISA system set to: 0x5394b00 0x5394b00
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821
0: system.cpu0.isa: ISA system set to: 0x3d33a20 0x3d33a20
0: system.cpu1.isa: ISA system set to: 0x3d33a20 0x3d33a20
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47349475204500 because m5_exit instruction encountered
Exiting @ tick 47397610926500 because m5_exit instruction encountered

4902
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt
View File

File diff suppressed because it is too large Load Diff

254
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
View File

@@ -32,135 +32,135 @@
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000019] Console: colour dummy device 80x25
[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000022] pid_max: default: 32768 minimum: 301
[ 0.000033] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000034] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000131] hw perfevents: no hardware support available
[ 0.060036] CPU1: Booted secondary processor
[ 1.080071] CPU2: failed to come online
[ 2.100137] CPU3: failed to come online
[ 2.100139] Brought up 2 CPUs
[ 2.100140] SMP: Total of 2 processors activated.
[ 2.100190] devtmpfs: initialized
[ 2.100793] atomic64_test: passed
[ 2.100838] regulator-dummy: no parameters
[ 2.101214] NET: Registered protocol family 16
[ 2.101343] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 2.101351] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 2.101748] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 2.101750] Serial: AMBA PL011 UART driver
[ 2.101922] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 2.101956] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 2.102494] console [ttyAMA0] enabled
[ 2.102553] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 2.102585] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 2.102617] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 2.102647] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 2.140272] 3V3: 3300 mV
[ 2.140314] vgaarb: loaded
[ 2.140359] SCSI subsystem initialized
[ 2.140388] libata version 3.00 loaded.
[ 2.140440] usbcore: registered new interface driver usbfs
[ 2.140458] usbcore: registered new interface driver hub
[ 2.140480] usbcore: registered new device driver usb
[ 2.140506] pps_core: LinuxPPS API ver. 1 registered
[ 2.140514] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 2.140532] PTP clock support registered
[ 2.140657] Switched to clocksource arch_sys_counter
[ 2.141767] NET: Registered protocol family 2
[ 2.141832] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 2.141848] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 2.141863] TCP: Hash tables configured (established 2048 bind 2048)
[ 2.141883] TCP: reno registered
[ 2.141889] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 2.141901] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 2.141933] NET: Registered protocol family 1
[ 2.141985] RPC: Registered named UNIX socket transport module.
[ 2.141995] RPC: Registered udp transport module.
[ 2.142003] RPC: Registered tcp transport module.
[ 2.142011] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.142022] PCI: CLS 0 bytes, default 64
[ 2.142178] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 2.142262] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 2.144252] fuse init (API version 7.23)
[ 2.144348] msgmni has been set to 469
[ 2.144441] io scheduler noop registered
[ 2.144502] io scheduler cfq registered (default)
[ 2.144877] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.144889] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.144900] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 2.144912] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.144921] pci_bus 0000:00: scanning bus
[ 2.144930] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.144942] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 2.144956] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.144993] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 2.145004] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.145014] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.145025] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 2.145035] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.145045] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.145056] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.145094] pci_bus 0000:00: fixups for bus
[ 2.145101] pci_bus 0000:00: bus scan returning with max=00
[ 2.145112] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.145130] pci 0000:00:00.0: fixup irq: got 33
[ 2.145138] pci 0000:00:00.0: assigning IRQ 33
[ 2.145148] pci 0000:00:01.0: fixup irq: got 34
[ 2.145156] pci 0000:00:01.0: assigning IRQ 34
[ 2.145166] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.145178] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.145191] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.145203] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.145214] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.145225] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.145236] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.145246] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.145736] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.145999] ata_piix 0000:00:01.0: version 2.13
[ 2.146009] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.146029] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.146283] scsi0 : ata_piix
[ 2.146361] scsi1 : ata_piix
[ 2.146393] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.146405] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.146514] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.146526] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.146540] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.146551] e1000 0000:00:00.0: enabling bus mastering
[ 2.290688] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290697] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290723] ata1.00: configured for UDMA/33
[ 2.290764] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.290877] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.290883] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.290933] sd 0:0:0:0: [sda] Write Protect is off
[ 2.290942] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.290962] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.291097] sda: sda1
[ 2.291216] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.410964] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.410977] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.411000] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.411009] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411031] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411042] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.411120] usbcore: registered new interface driver usb-storage
[ 2.411175] mousedev: PS/2 mouse device common for all mice
[ 2.411347] usbcore: registered new interface driver usbhid
[ 2.411357] usbhid: USB HID core driver
[ 2.411384] TCP: cubic registered
[ 2.411391] NET: Registered protocol family 17
[ 2.411706] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.411738] devtmpfs: mounted
[ 2.411771] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
[ 0.000024] Console: colour dummy device 80x25
[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000028] pid_max: default: 32768 minimum: 301
[ 0.000040] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000041] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000162] hw perfevents: no hardware support available
[ 0.060041] CPU1: Booted secondary processor
[ 1.080077] CPU2: failed to come online
[ 2.100147] CPU3: failed to come online
[ 2.100150] Brought up 2 CPUs
[ 2.100151] SMP: Total of 2 processors activated.
[ 2.100222] devtmpfs: initialized
[ 2.100720] atomic64_test: passed
[ 2.100765] regulator-dummy: no parameters
[ 2.101110] NET: Registered protocol family 16
[ 2.101240] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 2.101248] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 2.101774] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 2.101778] Serial: AMBA PL011 UART driver
[ 2.101977] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 2.102014] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 2.102559] console [ttyAMA0] enabled
[ 2.102714] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 2.102776] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 2.102840] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 2.102896] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 2.140326] 3V3: 3300 mV
[ 2.140386] vgaarb: loaded
[ 2.140451] SCSI subsystem initialized
[ 2.140500] libata version 3.00 loaded.
[ 2.140582] usbcore: registered new interface driver usbfs
[ 2.140606] usbcore: registered new interface driver hub
[ 2.140634] usbcore: registered new device driver usb
[ 2.140679] pps_core: LinuxPPS API ver. 1 registered
[ 2.140690] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 2.140713] PTP clock support registered
[ 2.140890] Switched to clocksource arch_sys_counter
[ 2.142410] NET: Registered protocol family 2
[ 2.142497] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 2.142513] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 2.142530] TCP: Hash tables configured (established 2048 bind 2048)
[ 2.142553] TCP: reno registered
[ 2.142559] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 2.142571] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 2.142606] NET: Registered protocol family 1
[ 2.142648] RPC: Registered named UNIX socket transport module.
[ 2.142658] RPC: Registered udp transport module.
[ 2.142666] RPC: Registered tcp transport module.
[ 2.142674] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.142686] PCI: CLS 0 bytes, default 64
[ 2.142917] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 2.143025] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 2.145169] fuse init (API version 7.23)
[ 2.145284] msgmni has been set to 469
[ 2.145389] io scheduler noop registered
[ 2.145440] io scheduler cfq registered (default)
[ 2.145841] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 2.145854] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 2.145865] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 2.145877] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 2.145887] pci_bus 0000:00: scanning bus
[ 2.145897] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 2.145910] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 2.145924] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.145958] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 2.145969] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 2.145980] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 2.145990] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 2.146000] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 2.146011] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 2.146022] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 2.146056] pci_bus 0000:00: fixups for bus
[ 2.146064] pci_bus 0000:00: bus scan returning with max=00
[ 2.146076] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 2.146095] pci 0000:00:00.0: fixup irq: got 33
[ 2.146103] pci 0000:00:00.0: assigning IRQ 33
[ 2.146113] pci 0000:00:01.0: fixup irq: got 34
[ 2.146121] pci 0000:00:01.0: assigning IRQ 34
[ 2.146133] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 2.146145] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 2.146158] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 2.146170] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 2.146181] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 2.146192] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 2.146203] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 2.146214] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 2.146861] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 2.147132] ata_piix 0000:00:01.0: version 2.13
[ 2.147142] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 2.147165] ata_piix 0000:00:01.0: enabling bus mastering
[ 2.147427] scsi0 : ata_piix
[ 2.147508] scsi1 : ata_piix
[ 2.147536] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 2.147548] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 2.147650] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 2.147662] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 2.147676] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 2.147687] e1000 0000:00:00.0: enabling bus mastering
[ 2.290931] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 2.290941] ata1.00: 2096640 sectors, multi 0: LBA
[ 2.290968] ata1.00: configured for UDMA/33
[ 2.291021] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 2.291157] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 2.291201] sd 0:0:0:0: [sda] Write Protect is off
[ 2.291210] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 2.291229] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 2.291303] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 2.291385] sda: sda1
[ 2.291511] sd 0:0:0:0: [sda] Attached SCSI disk
[ 2.411191] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 2.411204] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 2.411225] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 2.411235] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 2.411255] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 2.411267] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 2.411336] usbcore: registered new interface driver usb-storage
[ 2.411399] mousedev: PS/2 mouse device common for all mice
[ 2.411553] usbcore: registered new interface driver usbhid
[ 2.411563] usbhid: USB HID core driver
[ 2.411592] TCP: cubic registered
[ 2.411599] NET: Registered protocol family 17
[ 2.411953] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 2.411989] devtmpfs: mounted
[ 2.412026] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 2.449963] udevd[609]: starting version 182
[ 2.450394] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 2.513589] random: dd urandom read with 17 bits of entropy available
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014

43
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/config.ini
View File

@@ -12,12 +12,12 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
boot_loader=/dist/m5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
dtb_filename=/dist/m5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
@@ -30,20 +30,21 @@ have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
kernel=/dist/m5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.realview.vram system.physmem system.realview.nvmem
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
readfile=/work/gem5.latest/tests/halt.sh
readfile=/z/stever/hg/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
@@ -86,7 +87,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
image_file=/dist/m5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
@@ -186,6 +187,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -220,6 +222,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -237,7 +240,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -645,6 +647,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -713,6 +716,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -730,7 +734,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -755,6 +758,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -788,13 +792,16 @@ size=4194304
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -825,9 +832,11 @@ sys=system
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=1
frontend_latency=2
response_latency=2
use_default_range=true
width=8
width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
@@ -838,6 +847,7 @@ children=tags
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
@@ -872,11 +882,14 @@ type=CoherentXBar
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
@@ -926,7 +939,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8

0
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simerr Normal file → Executable file
View File

16
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/simout Normal file → Executable file
View File

@@ -1,16 +1,16 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Oct 29 2014 09:18:22
gem5 started Oct 29 2014 10:29:11
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
0: system.cpu.isa: ISA system set to: 0x5c61b00 0x5c61b00
info: kernel located at: /dist/m5/system/binaries/vmlinux.aarch64.20140821
0: system.cpu.isa: ISA system set to: 0x404afc0 0x404afc0
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: /projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Loading DTB file: /dist/m5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51727209160500 because m5_exit instruction encountered
Exiting @ tick 51609998980000 because m5_exit instruction encountered

1955
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt
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File diff suppressed because it is too large Load Diff

248
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/system.terminal
View File

@@ -34,133 +34,133 @@
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[ 0.000026] Console: colour dummy device 80x25
[ 0.000029] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[ 0.000030] pid_max: default: 32768 minimum: 301
[ 0.000044] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000046] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000174] hw perfevents: no hardware support available
[ 1.060092] CPU1: failed to come online
[ 2.080180] CPU2: failed to come online
[ 3.100268] CPU3: failed to come online
[ 3.100271] Brought up 1 CPUs
[ 3.100273] SMP: Total of 1 processors activated.
[ 3.100341] devtmpfs: initialized
[ 3.101042] atomic64_test: passed
[ 3.101098] regulator-dummy: no parameters
[ 3.101606] NET: Registered protocol family 16
[ 3.101773] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.101783] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.102080] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.102082] Serial: AMBA PL011 UART driver
[ 3.102304] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.102346] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.102874] console [ttyAMA0] enabled
[ 3.102953] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 3.102989] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 3.103025] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 3.103058] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 3.130671] 3V3: 3300 mV
[ 3.130723] vgaarb: loaded
[ 3.130779] SCSI subsystem initialized
[ 3.130831] libata version 3.00 loaded.
[ 3.130889] usbcore: registered new interface driver usbfs
[ 3.130910] usbcore: registered new interface driver hub
[ 3.130951] usbcore: registered new device driver usb
[ 3.130982] pps_core: LinuxPPS API ver. 1 registered
[ 3.130991] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.131010] PTP clock support registered
[ 3.131159] Switched to clocksource arch_sys_counter
[ 3.132645] NET: Registered protocol family 2
[ 3.132738] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 3.132758] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 3.132782] TCP: Hash tables configured (established 2048 bind 2048)
[ 3.132801] TCP: reno registered
[ 3.132808] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132822] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132867] NET: Registered protocol family 1
[ 3.132915] RPC: Registered named UNIX socket transport module.
[ 3.132925] RPC: Registered udp transport module.
[ 3.132933] RPC: Registered tcp transport module.
[ 3.132941] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 3.132953] PCI: CLS 0 bytes, default 64
[ 3.133150] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 3.133293] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.135708] fuse init (API version 7.23)
[ 3.135822] msgmni has been set to 469
[ 3.138911] io scheduler noop registered
[ 3.138984] io scheduler cfq registered (default)
[ 3.139445] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.139457] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.139469] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 3.139481] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.139491] pci_bus 0000:00: scanning bus
[ 3.139501] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.139514] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.139528] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.139574] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.139586] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 3.139597] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.139607] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.139618] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.139629] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.139640] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.139683] pci_bus 0000:00: fixups for bus
[ 3.139691] pci_bus 0000:00: bus scan returning with max=00
[ 3.139703] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.139723] pci 0000:00:00.0: fixup irq: got 33
[ 3.139731] pci 0000:00:00.0: assigning IRQ 33
[ 3.139742] pci 0000:00:01.0: fixup irq: got 34
[ 3.139750] pci 0000:00:01.0: assigning IRQ 34
[ 3.139762] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.139775] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.139788] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.139801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.139812] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.139823] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.139835] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.139846] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.140504] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.140842] ata_piix 0000:00:01.0: version 2.13
[ 3.140853] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.140875] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.141475] scsi0 : ata_piix
[ 3.141603] scsi1 : ata_piix
[ 3.141641] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.141654] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.141783] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.141795] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.141811] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.141823] e1000 0000:00:00.0: enabling bus mastering
[ 3.301188] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.301198] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.301227] ata1.00: configured for UDMA/33
[ 3.301281] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.301428] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.301457] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.301505] sd 0:0:0:0: [sda] Write Protect is off
[ 3.301514] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.301538] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 3.301694] sda: sda1
[ 3.301852] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.421479] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.421492] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.421515] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.421525] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.421549] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.421561] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.421651] usbcore: registered new interface driver usb-storage
[ 3.421719] mousedev: PS/2 mouse device common for all mice
[ 3.421922] usbcore: registered new interface driver usbhid
[ 3.421931] usbhid: USB HID core driver
[ 3.421965] TCP: cubic registered
[ 3.421972] NET: Registered protocol family 17
[ 3.422387] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.422426] devtmpfs: mounted
[ 0.000031] pid_max: default: 32768 minimum: 301
[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
[ 0.000180] hw perfevents: no hardware support available
[ 1.060095] CPU1: failed to come online
[ 2.080185] CPU2: failed to come online
[ 3.100275] CPU3: failed to come online
[ 3.100278] Brought up 1 CPUs
[ 3.100280] SMP: Total of 1 processors activated.
[ 3.100349] devtmpfs: initialized
[ 3.100980] atomic64_test: passed
[ 3.101035] regulator-dummy: no parameters
[ 3.101538] NET: Registered protocol family 16
[ 3.101703] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
[ 3.101713] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
[ 3.102141] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
[ 3.102147] Serial: AMBA PL011 UART driver
[ 3.102394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
[ 3.102440] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
[ 3.102971] console [ttyAMA0] enabled
[ 3.103068] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
[ 3.103104] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
[ 3.103141] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
[ 3.103175] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
[ 3.130690] 3V3: 3300 mV
[ 3.130742] vgaarb: loaded
[ 3.130800] SCSI subsystem initialized
[ 3.130851] libata version 3.00 loaded.
[ 3.130907] usbcore: registered new interface driver usbfs
[ 3.130928] usbcore: registered new interface driver hub
[ 3.130968] usbcore: registered new device driver usb
[ 3.130999] pps_core: LinuxPPS API ver. 1 registered
[ 3.131008] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 3.131027] PTP clock support registered
[ 3.131174] Switched to clocksource arch_sys_counter
[ 3.132602] NET: Registered protocol family 2
[ 3.132697] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
[ 3.132719] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
[ 3.132744] TCP: Hash tables configured (established 2048 bind 2048)
[ 3.132760] TCP: reno registered
[ 3.132768] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132782] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 3.132828] NET: Registered protocol family 1
[ 3.132876] RPC: Registered named UNIX socket transport module.
[ 3.132886] RPC: Registered udp transport module.
[ 3.132894] RPC: Registered tcp transport module.
[ 3.132902] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 3.132914] PCI: CLS 0 bytes, default 64
[ 3.133108] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 3.133253] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 3.135428] fuse init (API version 7.23)
[ 3.135535] msgmni has been set to 469
[ 3.138600] io scheduler noop registered
[ 3.138667] io scheduler cfq registered (default)
[ 3.139158] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
[ 3.139171] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
[ 3.139182] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
[ 3.139194] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 3.139204] pci_bus 0000:00: scanning bus
[ 3.139215] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
[ 3.139228] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
[ 3.139243] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.139286] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
[ 3.139299] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
[ 3.139310] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
[ 3.139320] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
[ 3.139331] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
[ 3.139342] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
[ 3.139353] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
[ 3.139394] pci_bus 0000:00: fixups for bus
[ 3.139403] pci_bus 0000:00: bus scan returning with max=00
[ 3.139414] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
[ 3.139435] pci 0000:00:00.0: fixup irq: got 33
[ 3.139444] pci 0000:00:00.0: assigning IRQ 33
[ 3.139455] pci 0000:00:01.0: fixup irq: got 34
[ 3.139463] pci 0000:00:01.0: assigning IRQ 34
[ 3.139475] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
[ 3.139488] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
[ 3.139501] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
[ 3.139514] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
[ 3.139525] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
[ 3.139537] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
[ 3.139548] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
[ 3.139559] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
[ 3.140184] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 3.140520] ata_piix 0000:00:01.0: version 2.13
[ 3.140531] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
[ 3.140555] ata_piix 0000:00:01.0: enabling bus mastering
[ 3.140911] scsi0 : ata_piix
[ 3.141038] scsi1 : ata_piix
[ 3.141075] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
[ 3.141087] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
[ 3.141242] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
[ 3.141254] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 3.141271] e1000 0000:00:00.0: enabling device (0000 -> 0002)
[ 3.141283] e1000 0000:00:00.0: enabling bus mastering
[ 3.301203] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
[ 3.301213] ata1.00: 2096640 sectors, multi 0: LBA
[ 3.301243] ata1.00: configured for UDMA/33
[ 3.301299] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
[ 3.301438] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 3.301467] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
[ 3.301514] sd 0:0:0:0: [sda] Write Protect is off
[ 3.301523] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.301547] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[ 3.301695] sda: sda1
[ 3.301842] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.421490] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
[ 3.421503] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
[ 3.421526] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
[ 3.421536] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
[ 3.421559] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
[ 3.421571] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 3.421656] usbcore: registered new interface driver usb-storage
[ 3.421723] mousedev: PS/2 mouse device common for all mice
[ 3.421911] usbcore: registered new interface driver usbhid
[ 3.421921] usbhid: USB HID core driver
[ 3.421955] TCP: cubic registered
[ 3.421963] NET: Registered protocol family 17
[ 3.422382] VFS: Mounted root (ext2 filesystem) on device 8:1.
[ 3.422420] devtmpfs: mounted
[ 3.422455] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
INIT: version 2.88 booting
Starting udev
[ 3.464515] udevd[607]: starting version 182
[ 3.464312] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
[ 3.594630] random: dd urandom read with 20 bits of entropy available
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014

25
tests/long/se/10.mcf/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -167,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -184,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -661,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -678,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -737,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -759,9 +763,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
max_stack_size=67108864
output=cout
@@ -792,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -827,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8

1
tests/long/se/10.mcf/ref/arm/linux/minor-timing/simerr Normal file → Executable file
View File

@@ -1 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections

14
tests/long/se/10.mcf/ref/arm/linux/minor-timing/simout Normal file → Executable file
View File

@@ -1,14 +1,12 @@
Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 7 2014 10:57:46
gem5 started May 7 2014 16:03:40
gem5 executing on cz3211bhr8
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x11aa5150
0: system.cpu.isa: ISA system set to: 0 0x45a0240
info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
@@ -26,4 +24,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
Exiting @ tick 61276704500 because target called exit()
Exiting @ tick 61589191500 because target called exit()

582
tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt
View File

@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.061593 # Number of seconds simulated
sim_ticks 61592600500 # Number of ticks simulated
final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_seconds 0.061589 # Number of seconds simulated
sim_ticks 61589191500 # Number of ticks simulated
final_tick 61589191500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 271325 # Simulator instruction rate (inst/s)
host_op_rate 272676 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 184448880 # Simulator tick rate (ticks/s)
host_mem_usage 445184 # Number of bytes of host memory used
host_seconds 333.93 # Real time elapsed on the host
host_inst_rate 169101 # Simulator instruction rate (inst/s)
host_op_rate 169943 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 114949938 # Simulator tick rate (ticks/s)
host_mem_usage 374724 # Number of bytes of host memory used
host_seconds 535.79 # Real time elapsed on the host
sim_insts 90602849 # Number of instructions simulated
sim_ops 91054080 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu
system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 805336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 15379322 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 16184658 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 805336 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 805336 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 805336 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 15379322 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 16184658 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15575 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue
@@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 61592506000 # Total gap between requests
system.physmem.totGap 61589097000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation
system.physmem.totQLat 77242000 # Total ticks spent queuing
system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::samples 1548 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 642.728682 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 437.613794 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 401.141843 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 250 16.15% 16.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 184 11.89% 28.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 91 5.88% 33.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 69 4.46% 38.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 77 4.97% 43.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 93 6.01% 49.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 43 2.78% 52.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 36 2.33% 54.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 705 45.54% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1548 # Bytes accessed per row activation
system.physmem.totQLat 76265750 # Total ticks spent queuing
system.physmem.totMemAccLat 368297000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers
system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst
system.physmem.avgQLat 4896.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 23646.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 14018 # Number of row buffer hits during reads
system.physmem.readRowHits 14017 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 3954575.02 # Average gap between requests
system.physmem.avgGap 3954356.15 # Average gap between requests
system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ)
system.physmem_0.actEnergy 6365520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 3473250 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.572046 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_0.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 2552305815 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 34710162000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 41358171225 # Total energy per rank (pJ)
system.physmem_0.averagePower 671.598278 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 57736612750 # Time in different power states
system.physmem_0.memoryStateTime::REF 2056340000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1792195250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ)
system.physmem_1.actEnergy 5322240 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2904000 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.509428 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states
system.physmem_1.refreshEnergy 4022201040 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 2572075980 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 34692811500 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 41352777360 # Total energy per rank (pJ)
system.physmem_1.averagePower 671.510839 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 57709022500 # Time in different power states
system.physmem_1.memoryStateTime::REF 2056340000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1820633500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 20789446 # Number of BP lookups
system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits
system.cpu.branchPred.lookups 20789992 # Number of BP lookups
system.cpu.branchPred.condPredicted 17092121 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 765794 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 8976081 # Number of BTB lookups
system.cpu.branchPred.BTBHits 8866607 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target.
system.cpu.branchPred.BTBHitPct 98.780381 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 62695 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -377,89 +377,97 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 442 # Number of system calls
system.cpu.numCycles 123185201 # number of cpu cycles simulated
system.cpu.numCycles 123178383 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 90602849 # Number of instructions committed
system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed
system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 2068275 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.359617 # CPI: cycles per instruction
system.cpu.ipc 0.735501 # IPC: instructions per cycle
system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped
system.cpu.cpi 1.359542 # CPI: cycles per instruction
system.cpu.ipc 0.735542 # IPC: instructions per cycle
system.cpu.tickCycles 109824698 # Number of cycles that the object actually ticked
system.cpu.idleCycles 13353685 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 946107 # number of replacements
system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 3616.117477 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26267654 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 27.644255 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_blocks::cpu.data 3616.117477 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.882841 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.882841 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 260 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2243 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 1593 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits
system.cpu.dcache.tags.tag_accesses 55463725 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 55463725 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 21598560 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 21598560 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 4660812 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 4660812 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits
system.cpu.dcache.overall_hits::total 26259649 # number of overall hits
system.cpu.dcache.demand_hits::cpu.data 26259372 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 26259372 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 26259880 # number of overall hits
system.cpu.dcache.overall_hits::total 26259880 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses
system.cpu.dcache.overall_misses::total 989105 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_misses::cpu.data 74169 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 74169 # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 989103 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 989103 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 989107 # number of overall misses
system.cpu.dcache.overall_misses::total 989107 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918328994 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 11918328994 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 2566867500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 2566867500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 14485196494 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 14485196494 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 14485196494 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 14485196494 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 22513494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 22513494 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 27248475 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 27248475 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 27248987 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 27248987 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.435780 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.435780 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34608.360636 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 34608.360636 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 14644.780669 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 14644.780669 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 14644.721445 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 14644.721445 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -468,101 +476,109 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks
system.cpu.dcache.writebacks::total 943286 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46768 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950203 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses
system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks
system.cpu.dcache.writebacks::total 943285 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11501 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 11501 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27402 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 27402 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 38903 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 38903 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 38903 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 38903 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46767 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 46767 # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 950200 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 950200 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413180006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413180006 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1463830500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1463830500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 155500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877010506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 11877010506 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877166006 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 11877166006 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040129 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040129 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009877 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.034872 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.233828 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.233828 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31300.500353 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31300.500353 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51833.333333 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12499.484852 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 12499.484852 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12499.609037 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 12499.609037 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 5 # number of replacements
system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 690.367878 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 27855563 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 34689.368618 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 690.367878 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.337094 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.337094 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits
system.cpu.icache.overall_hits::total 27857028 # number of overall hits
system.cpu.icache.tags.tag_accesses 55713535 # Number of tag accesses
system.cpu.icache.tags.data_accesses 55713535 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 27855563 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 27855563 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 27855563 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 27855563 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 27855563 # number of overall hits
system.cpu.icache.overall_hits::total 27855563 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses
system.cpu.icache.overall_misses::total 803 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 60778747 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 60778747 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 60778747 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 60778747 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 60778747 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 60778747 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 27856366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 27856366 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 27856366 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 27856366 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 27856366 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 27856366 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75689.597758 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 75689.597758 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 75689.597758 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 75689.597758 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 75689.597758 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -577,38 +593,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803
system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59238753 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 59238753 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59238753 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 59238753 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59238753 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 59238753 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73771.797011 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73771.797011 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73771.797011 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 73771.797011 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 10238.331530 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_blocks::writebacks 9347.552494 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.372759 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 215.406276 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.285265 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.312449 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
@@ -616,15 +632,15 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 526
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses
system.cpu.l2cache.tags.tag_accesses 15216653 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 15216653 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 903174 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 943285 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 943285 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 32223 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 32223 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits
@@ -642,24 +658,24 @@ system.cpu.l2cache.demand_misses::total 15584 # nu
system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses
system.cpu.l2cache.overall_misses::total 15584 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58173250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 80440250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073291000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 1073291000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 58173250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 1095558000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 1153731250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 58173250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 1095558000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 1153731250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 943286 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 943286 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46768 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46768 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 903436 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 904239 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 943285 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 943285 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 46767 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 46767 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 803 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 950203 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 951006 # number of demand (read+write) accesses
@@ -669,25 +685,25 @@ system.cpu.l2cache.overall_accesses::total 951006 #
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310989 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.310989 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74772.814910 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84988.549618 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 77346.394231 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73796.135864 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73796.135864 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 74033.062757 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74772.814910 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73994.191544 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 74033.062757 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -716,70 +732,70 @@ system.cpu.l2cache.demand_mshr_misses::total 15575
system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48299750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18668000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 66967750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 891481000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 891481000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48299750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910149000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 958448750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48299750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910149000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 958448750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310982 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310982 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.310989 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.310989 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62322.258065 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72921.875000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64954.170708 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61295.448295 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61295.448295 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62322.258065 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61496.554054 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61537.640449 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943286 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46768 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46768 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadReq 904239 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 904239 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 943285 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 46767 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 46767 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1606 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843692 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845298 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2843691 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 2845297 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183296 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183232 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 121234624 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::samples 1894291 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 1894291 100.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoop_fanout::total 1894291 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890430500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 1372247 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 1428681994 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%)
system.membus.trans_dist::ReadReq 1031 # Transaction distribution
system.membus.trans_dist::ReadResp 1031 # Transaction distribution
@@ -800,7 +816,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 15575 # Request fanout histogram
system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 21630500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)

25
tests/long/se/20.parser/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -167,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -184,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -661,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -678,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -737,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -759,9 +763,9 @@ env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
max_stack_size=67108864
output=cout
@@ -792,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -827,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8

1
tests/long/se/20.parser/ref/arm/linux/minor-timing/simerr Normal file → Executable file
View File

@@ -1,2 +1,3 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

14
tests/long/se/20.parser/ref/arm/linux/minor-timing/simout Normal file → Executable file
View File

@@ -1,14 +1,12 @@
Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 7 2014 10:57:46
gem5 started May 7 2014 15:30:22
gem5 executing on cz3211bhr8
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x1e6be7a0
0: system.cpu.isa: ISA system set to: 0 0x3275620
info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -70,4 +68,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
Exiting @ tick 377875396500 because target called exit()
Exiting @ tick 366358475500 because target called exit()

942
tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

30
tests/long/se/30.eon/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -132,6 +133,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -166,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -183,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -591,6 +593,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -651,6 +654,7 @@ id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
[system.cpu.istage2_mmu]
@@ -658,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -675,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -700,6 +704,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -733,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -749,14 +757,16 @@ eventq_index=0
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -786,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -821,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -830,6 +843,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0

1
tests/long/se/30.eon/ref/arm/linux/minor-timing/simerr Normal file → Executable file
View File

@@ -1,3 +1,4 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
getting pixel output filename pixels_out.cook
opening control file chair.control.cook

16
tests/long/se/30.eon/ref/arm/linux/minor-timing/simout Normal file → Executable file
View File

@@ -1,19 +1,17 @@
Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 7 2014 10:57:46
gem5 started May 7 2014 12:10:42
gem5 executing on cz3211bhr8
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0xc928260
0: system.cpu.isa: ISA system set to: 0 0x3ccd9b0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.220000
Exiting @ tick 227450162000 because target called exit()
OO-style eon Time= 0.210000
Exiting @ tick 216864820000 because target called exit()

426
tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.216865 # Nu
sim_ticks 216864820000 # Number of ticks simulated
final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 175540 # Simulator instruction rate (inst/s)
host_op_rate 210755 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 139425507 # Simulator tick rate (ticks/s)
host_mem_usage 321524 # Number of bytes of host memory used
host_seconds 1555.42 # Real time elapsed on the host
host_inst_rate 114758 # Simulator instruction rate (inst/s)
host_op_rate 137779 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 91148248 # Simulator tick rate (ticks/s)
host_mem_usage 250616 # Number of bytes of host memory used
host_seconds 2379.25 # Real time elapsed on the host
sim_insts 273037856 # Number of instructions simulated
sim_ops 327812213 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::0 6625 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 899 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation
system.physmem.totQLat 53728750 # Total ticks spent queuing
system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.bytesPerActivate::samples 1521 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 318.190664 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 188.796192 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 330.520878 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 546 35.90% 35.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 355 23.34% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 175 11.51% 70.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 75 4.93% 75.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 71 4.67% 80.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 52 3.42% 83.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 37 2.43% 86.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 29 1.91% 88.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 181 11.90% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1521 # Bytes accessed per row activation
system.physmem.totQLat 53624000 # Total ticks spent queuing
system.physmem.totMemAccLat 195824000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst
system.physmem.avgQLat 7070.68 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 25820.68 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s
@@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 6056 # Number of row buffer hits during reads
system.physmem.readRowHits 6058 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads
system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 28595013.65 # Average gap between requests
system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ)
system.physmem.pageHitRate 79.88 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.698913 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states
system.physmem_0.actBackEnergy 5663385765 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 125149854750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 145015352790 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.696011 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 208196147750 # Time in different power states
system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1425508750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.797614 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states
system.physmem_1.actBackEnergy 5827279860 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 125006088000 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 145036838310 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.795085 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 207953796500 # Time in different power states
system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1667592250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 33219592 # Number of BP lookups
system.cpu.branchPred.lookups 33219593 # Number of BP lookups
system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target.
system.cpu.branchPred.usedRAS 6612086 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
@@ -382,19 +382,19 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 273037856 # Number of instructions committed
system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed
system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 4054236 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.588533 # CPI: cycles per instruction
system.cpu.ipc 0.629512 # IPC: instructions per cycle
system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped
system.cpu.tickCycles 430193126 # Number of cycles that the object actually ticked
system.cpu.idleCycles 3536514 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 1354 # number of replacements
system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 3085.769078 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 168782221 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 37415.699623 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 3085.769078 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id
@@ -406,62 +406,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432
system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 86649433 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 86649433 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 63540 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 63540 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits
system.cpu.dcache.overall_hits::total 168760435 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 168696891 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 168696891 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 168760431 # number of overall hits
system.cpu.dcache.overall_hits::total 168760431 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 2059 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 2059 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses
system.cpu.dcache.overall_misses::total 7280 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_misses::cpu.data 6 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 7278 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 7278 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 7284 # number of overall misses
system.cpu.dcache.overall_misses::total 7284 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 136977706 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 136977706 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 400661500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 400661500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 537639206 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 537639206 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 537639206 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 537639206 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 86651492 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 86651492 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 63546 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 63546 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 168704169 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 168704169 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000064 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000094 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000094 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66526.326372 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 66526.326372 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76769.783483 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 76769.783483 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 73871.833746 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 73871.833746 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 73810.983800 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 73810.983800 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -472,56 +480,64 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks
system.cpu.dcache.writebacks::total 1010 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses
system.cpu.dcache.demand_mshr_hits::cpu.data 2771 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2771 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2771 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2771 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1637 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1637 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 2870 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4511 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 4507 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 4507 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109140792 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 109140792 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 220213500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 220213500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 320750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 320750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329354292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 329354292 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329675042 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 329675042 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000063 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66671.222969 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66671.222969 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.442509 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.442509 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80187.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80187.500000 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73076.168627 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73076.168627 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73082.474396 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73082.474396 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 36897 # number of replacements
system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 1924.852858 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 73252007 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 1886.285394 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852858 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.939870 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.939870 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
@@ -529,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 34
system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits
system.cpu.icache.overall_hits::total 73252005 # number of overall hits
system.cpu.icache.tags.tag_accesses 146620518 # Number of tag accesses
system.cpu.icache.tags.data_accesses 146620518 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 73252007 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 73252007 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 73252007 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 73252007 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 73252007 # number of overall hits
system.cpu.icache.overall_hits::total 73252007 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses
system.cpu.icache.overall_misses::total 38835 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 728387498 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 728387498 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 728387498 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 728387498 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 728387498 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 728387498 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 73290842 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 73290842 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 73290842 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 73290842 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 73290842 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 73290842 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18755.954629 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 18755.954629 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 18755.954629 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 18755.954629 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 18755.954629 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -581,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 38835
system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668686502 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 668686502 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668686502 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 668686502 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668686502 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 668686502 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17218.655903 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17218.655903 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17218.655903 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 17218.655903 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 4197.194738 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 353.722054 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177954 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294730 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy
@@ -646,17 +662,17 @@ system.cpu.l2cache.demand_misses::total 7628 # nu
system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses
system.cpu.l2cache.overall_misses::total 7628 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258045000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 104755500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 362800500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 217140500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 217140500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 258045000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 321896000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 579941000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 258045000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 321896000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 579941000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses)
@@ -681,17 +697,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.175979 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75363.609813 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77596.666667 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75995.077503 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76082.866153 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76082.866153 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 76027.923440 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75363.609813 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76568.981922 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 76027.923440 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -720,17 +736,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7584
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215060000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85447750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300507750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181443000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181443000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215060000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266890750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 481950750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215060000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266890750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 481950750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses
@@ -742,17 +758,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62846.288720 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65327.025994 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63532.293869 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63574.982481 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63574.982481 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62846.288720 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64125.600673 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63548.358386 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution
@@ -781,9 +797,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 #
system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 58975998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 7577458 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::ReadReq 4730 # Transaction distribution
system.membus.trans_dist::ReadResp 4730 # Transaction distribution
@@ -804,9 +820,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 7584 # Request fanout histogram
system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 8969000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 40262750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

30
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -132,6 +133,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -166,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -183,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -591,6 +593,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -651,6 +654,7 @@ id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
[system.cpu.istage2_mmu]
@@ -658,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -675,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -700,6 +704,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -733,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -749,14 +757,16 @@ eventq_index=0
type=LiveProcess
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -786,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -821,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -830,6 +843,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0

1
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simerr Normal file → Executable file
View File

@@ -1,2 +1,3 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: fcntl64(3, 2) passed through to host

2028
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/simout Normal file → Executable file
View File

File diff suppressed because it is too large Load Diff

340
tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.545057 # Nu
sim_ticks 545056655500 # Number of ticks simulated
final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 182072 # Simulator instruction rate (inst/s)
host_op_rate 224154 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 154902851 # Simulator tick rate (ticks/s)
host_mem_usage 321108 # Number of bytes of host memory used
host_seconds 3518.70 # Real time elapsed on the host
host_inst_rate 122221 # Simulator instruction rate (inst/s)
host_op_rate 150470 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 103982941 # Simulator tick rate (ticks/s)
host_mem_usage 247272 # Number of bytes of host memory used
host_seconds 5241.79 # Real time elapsed on the host
sim_insts 640655084 # Number of instructions simulated
sim_ops 788730743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -193,20 +193,20 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::samples 112303 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 203.039278 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 132.213865 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 254.441282 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 47271 42.09% 42.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 43737 38.95% 81.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8997 8.01% 89.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1907 1.70% 90.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 490 0.44% 91.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 112303 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes
@@ -223,12 +223,12 @@ system.physmem.wrPerTurnAround::stdev 0.855134 # Wr
system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads
system.physmem.totQLat 2737356250 # Total ticks spent queuing
system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 2738025750 # Total ticks spent queuing
system.physmem.totMemAccLat 8179857000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst
system.physmem.avgQLat 9433.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 28183.95 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s
@@ -239,39 +239,39 @@ system.physmem.busUtilRead 0.27 # Da
system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing
system.physmem.readRowHits 193898 # Number of row buffer hits during reads
system.physmem.readRowHits 193900 # Number of row buffer hits during reads
system.physmem.writeRowHits 50093 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
system.physmem.avgGap 1528348.80 # Average gap between requests
system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ)
system.physmem_0.actEnergy 424055520 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 231379500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ)
system.physmem_0.averagePower 693.076638 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states
system.physmem_0.actBackEnergy 106906564890 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 233254311000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 377766467790 # Total energy per rank (pJ)
system.physmem_0.averagePower 693.081659 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 387327017750 # Time in different power states
system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states
system.physmem_0.memoryStateTime::ACT 139526544250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ)
system.physmem_1.actEnergy 424894680 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 231837375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ)
system.physmem_1.averagePower 692.846209 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states
system.physmem_1.actBackEnergy 105911923725 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 234126803250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 377637362310 # Total energy per rank (pJ)
system.physmem_1.averagePower 692.844791 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 388779883250 # Time in different power states
system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states
system.physmem_1.memoryStateTime::ACT 138072943000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 155213668 # Number of BP lookups
system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted
@@ -409,13 +409,13 @@ system.cpu.discardedOps 22623250 # Nu
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.701560 # CPI: cycles per instruction
system.cpu.ipc 0.587696 # IPC: instructions per cycle
system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked
system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped
system.cpu.tickCycles 1030410775 # Number of cycles that the object actually ticked
system.cpu.idleCycles 59702536 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 778141 # number of replacements
system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks.
system.cpu.dcache.tags.total_refs 378456342 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 483.812888 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy
@@ -429,62 +429,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 249627614 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 249627614 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 3485 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 3485 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits
system.cpu.dcache.overall_hits::total 378445004 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 378441379 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 378441379 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 378444864 # number of overall hits
system.cpu.dcache.overall_hits::total 378444864 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 713664 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 713664 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses
system.cpu.dcache.overall_misses::total 851377 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles
system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 851376 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 851376 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 851517 # number of overall misses
system.cpu.dcache.overall_misses::total 851517 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 24697977718 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 24697977718 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.demand_miss_latency::cpu.data 34888229468 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 34888229468 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 34888229468 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 34888229468 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 250341278 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 250341278 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3626 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3626 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 379292755 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 379292755 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038886 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038886 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.290991 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.290991 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.638660 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 40978.638660 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 40971.853137 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 40971.853137 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -495,54 +503,62 @@ system.cpu.dcache.fast_writes 0 # nu
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks
system.cpu.dcache.writebacks::total 91420 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 888 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 888 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses
system.cpu.dcache.demand_mshr_hits::cpu.data 69278 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 69278 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 69278 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 69278 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712776 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712776 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 782098 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 782098 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23542622277 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 23542622277 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1719000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1719000 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28588153527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 28588153527 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589872527 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 28589872527 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038334 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038334 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33029.482302 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33029.482302 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.906475 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.906475 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36553.160252 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 36553.160252 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36548.862464 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 36548.862464 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 23596 # number of replacements
system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use
system.cpu.icache.tags.tagsinuse 1712.064970 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064970 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id
@@ -564,12 +580,12 @@ system.cpu.icache.demand_misses::cpu.inst 25348 # n
system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses
system.cpu.icache.overall_misses::total 25348 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles
system.cpu.icache.ReadReq_miss_latency::cpu.inst 499948995 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 499948995 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 499948995 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 499948995 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 499948995 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 499948995 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses
@@ -582,12 +598,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000087
system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19723.409934 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19723.409934 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19723.409934 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19723.409934 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19723.409934 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -602,34 +618,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 25348
system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460840255 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 460840255 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460840255 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 460840255 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460840255 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 460840255 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460820505 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 460820505 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460820505 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 460820505 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460820505 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 460820505 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18180.537123 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18180.537123 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18179.757969 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18179.757969 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18179.757969 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18179.757969 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 257753 # number of replacements
system.cpu.l2cache.tags.tagsinuse 32573.758002 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 32573.758043 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231572 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601388 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925083 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy
@@ -667,17 +683,17 @@ system.cpu.l2cache.demand_misses::total 290566 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses
system.cpu.l2cache.overall_misses::total 290566 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196449750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17674937000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17871386750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196430000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17675629250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 17872059250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 196449750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22617218750 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22813668500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 196430000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 22617911000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 22814341000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 196430000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 22617911000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 22814341000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses)
@@ -702,17 +718,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.359796 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76076.684741 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79658.345464 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 79617.147789 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 78516.898054 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76076.684741 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78538.776460 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 78516.898054 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -743,17 +759,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290534
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163824250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14898374500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15062198750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163824250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19012312250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 19176136500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163824250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19012312250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 19176136500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses
@@ -765,17 +781,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63571.691890 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67150.327225 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67109.238203 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63571.691890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66024.830964 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66003.071930 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution
@@ -804,9 +820,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 #
system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 38574495 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.occupancy 1224002973 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.trans_dist::ReadReq 224442 # Transaction distribution
system.membus.trans_dist::ReadResp 224442 # Transaction distribution
@@ -828,9 +844,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 356631 # Request fanout histogram
system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks)
system.membus.reqLayer0.occupancy 731518000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 1551221500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------

30
tests/long/se/50.vortex/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -132,6 +133,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -166,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -183,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -591,6 +593,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -651,6 +654,7 @@ id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
[system.cpu.istage2_mmu]
@@ -658,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -675,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -700,6 +704,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -733,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -749,14 +757,16 @@ eventq_index=0
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -786,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -821,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -830,6 +843,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0

1
tests/long/se/50.vortex/ref/arm/linux/minor-timing/simerr Normal file → Executable file
View File

@@ -1 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections

14
tests/long/se/50.vortex/ref/arm/linux/minor-timing/simout Normal file → Executable file
View File

@@ -1,14 +1,12 @@
Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 7 2014 10:57:46
gem5 started May 7 2014 17:09:29
gem5 executing on cz3211bhr8
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0xcee8df0
0: system.cpu.isa: ISA system set to: 0 0x3b079b0
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 64581408500 because target called exit()
Exiting @ tick 57738195500 because target called exit()

1031
tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt
View File

File diff suppressed because it is too large Load Diff

30
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -132,6 +133,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -166,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -183,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -591,6 +593,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -651,6 +654,7 @@ id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
[system.cpu.istage2_mmu]
@@ -658,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -675,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -700,6 +704,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -733,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -749,14 +757,16 @@ eventq_index=0
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -786,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -821,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -830,6 +843,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0

1
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simerr Normal file → Executable file
View File

@@ -1,2 +1,3 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]

14
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/simout Normal file → Executable file
View File

@@ -1,14 +1,12 @@
Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 7 2014 10:57:46
gem5 started May 7 2014 11:11:49
gem5 executing on cz3211bhr8
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x1f2b7940
0: system.cpu.isa: ISA system set to: 0 0x2c50960
info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
@@ -27,4 +25,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1135900642500 because target called exit()
Exiting @ tick 1121241432500 because target called exit()

320
tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 1.121241 # Nu
sim_ticks 1121241432500 # Number of ticks simulated
final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 243175 # Simulator instruction rate (inst/s)
host_op_rate 261985 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 176527853 # Simulator tick rate (ticks/s)
host_mem_usage 312356 # Number of bytes of host memory used
host_seconds 6351.64 # Real time elapsed on the host
host_inst_rate 170583 # Simulator instruction rate (inst/s)
host_op_rate 183778 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 123831111 # Simulator tick rate (ticks/s)
host_mem_usage 241824 # Number of bytes of host memory used
host_seconds 9054.60 # Real time elapsed on the host
sim_insts 1544563087 # Number of instructions simulated
sim_ops 1664032480 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -234,8 +234,8 @@ system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Wr
system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads
system.physmem.totQLat 38434565750 # Total ticks spent queuing
system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 38434561000 # Total ticks spent queuing
system.physmem.totMemAccLat 76957223500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers
system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
@@ -284,13 +284,13 @@ system.physmem_1.memoryStateTime::REF 37440520000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 240141363 # Number of BP lookups
system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted
system.cpu.branchPred.lookups 240141357 # Number of BP lookups
system.cpu.branchPred.condPredicted 186745174 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups
system.cpu.branchPred.BTBLookups 132286195 # Number of BTB lookups
system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 92.438534 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@@ -416,19 +416,19 @@ system.cpu.numWorkItemsStarted 0 # nu
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 1544563087 # Number of instructions committed
system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit
system.cpu.discardedOps 40063388 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.451856 # CPI: cycles per instruction
system.cpu.ipc 0.688774 # IPC: instructions per cycle
system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked
system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped
system.cpu.tickCycles 1838984644 # Number of cycles that the object actually ticked
system.cpu.idleCycles 403498221 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 9223361 # number of replacements
system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 4085.642531 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 624067002 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 67.631526 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642531 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
@@ -439,62 +439,70 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::3 61
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::cpu.data 453735352 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 453735352 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits
system.cpu.dcache.overall_hits::total 624066881 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 624066879 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 624066879 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 624066880 # number of overall hits
system.cpu.dcache.overall_hits::total 624066880 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7336761 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7336761 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses
system.cpu.dcache.overall_misses::total 9591282 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 9591281 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 9591281 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 9591283 # number of overall misses
system.cpu.dcache.overall_misses::total 9591283 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442274246 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 192442274246 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711140250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 109711140250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 302153414496 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 302153414496 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 302153414496 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 302153414496 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 461072113 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 461072113 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 633658160 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 633658160 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.868227 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.868227 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.748723 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.748723 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.925886 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 31502.925886 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.919317 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 31502.919317 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -513,44 +521,52 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 363825
system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336553 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7336553 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9227456 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9227456 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020814754 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020814754 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976850000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976850000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 73750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 73750 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997664754 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 264997664754 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997738504 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 264997738504 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.823627 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.823627 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.977189 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.977189 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 73750 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 73750 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.388335 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.388335 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393215 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393215 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 32 # number of replacements
system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks.
system.cpu.icache.tags.total_refs 466139348 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 566390.459295 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy
@@ -560,44 +576,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 32
system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 932281173 # Number of tag accesses
system.cpu.icache.tags.data_accesses 932281173 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 466139352 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 466139352 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 466139352 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 466139352 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 466139352 # number of overall hits
system.cpu.icache.overall_hits::total 466139352 # number of overall hits
system.cpu.icache.tags.tag_accesses 932281165 # Number of tag accesses
system.cpu.icache.tags.data_accesses 932281165 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 466139348 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 466139348 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 466139348 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 466139348 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 466139348 # number of overall hits
system.cpu.icache.overall_hits::total 466139348 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses
system.cpu.icache.overall_misses::total 823 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 63715999 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 63715999 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 63715999 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 63715999 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 63715999 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 63715999 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 466140175 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 466140175 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 466140175 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 466140175 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 466140175 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 466140175 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 63711749 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 63711749 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 63711749 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 63711749 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 63711749 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 63711749 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 466140171 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 466140171 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 466140171 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 466140171 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 466140171 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 466140171 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77414.032807 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 77414.032807 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 77414.032807 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 77414.032807 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 77414.032807 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -612,24 +628,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 823
system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62143751 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 62143751 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62143751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 62143751 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62143751 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 62143751 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75508.810450 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75508.810450 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75508.810450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 75508.810450 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 2023178 # number of replacements
system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use
@@ -677,17 +693,17 @@ system.cpu.l2cache.demand_misses::total 2055888 # nu
system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses
system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60988000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60983250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 109882532000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568051000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 70568051000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 60988000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 180389595000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 180450583000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 60988000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 180389595000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 180450583000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 109882527250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568052000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 70568052000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 60983250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 180389596000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 180450579250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 60983250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 180389596000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 180450579250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses)
@@ -712,17 +728,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.222781 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77096.396966 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.132819 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.859378 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.859378 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 87772.572849 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77096.396966 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.682074 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 87772.572849 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -753,17 +769,17 @@ system.cpu.l2cache.demand_mshr_misses::total 2055883
system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51082250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006084250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459126500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459126500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51082250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414128500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 154465210750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51082250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414128500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 154465210750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses
@@ -775,17 +791,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64661.075949 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.343666 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.023971 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.023971 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64661.075949 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294760 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.269135 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution
@@ -814,7 +830,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 #
system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.occupancy 1401249 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
@@ -840,7 +856,7 @@ system.membus.snoop_fanout::max_value 0 # Re
system.membus.snoop_fanout::total 3102414 # Request fanout histogram
system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 11243795750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
---------- End Simulation Statistics ----------

30
tests/long/se/70.twolf/ref/arm/linux/minor-timing/config.ini
View File

@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -132,6 +133,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -166,6 +168,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
@@ -183,7 +186,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
@@ -591,6 +593,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
@@ -651,6 +654,7 @@ id_mmfr3=34611729
id_pfr0=49
id_pfr1=4113
midr=1091551472
pmu=Null
system=system
[system.cpu.istage2_mmu]
@@ -658,6 +662,7 @@ type=ArmStage2MMU
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
@@ -675,7 +680,6 @@ eventq_index=0
is_stage2=true
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
@@ -700,6 +704,7 @@ children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
@@ -733,13 +738,16 @@ size=2097152
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
forward_latency=0
frontend_latency=1
response_latency=1
snoop_filter=Null
snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
@@ -749,14 +757,16 @@ eventq_index=0
type=LiveProcess
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
drivers=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
@@ -786,11 +796,14 @@ transition_latency=100000000
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
forward_latency=4
frontend_latency=3
response_latency=2
snoop_filter=Null
snoop_response_latency=4
system=system
use_default_range=false
width=8
width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
@@ -821,7 +834,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
addr_mapping=RoRaBaChCo
addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -830,6 +843,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0

1
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simerr
View File

@@ -1 +1,2 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections

14
tests/long/se/70.twolf/ref/arm/linux/minor-timing/simout
View File

@@ -1,16 +1,14 @@
Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simout
Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled May 7 2014 10:57:46
gem5 started May 7 2014 13:16:45
gem5 executing on cz3211bhr8
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
gem5 compiled Mar 15 2015 20:30:55
gem5 started Mar 15 2015 20:31:14
gem5 executing on zizzer2
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing -re /z/stever/hg/gem5/tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/minor-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
0: system.cpu.isa: ISA system set to: 0 0x1c024750
0: system.cpu.isa: ISA system set to: 0 0x3623b60
info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
@@ -26,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 133578736500 because target called exit()
122 123 124 Exiting @ tick 131756455500 because target called exit()

346
tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt
View File

@@ -4,11 +4,11 @@ sim_seconds 0.131756 # Nu
sim_ticks 131756455500 # Number of ticks simulated
final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 249754 # Simulator instruction rate (inst/s)
host_op_rate 263281 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 190965456 # Simulator tick rate (ticks/s)
host_mem_usage 316672 # Number of bytes of host memory used
host_seconds 689.95 # Real time elapsed on the host
host_inst_rate 150043 # Simulator instruction rate (inst/s)
host_op_rate 158169 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 114724713 # Simulator tick rate (ticks/s)
host_mem_usage 245376 # Number of bytes of host memory used
host_seconds 1148.46 # Real time elapsed on the host
sim_insts 172317809 # Number of instructions simulated
sim_ops 181650742 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # By
system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation
system.physmem.totQLat 26801000 # Total ticks spent queuing
system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totQLat 26795500 # Total ticks spent queuing
system.physmem.totMemAccLat 99339250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst
system.physmem.avgQLat 6925.69 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst
system.physmem.avgMemAccLat 25675.69 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s
@@ -227,14 +227,14 @@ system.physmem_0.preEnergy 1674750 # En
system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.773044 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states
system.physmem_0.actBackEnergy 3539591415 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 75945924750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 88111773435 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.773046 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 126343729250 # Time in different power states
system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states
system.physmem_0.memoryStateTime::ACT 1010946750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ)
@@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 4399460000 # Ti
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu.branchPred.lookups 49934480 # Number of BP lookups
system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted
system.cpu.branchPred.lookups 49934475 # Number of BP lookups
system.cpu.branchPred.condPredicted 39666705 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups
system.cpu.branchPred.BTBLookups 24374227 # Number of BTB lookups
system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage
system.cpu.branchPred.BTBHitPct 95.592537 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@@ -386,15 +386,15 @@ system.cpu.discardedOps 11759003 # Nu
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
system.cpu.cpi 1.529226 # CPI: cycles per instruction
system.cpu.ipc 0.653925 # IPC: instructions per cycle
system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped
system.cpu.tickCycles 257129929 # Number of cycles that the object actually ticked
system.cpu.idleCycles 6382982 # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements 42 # number of replacements
system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks.
system.cpu.dcache.tags.tagsinuse 1377.698550 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 40765676 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks.
system.cpu.dcache.tags.avg_refs 22522.472928 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698550 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id
@@ -404,64 +404,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 83
system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits
system.cpu.dcache.tags.tag_accesses 81538034 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 81538034 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 28357756 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 28357756 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 465 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 465 # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits
system.cpu.dcache.overall_hits::total 40720863 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses
system.cpu.dcache.demand_hits::cpu.data 40720397 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 40720397 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 40720862 # number of overall hits
system.cpu.dcache.overall_hits::total 40720862 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 789 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 789 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data 2435 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2435 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses
system.cpu.dcache.overall_misses::total 2436 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_latency::cpu.data 57528734 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 57528734 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 127304750 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 127304750 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 184833484 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 184833484 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 184833484 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 184833484 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 28358545 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 28358545 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 466 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 466 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses
system.cpu.dcache.demand_accesses::cpu.data 40722832 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 40722832 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 40723298 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 40723298 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.000133 # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002146 # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002146 # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72913.477820 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 72913.477820 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77341.889429 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 77341.889429 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 75906.974949 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 75906.974949 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 75875.814450 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 75875.814450 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -480,46 +488,54 @@ system.cpu.dcache.demand_mshr_hits::cpu.data 626
system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 626 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 712 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1098 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1098 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1810 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1809 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1809 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51124264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 51124264 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85250250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 85250250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136374514 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 136374514 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136444014 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 136444014 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002146 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002146 # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71904.731364 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71904.731364 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77641.393443 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77641.393443 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75386.685462 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75386.685462 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75383.433149 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75383.433149 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 2891 # number of replacements
system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks.
system.cpu.icache.tags.tagsinuse 1424.909257 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 71597353 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks.
system.cpu.icache.tags.avg_refs 15272.472910 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909257 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id
@@ -529,44 +545,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 490
system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses
system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits
system.cpu.icache.overall_hits::total 71597357 # number of overall hits
system.cpu.icache.tags.tag_accesses 143208772 # Number of tag accesses
system.cpu.icache.tags.data_accesses 143208772 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 71597353 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 71597353 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 71597353 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 71597353 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 71597353 # number of overall hits
system.cpu.icache.overall_hits::total 71597353 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses
system.cpu.icache.overall_misses::total 4689 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 200357248 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 200357248 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 200357248 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 200357248 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 200357248 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 200357248 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 71602042 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 71602042 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 71602042 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 71602042 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 71602042 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 71602042 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42729.206227 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 42729.206227 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 42729.206227 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 42729.206227 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 42729.206227 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -581,34 +597,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4689
system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192396752 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 192396752 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192396752 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 192396752 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192396752 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 192396752 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41031.510343 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41031.510343 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41031.510343 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 41031.510343 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use
system.cpu.l2cache.tags.tagsinuse 2001.520504 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676370 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814964 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy
@@ -646,17 +662,17 @@ system.cpu.l2cache.demand_misses::total 3886 # nu
system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses
system.cpu.l2cache.overall_misses::total 3886 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161196250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 210833500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84066750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 84066750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 161196250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 133704000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 294900250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 161196250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 133704000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 294900250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses)
@@ -681,17 +697,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.597938 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74489.949168 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 75405.400572 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77125.458716 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77125.458716 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75887.866701 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74489.949168 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.599303 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75887.866701 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -720,17 +736,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3870
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134003000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174699500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70437750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70437750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134003000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111134250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 245137250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134003000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111134250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 245137250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses
@@ -742,17 +758,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61981.036078 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62841.546763 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64621.788991 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64621.788991 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61981.036078 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.891101 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63342.958656 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution
@@ -806,7 +822,7 @@ system.membus.snoop_fanout::max_value 0 # Re
system.membus.snoop_fanout::total 3869 # Request fanout histogram
system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks)
system.membus.respLayer1.occupancy 20559750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------