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arch-arm: Fix NumVecV7ArchRegs value (64->16)

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In armv7 there are 16 only quadword (vector) registers which are usable
by SIMD instructions (Q0-Q15). Those completely overlap with the 32
double word registers (D0-D31).

NumVecV7ArchRegs  = 16; // Q0-Q15

Change-Id: Id8fee1064d60dcfa54f273fa7d579a20c0087835
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23105
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-11-18 13:50:02 +00:00
parent 2b72ab23ab
commit 1398a81618
1 changed files with 2 additions and 2 deletions
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4
src/arch/arm/registers.hh
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@@ -88,8 +88,8 @@ const int NumMiscRegs = NUM_MISCREGS;
// Vec, PredVec
const int NumFloatV7ArchRegs = 64;
const int NumVecV7ArchRegs = 64;
const int NumVecV8ArchRegs = 32;
const int NumVecV7ArchRegs = 16; // Q0-Q15
const int NumVecV8ArchRegs = 32; // V0-V31
const int NumVecSpecialRegs = 8;
const int NumVecIntrlvRegs = 4;
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;