protocol: made MI_example dma mapping generic
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@@ -1,6 +1,8 @@
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machine(Directory, "Directory protocol")
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: int directory_latency
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: int directory_latency,
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int dma_select_low_bit,
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int dma_select_num_bits
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{
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MessageBuffer forwardFromDir, network="To", virtual_network="2", ordered="false";
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@@ -220,26 +222,6 @@ machine(Directory, "Directory protocol")
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directory[address].Owner.clear();
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}
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// action(d_sendData, "d", desc="Send data to requestor") {
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// peek(requestQueue_in, RequestMsg) {
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// enqueue(responseNetwork_out, ResponseMsg, latency="MEMORY_LATENCY") {
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// out_msg.Address := address;
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//
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// if (in_msg.Type == CoherenceRequestType:GETS && directory[address].Sharers.count() == 0) {
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// // out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE_CLEAN;
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// out_msg.Type := CoherenceResponseType:DATA;
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// } else {
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// out_msg.Type := CoherenceResponseType:DATA;
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// }
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//
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// out_msg.Sender := machineID;
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// out_msg.Destination.add(in_msg.Requestor);
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// out_msg.DataBlk := directory[in_msg.Address].DataBlk;
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// out_msg.MessageSize := MessageSizeType:Response_Data;
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// }
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// }
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// }
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action(d_sendData, "d", desc="Send data to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency="1") {
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@@ -253,18 +235,6 @@ machine(Directory, "Directory protocol")
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}
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}
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// action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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// peek(dmaRequestQueue_in, DMARequestMsg) {
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// enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
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// out_msg.PhysicalAddress := address;
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// out_msg.Type := DMAResponseType:DATA;
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// out_msg.DataBlk := directory[in_msg.PhysicalAddress].DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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// out_msg.Destination.add(map_Address_to_DMA(address));
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// out_msg.MessageSize := MessageSizeType:Response_Data;
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// }
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// }
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// }
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="1") {
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@@ -272,7 +242,8 @@ machine(Directory, "Directory protocol")
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
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dma_select_low_bit, dma_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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@@ -287,7 +258,8 @@ machine(Directory, "Directory protocol")
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
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dma_select_low_bit, dma_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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@@ -298,7 +270,8 @@ machine(Directory, "Directory protocol")
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Destination.add(map_Address_to_DMA(address));
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out_msg.Destination.add(mapAddressToRange(address, MachineType:DMA,
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dma_select_low_bit, dma_select_num_bits));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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@@ -416,20 +389,6 @@ machine(Directory, "Directory protocol")
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}
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}
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}
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// action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") {
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// peek(dmaRequestQueue_in, DMARequestMsg) {
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// enqueue(memQueue_out, MemoryMsg, latency="1") {
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// out_msg.Address := address;
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// out_msg.Type := MemoryRequestType:MEMORY_WB;
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// out_msg.OriginalRequestorMachId := machineID;
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// out_msg.DataBlk := in_msg.DataBlk;
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// out_msg.MessageSize := in_msg.MessageSize;
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// DEBUG_EXPR(out_msg);
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// }
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// }
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// }
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action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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