arch: Get rid of the unused (and mostly undefined) zeroRegisters.

Change-Id: Iadf56e4e742506af7ae4b617d2dc5a56439aa407
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24188
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/alpha/ev5.cc

@@ -80,17 +80,6 @@ initCPU(ThreadContext *tc, int cpuId)
     delete reset;
 }
 
-template <class CPU>
-void
-zeroRegisters(CPU *cpu)
-{
-    // Insure ISA semantics
-    // (no longer very clean due to the change in setIntReg() in the
-    // cpu model.  Consider changing later.)
-    cpu->thread->setIntReg(ZeroReg, 0);
-    cpu->thread->setFloatReg(ZeroReg, 0);
-}
-
 ////////////////////////////////////////////////////////////////////////
 //
 //

src/arch/alpha/utility.hh

@@ -58,13 +58,6 @@ inUserMode(ThreadContext *tc)
     return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0;
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 // Alpha IPR register accessors
 inline bool PcPAL(Addr addr) { return addr & 0x3; }
 inline void startupCPU(ThreadContext *tc, int cpuId)

src/arch/arm/utility.hh

@@ -95,13 +95,6 @@ testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
     }
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 inline void startupCPU(ThreadContext *tc, int cpuId)
 {
     tc->activate();

src/arch/mips/utility.cc

@@ -217,17 +217,6 @@ isSnan(void *val_ptr, int size)
     }
 }
 
-template <class CPU>
-void
-zeroRegisters(CPU *cpu)
-{
-    // Insure ISA semantics
-    // (no longer very clean due to the change in setIntReg() in the
-    // cpu model.  Consider changing later.)
-    cpu->thread->setIntReg(ZeroReg, 0);
-    cpu->thread->setFloatReg(ZeroReg, 0);
-}
-
 void
 startupCPU(ThreadContext *tc, int cpuId)
 {

src/arch/mips/utility.hh

@@ -87,9 +87,6 @@ inUserMode(ThreadContext *tc)
     }
 }
 
-template <class CPU>
-void zeroRegisters(CPU *cpu);
-
 ////////////////////////////////////////////////////////////////////////
 //
 //  Translation stuff

src/arch/power/utility.hh

@@ -49,13 +49,6 @@ buildRetPC(const PCState &curPC, const PCState &callPC)
     return retPC;
 }
 
-/**
- * Function to ensure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 inline void
 startupCPU(ThreadContext *tc, int cpuId)
 {

src/arch/sparc/utility.hh

@@ -62,13 +62,6 @@ inUserMode(ThreadContext *tc)
     return !(pstate.priv || hpstate.hpriv);
 }
 
-/**
- * Function to insure ISA semantics about 0 registers.
- * @param tc The thread context.
- */
-template <class TC>
-void zeroRegisters(TC *tc);
-
 void initCPU(ThreadContext *tc, int cpuId);
 
 inline void

src/arch/x86/utility.hh

@@ -69,13 +69,6 @@ namespace X86ISA
         }
     }
 
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void zeroRegisters(TC *tc);
-
     void initCPU(ThreadContext *tc, int cpuId);
 
     void startupCPU(ThreadContext *tc, int cpuId);