ARM: Treat LDRD in ARM with an odd index as an undefined instruction.

2010-06-02 12:58:17 -05:00
parent 3dc6a8070e
commit 0e556e9dfb
1 changed files with 3 additions and 1 deletions
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -122,8 +122,10 @@ def format AddrMode3() {{
          case 0x2:
            if (op1 & 0x1) {
                %(ldrsb)s
-            } else {
+            } else if ((RT %% 2) == 0) {
                %(ldrd)s
+            } else {
+                return new Unknown(machInst);
            }
          case 0x3:
            if (op1 & 0x1) {