derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch,cpu,dev,sim,mem: Collect System thread elements into a subclass.

Browse Source 
The System class has a few different arrays of values which each
correspond to a thread of execution based on their position. This
change collects them together into a single class to make managing them
easier and less error prone. It also collects methods for manipulating
those threads as an API for that class.

This class acts as a collection point for thread based state which the
System class can look into to get at all its state. It also acts as an
interface for interacting with threads for other classes. This forces
external consumers to use the API instead of accessing the individual
arrays which improves consistency.

Change-Id: Idc4575c5a0b56fe75f5c497809ad91c22bfe26cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25144
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-02-05 19:40:26 -08:00
parent 5da62e6331
commit 0dfa59f0bb
50 changed files with 363 additions and 266 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src/dev/arm/a9scu.cc
View File

@@ -60,20 +60,23 @@ A9SCU::read(PacketPtr pkt)
pkt->setLE(1); // SCU already enabled
break;
case Config:
/* Without making a completely new SCU, we can use the core count field
* as 4 bits and inform the OS of up to 16 CPUs. Although the core
* count is technically bits [1:0] only, bits [3:2] are SBZ for future
* expansion like this.
*/
if (sys->numContexts() > 4) {
warn_once("A9SCU with >4 CPUs is unsupported\n");
if (sys->numContexts() > 15)
fatal("Too many CPUs (%d) for A9SCU!\n", sys->numContexts());
{
/* Without making a completely new SCU, we can use the core count
* field as 4 bits and inform the OS of up to 16 CPUs. Although
* the core count is technically bits [1:0] only, bits [3:2] are
* SBZ for future expansion like this.
*/
int threads = sys->threads.size();
if (threads > 4) {
warn_once("A9SCU with >4 CPUs is unsupported");
fatal_if(threads > 15,
"Too many CPUs (%d) for A9SCU!", threads);
}
int smp_bits, core_cnt;
smp_bits = (1 << threads) - 1;
core_cnt = threads - 1;
pkt->setLE(smp_bits << 4 | core_cnt);
}
int smp_bits, core_cnt;
smp_bits = (1 << sys->numContexts()) - 1;
core_cnt = sys->numContexts() - 1;
pkt->setLE(smp_bits << 4 | core_cnt);
break;
default:
// Only configuration register is implemented

10
src/dev/arm/fvp_base_pwr_ctrl.cc
View File

@@ -61,8 +61,8 @@ void
FVPBasePwrCtrl::init()
{
// All cores are ON by default (PwrStatus.{l0,l1} = 0b1)
corePwrStatus.resize(sys->numContexts(), 0x60000000);
for (const auto &tc : sys->threadContexts)
corePwrStatus.resize(sys->threads.size(), 0x60000000);
for (const auto &tc : sys->threads)
poweredCoresPerCluster[tc->socketId()] += 1;
BasicPioDevice::init();
}
@@ -200,7 +200,7 @@ FVPBasePwrCtrl::write(PacketPtr pkt)
regs.pcoffr = ~0;
} else if (pwrs->l0) {
// Power off all cores in the cluster
for (const auto &tco : sys->threadContexts) {
for (const auto &tco : sys->threads) {
if (tc->socketId() == tco->socketId()) {
PwrStatus *npwrs = getCorePwrStatus(tco);
// Set pending cluster power off
@@ -257,7 +257,7 @@ FVPBasePwrCtrl::getCorePwrStatus(ThreadContext *const tc)
ThreadContext *
FVPBasePwrCtrl::getThreadContextByMPID(uint32_t mpid) const
{
for (auto &tc : sys->threadContexts) {
for (auto &tc : sys->threads) {
if (mpid == ArmISA::getAffinity(&system, tc))
return tc;
}
@@ -274,7 +274,7 @@ FVPBasePwrCtrl::powerCoreOn(ThreadContext *const tc, PwrStatus *const pwrs)
// Clear pending power-offs to the core
pwrs->pp = 0;
// Clear pending power-offs to the core's cluster
for (const auto &tco : sys->threadContexts) {
for (const auto &tco : sys->threads) {
if (tc->socketId() == tco->socketId()) {
PwrStatus *npwrs = getCorePwrStatus(tco);
npwrs->pc = 0;

6
src/dev/arm/generic_timer.cc
View File

@@ -440,7 +440,7 @@ GenericTimer::createTimers(unsigned cpus)
timers.resize(cpus);
for (unsigned i = old_cpu_count; i < cpus; ++i) {
ThreadContext *tc = system.getThreadContext(i);
ThreadContext *tc = system.threads[i];
timers[i].reset(
new CoreTimers(*this, system, i,
@@ -481,7 +481,7 @@ void
GenericTimer::setMiscReg(int reg, unsigned cpu, RegVal val)
{
CoreTimers &core(getTimers(cpu));
ThreadContext *tc = system.getThreadContext(cpu);
ThreadContext *tc = system.threads[cpu];
switch (reg) {
case MISCREG_CNTFRQ:
@@ -695,7 +695,7 @@ GenericTimer::CoreTimers::CoreTimers(GenericTimer &_parent,
ArmInterruptPin *_irqVirt, ArmInterruptPin *_irqHyp)
: parent(_parent),
cntfrq(parent.params()->cntfrq),
threadContext(system.getThreadContext(cpu)),
threadContext(system.threads[cpu]),
irqPhysS(_irqPhysS),
irqPhysNS(_irqPhysNS),
irqVirt(_irqVirt),

24
src/dev/arm/gic_v2.cc
View File

@@ -263,7 +263,7 @@ GicV2::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
/* The 0x100 is a made-up flag to show that gem5 extensions
* are available,
* write 0x200 to this register to enable it. */
return (((sys->numRunningContexts() - 1) << 5) |
return (((sys->threads.numRunning() - 1) << 5) |
(itLines/INT_BITS_MAX -1) |
(haveGem5Extensions ? 0x100 : 0x0));
case GICD_PIDR0:
@@ -291,10 +291,9 @@ GicV2::readCpu(PacketPtr pkt)
assert(pkt->req->hasContextId());
const ContextID ctx = pkt->req->contextId();
assert(ctx < sys->numRunningContexts());
assert(ctx < sys->threads.numRunning());
DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
ctx);
DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr, ctx);
pkt->setLE<uint32_t>(readCpu(ctx, daddr));
@@ -326,7 +325,7 @@ GicV2::readCpu(ContextID ctx, Addr daddr)
panic_if(!cpuSgiPending[active_int],
"Interrupt %d active but no CPU generated it?\n",
active_int);
for (int x = 0; x < sys->numRunningContexts(); x++) {
for (int x = 0; x < sys->threads.numRunning(); x++) {
// See which CPU generated the interrupt
uint8_t cpugen =
bits(cpuSgiPending[active_int], 7 + 8 * x, 8 * x);
@@ -660,7 +659,7 @@ GicV2::softInt(ContextID ctx, SWI swi)
} break;
case 1: {
// interrupt all
for (int i = 0; i < sys->numContexts(); i++) {
for (int i = 0; i < sys->threads.size(); i++) {
DPRINTF(IPI, "Processing CPU %d\n", i);
if (!cpuEnabled(i))
continue;
@@ -686,7 +685,7 @@ GicV2::softInt(ContextID ctx, SWI swi)
// interrupt all
uint8_t cpu_list;
cpu_list = 0;
for (int x = 0; x < sys->numContexts(); x++)
for (int x = 0; x < sys->threads.size(); x++)
cpu_list |= cpuEnabled(x) ? 1 << x : 0;
swi.cpu_list = cpu_list;
break;
@@ -699,7 +698,7 @@ GicV2::softInt(ContextID ctx, SWI swi)
DPRINTF(IPI, "Generating softIRQ from CPU %d for %#x\n", ctx,
swi.cpu_list);
for (int i = 0; i < sys->numContexts(); i++) {
for (int i = 0; i < sys->threads.size(); i++) {
DPRINTF(IPI, "Processing CPU %d\n", i);
if (!cpuEnabled(i))
continue;
@@ -715,8 +714,7 @@ GicV2::softInt(ContextID ctx, SWI swi)
uint64_t
GicV2::genSwiMask(int cpu)
{
if (cpu > sys->numContexts())
panic("Invalid CPU ID\n");
panic_if(cpu > sys->threads.size(), "Invalid CPU ID.");
return ULL(0x0101010101010101) << cpu;
}
@@ -734,7 +732,7 @@ GicV2::getCpuPriority(unsigned cpu)
void
GicV2::updateIntState(int hint)
{
for (int cpu = 0; cpu < sys->numContexts(); cpu++) {
for (int cpu = 0; cpu < sys->threads.size(); cpu++) {
if (!cpuEnabled(cpu))
continue;
@@ -773,7 +771,7 @@ GicV2::updateIntState(int hint)
}
}
bool mp_sys = sys->numRunningContexts() > 1;
bool mp_sys = sys->threads.numRunning() > 1;
// Check other ints
for (int x = 0; x < (itLines/INT_BITS_MAX); x++) {
if (getIntEnabled(cpu, x) & getPendingInt(cpu, x)) {
@@ -832,7 +830,7 @@ GicV2::updateIntState(int hint)
void
GicV2::updateRunPri()
{
for (int cpu = 0; cpu < sys->numContexts(); cpu++) {
for (int cpu = 0; cpu < sys->threads.size(); cpu++) {
if (!cpuEnabled(cpu))
continue;
uint8_t maxPriority = 0xff;

2
src/dev/arm/gic_v2.hh
View File

@@ -297,7 +297,7 @@ class GicV2 : public BaseGic, public BaseGicRegisters
uint8_t cpuTarget[GLOBAL_INT_LINES];
uint8_t getCpuTarget(ContextID ctx, uint32_t ix) {
assert(ctx < sys->numRunningContexts());
assert(ctx < sys->threads.numRunning());
assert(ix < INT_LINES_MAX);
if (ix < SGI_MAX + PPI_MAX) {
// "GICD_ITARGETSR0 to GICD_ITARGETSR7 are read-only, and each

19
src/dev/arm/gic_v3.cc
View File

@@ -60,15 +60,15 @@ void
Gicv3::init()
{
distributor = new Gicv3Distributor(this, params()->it_lines);
redistributors.resize(sys->numContexts(), nullptr);
cpuInterfaces.resize(sys->numContexts(), nullptr);
int threads = sys->threads.size();
redistributors.resize(threads, nullptr);
cpuInterfaces.resize(threads, nullptr);
panic_if(sys->numContexts() > params()->cpu_max,
panic_if(threads > params()->cpu_max,
"Exceeding maximum number of PEs supported by GICv3: "
"using %u while maximum is %u\n", sys->numContexts(),
params()->cpu_max);
"using %u while maximum is %u.", threads, params()->cpu_max);
for (int i = 0; i < sys->numContexts(); i++) {
for (int i = 0; i < threads; i++) {
redistributors[i] = new Gicv3Redistributor(this, i);
cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
}
@@ -77,14 +77,13 @@ Gicv3::init()
Gicv3Distributor::ADDR_RANGE_SIZE - 1);
redistSize = redistributors[0]->addrRangeSize;
redistRange = RangeSize(params()->redist_addr,
redistSize * sys->numContexts() - 1);
redistRange = RangeSize(params()->redist_addr, redistSize * threads - 1);
addrRanges = {distRange, redistRange};
distributor->init();
for (int i = 0; i < sys->numContexts(); i++) {
for (int i = 0; i < threads; i++) {
redistributors[i]->init();
cpuInterfaces[i]->init();
}
@@ -205,7 +204,7 @@ void
Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type)
{
platform->intrctrl->post(cpu, int_type, 0);
ArmSystem::callClearStandByWfi(sys->getThreadContext(cpu));
ArmSystem::callClearStandByWfi(sys->threads[cpu]);
}
bool

6
src/dev/arm/gic_v3_cpu_interface.cc
View File

@@ -1776,7 +1776,7 @@ Gicv3CPUInterface::generateSGI(RegVal val, Gicv3::GroupId group)
bool ns = !inSecureState();
for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
for (int i = 0; i < gic->getSystem()->threads.size(); i++) {
Gicv3Redistributor * redistributor_i =
gic->getRedistributor(i);
uint32_t affinity_i = redistributor_i->getAffinity();
@@ -2587,7 +2587,7 @@ Gicv3CPUInterface::clearPendingInterrupts()
void
Gicv3CPUInterface::assertWakeRequest()
{
ThreadContext *tc = gic->getSystem()->getThreadContext(cpuId);
auto *tc = gic->getSystem()->threads[cpuId];
if (ArmSystem::callSetWakeRequest(tc)) {
Reset().invoke(tc);
tc->activate();
@@ -2597,7 +2597,7 @@ Gicv3CPUInterface::assertWakeRequest()
void
Gicv3CPUInterface::deassertWakeRequest()
{
ThreadContext *tc = gic->getSystem()->getThreadContext(cpuId);
auto *tc = gic->getSystem()->threads[cpuId];
ArmSystem::callClearWakeRequest(tc);
}

4
src/dev/arm/gic_v3_distributor.cc
View File

@@ -1021,7 +1021,7 @@ Gicv3Distributor::route(uint32_t int_id)
if (affinity_routing.IRM) {
// Interrupts routed to any PE defined as a participating node
for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
for (int i = 0; i < gic->getSystem()->threads.size(); i++) {
Gicv3Redistributor * redistributor_i =
gic->getRedistributor(i);
@@ -1086,7 +1086,7 @@ Gicv3Distributor::update()
}
// Update all redistributors
for (int i = 0; i < gic->getSystem()->numContexts(); i++) {
for (int i = 0; i < gic->getSystem()->threads.size(); i++) {
gic->getRedistributor(i)->update();
}
}

4
src/dev/arm/gic_v3_redistributor.cc
View File

@@ -158,7 +158,7 @@ Gicv3Redistributor::read(Addr addr, size_t size, bool is_secure_access)
* (physical LPIs supported)
*/
uint64_t affinity = getAffinity();
int last = cpuId == (gic->getSystem()->numContexts() - 1);
int last = cpuId == (gic->getSystem()->threads.size() - 1);
return (affinity << 32) | (1 << 24) | (cpuId << 8) |
(1 << 5) | (last << 4) | (1 << 3) | (1 << 0);
}
@@ -990,7 +990,7 @@ Gicv3Redistributor::deactivateIRQ(uint32_t int_id)
uint32_t
Gicv3Redistributor::getAffinity() const
{
ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
ThreadContext *tc = gic->getSystem()->threads[cpuId];
uint64_t mpidr = getMPIDR(gic->getSystem(), tc);
/*
* Aff3 = MPIDR[39:32]

8
src/dev/arm/timer_cpulocal.cc
View File

@@ -56,8 +56,8 @@ CpuLocalTimer::init()
{
auto p = params();
// Initialize the timer registers for each per cpu timer
for (int i = 0; i < sys->numContexts(); i++) {
ThreadContext* tc = sys->getThreadContext(i);
for (int i = 0; i < sys->threads.size(); i++) {
ThreadContext* tc = sys->threads[i];
std::stringstream oss;
oss << name() << ".timer" << i;
@@ -429,14 +429,14 @@ CpuLocalTimer::Timer::unserialize(CheckpointIn &cp)
void
CpuLocalTimer::serialize(CheckpointOut &cp) const
{
for (int i = 0; i < sys->numContexts(); i++)
for (int i = 0; i < sys->threads.size(); i++)
localTimer[i]->serializeSection(cp, csprintf("timer%d", i));
}
void
CpuLocalTimer::unserialize(CheckpointIn &cp)
{
for (int i = 0; i < sys->numContexts(); i++)
for (int i = 0; i < sys->threads.size(); i++)
localTimer[i]->unserializeSection(cp, csprintf("timer%d", i));
}

6
src/dev/arm/vgic.cc
View File

@@ -56,7 +56,7 @@ VGic::VGic(const Params *p)
maintIntPosted[x] = false;
vIntPosted[x] = false;
}
assert(sys->numRunningContexts() <= VGIC_CPU_MAX);
assert(sys->threads.numRunning() <= VGIC_CPU_MAX);
}
VGic::~VGic()
@@ -414,8 +414,8 @@ VGic::updateIntState(ContextID ctx_id)
}
}
assert(sys->numRunningContexts() <= VGIC_CPU_MAX);
for (int i = 0; i < sys->numRunningContexts(); i++) {
assert(sys->threads.numRunning() <= VGIC_CPU_MAX);
for (int i = 0; i < sys->threads.numRunning(); i++) {
struct vcpuIntData *vid = &vcpuData[i];
// Are any LRs active that weren't before?
if (!vIntPosted[i]) {

4
src/dev/mips/malta_cchip.cc
View File

@@ -102,7 +102,7 @@ MaltaCChip::postRTC()
void
MaltaCChip::postIntr(uint32_t interrupt)
{
uint64_t size = sys->threadContexts.size();
uint64_t size = sys->threads.size();
assert(size <= Malta::Max_CPUs);
for (int i=0; i < size; i++) {
@@ -117,7 +117,7 @@ MaltaCChip::postIntr(uint32_t interrupt)
void
MaltaCChip::clearIntr(uint32_t interrupt)
{
uint64_t size = sys->threadContexts.size();
uint64_t size = sys->threads.size();
assert(size <= Malta::Max_CPUs);
for (int i=0; i < size; i++) {

10
src/dev/net/dist_iface.cc
View File

@@ -410,9 +410,7 @@ DistIface::SyncEvent::process()
start();
} else {
// Wake up thread contexts on non-switch nodes.
for (int i = 0; i < DistIface::master->sys->numContexts(); i++) {
ThreadContext *tc =
DistIface::master->sys->getThreadContext(i);
for (auto *tc: master->sys->threads) {
if (tc->status() == ThreadContext::Suspended)
tc->activate();
else
@@ -868,8 +866,7 @@ DistIface::toggleSync(ThreadContext *tc)
// Dist-gem5 will reactivate all thread contexts when everyone has
// reached the sync stop point.
#if THE_ISA != NULL_ISA
for (int i = 0; i < master->sys->numContexts(); i++) {
ThreadContext *tc = master->sys->getThreadContext(i);
for (auto *tc: master->sys->threads) {
if (tc->status() == ThreadContext::Active)
tc->quiesce();
}
@@ -883,8 +880,7 @@ DistIface::toggleSync(ThreadContext *tc)
// activation here, since we know exactly when the next sync will
// occur.
#if THE_ISA != NULL_ISA
for (int i = 0; i < master->sys->numContexts(); i++) {
ThreadContext *tc = master->sys->getThreadContext(i);
for (auto *tc: master->sys->threads) {
if (tc->status() == ThreadContext::Active)
tc->quiesceTick(master->syncEvent->when() + 1);
}

12
src/dev/sparc/iob.cc
View File

@@ -58,7 +58,7 @@ Iob::Iob(const Params *p)
iobManSize = ULL(0x0100000000);
iobJBusAddr = ULL(0x9F00000000);
iobJBusSize = ULL(0x0100000000);
assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
assert(params()->system->threads.size() <= MaxNiagaraProcs);
pioDelay = p->pio_latency;
@@ -276,7 +276,7 @@ void
Iob::generateIpi(Type type, int cpu_id, int vector)
{
SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset();
if (cpu_id >= sys->numContexts())
if (cpu_id >= sys->threads.size())
return;
switch (type) {
@@ -289,16 +289,16 @@ Iob::generateIpi(Type type, int cpu_id, int vector)
warn("Sending reset to CPU: %d\n", cpu_id);
if (vector != por->trapType())
panic("Don't know how to set non-POR reset to cpu\n");
por->invoke(sys->threadContexts[cpu_id]);
sys->threadContexts[cpu_id]->activate();
por->invoke(sys->threads[cpu_id]);
sys->threads[cpu_id]->activate();
break;
case 2: // idle -- this means stop executing and don't wake on interrupts
DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id);
sys->threadContexts[cpu_id]->halt();
sys->threads[cpu_id]->halt();
break;
case 3: // resume
DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id);
sys->threadContexts[cpu_id]->activate();
sys->threads[cpu_id]->activate();
break;
default:
panic("Invalid type to generate ipi\n");

4
src/dev/x86/i82094aa.cc
View File

@@ -198,7 +198,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
message.level = entry.polarity;
message.trigger = entry.trigger;
std::list<int> apics;
int numContexts = sys->numContexts();
int numContexts = sys->threads.size();
if (message.destMode == 0) {
if (message.deliveryMode == DeliveryMode::LowestPriority) {
panic("Lowest priority delivery mode from the "
@@ -214,7 +214,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
}
} else {
for (int i = 0; i < numContexts; i++) {
BaseInterrupts *base_int = sys->getThreadContext(i)->
BaseInterrupts *base_int = sys->threads[i]->
getCpuPtr()->getInterruptController(0);
auto *localApic = dynamic_cast<Interrupts *>(base_int);
if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &