0dfa59f0bb
The System class has a few different arrays of values which each correspond to a thread of execution based on their position. This change collects them together into a single class to make managing them easier and less error prone. It also collects methods for manipulating those threads as an API for that class. This class acts as a collection point for thread based state which the System class can look into to get at all its state. It also acts as an interface for interacting with threads for other classes. This forces external consumers to use the API instead of accessing the individual arrays which improves consistency. Change-Id: Idc4575c5a0b56fe75f5c497809ad91c22bfe26cc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25144 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
112 lines
4.0 KiB
C++
112 lines
4.0 KiB
C++
/*
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* Copyright (c) 2010,2019 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "dev/arm/a9scu.hh"
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#include "base/intmath.hh"
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#include "base/trace.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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A9SCU::A9SCU(Params *p)
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: BasicPioDevice(p, 0x60)
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{
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}
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Tick
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A9SCU::read(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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assert(pkt->getSize() == 4);
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Addr daddr = pkt->getAddr() - pioAddr;
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switch(daddr) {
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case Control:
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pkt->setLE(1); // SCU already enabled
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break;
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case Config:
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{
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/* Without making a completely new SCU, we can use the core count
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* field as 4 bits and inform the OS of up to 16 CPUs. Although
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* the core count is technically bits [1:0] only, bits [3:2] are
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* SBZ for future expansion like this.
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*/
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int threads = sys->threads.size();
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if (threads > 4) {
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warn_once("A9SCU with >4 CPUs is unsupported");
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fatal_if(threads > 15,
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"Too many CPUs (%d) for A9SCU!", threads);
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}
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int smp_bits, core_cnt;
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smp_bits = (1 << threads) - 1;
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core_cnt = threads - 1;
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pkt->setLE(smp_bits << 4 | core_cnt);
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}
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break;
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default:
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// Only configuration register is implemented
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panic("Tried to read SCU at offset %#x\n", daddr);
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break;
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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Tick
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A9SCU::write(PacketPtr pkt)
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{
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assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
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Addr daddr = pkt->getAddr() - pioAddr;
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switch (daddr) {
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default:
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// Nothing implemented at this point
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warn("Tried to write SCU at offset %#x\n", daddr);
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break;
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}
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pkt->makeAtomicResponse();
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return pioDelay;
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}
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A9SCU *
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A9SCUParams::create()
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{
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return new A9SCU(this);
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}
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