arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable as ISA parameter values. Additionally, setMiscReg now ignores writes to all of the ID registers. Note: This moves the MIDR parameter from ArmSystem to ArmISA for consistency.
This commit is contained in:
Andreas Sandberg
@@ -35,9 +35,49 @@
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#
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# Authors: Andreas Sandberg
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from m5.params import *
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from m5.SimObject import SimObject
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class ArmISA(SimObject):
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type = 'ArmISA'
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cxx_class = 'ArmISA::ISA'
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cxx_header = "arch/arm/isa.hh"
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# 0x35 Implementor is '5' from "M5"
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# 0x0 Variant
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# 0xf Architecture from CPUID scheme
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# 0xc00 Primary part number ("c" or higher implies ARM v7)
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# 0x0 Revision
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midr = Param.UInt32(0x350fc000, "Main ID Register")
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# See section B4.1.93 - B4.1.94 of the ARM ARM
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#
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# !ThumbEE | !Jazelle | Thumb | ARM
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# Note: ThumbEE is disabled for now since we don't support CP14
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# config registers and jumping to ThumbEE vectors
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id_pfr0 = Param.UInt32(0x00000031, "Processor Feature Register 0")
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# !Timer | !Virti | !M Profile | !TrustZone | ARMv4
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id_pfr1 = Param.UInt32(0x00000001, "Processor Feature Register 1")
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# See section B4.1.89 - B4.1.92 of the ARM ARM
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# VMSAv7 support
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id_mmfr0 = Param.UInt32(0x00000003, "Memory Model Feature Register 0")
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id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
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# no HW access | WFI stalling | ISB and DSB |
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# all TLB maintenance | no Harvard
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id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
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# SuperSec | Coherent TLB | Bcast Maint |
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# BP Maint | Cache Maint Set/way | Cache Maint MVA
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id_mmfr3 = Param.UInt32(0xF0102211, "Memory Model Feature Register 3")
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# See section B4.1.84 of ARM ARM
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# All values are latest for ARMv7-A profile
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id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
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id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
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id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
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id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
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id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
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id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
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fpsid = Param.UInt32(0x410430A0, "Floating-point System ID Register")
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@@ -50,12 +50,6 @@ class ArmSystem(System):
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type = 'ArmSystem'
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cxx_header = "arch/arm/system.hh"
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load_addr_mask = 0xffffffff
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# 0x35 Implementor is '5' from "M5"
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# 0x0 Variant
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# 0xf Architecture from CPUID scheme
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# 0xc00 Primary part number ("c" or higher implies ARM v7)
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# 0x0 Revision
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midr_regval = Param.UInt32(0x350fc000, "MIDR value")
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multi_proc = Param.Bool(True, "Multiprocessor system?")
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boot_loader = Param.String("", "File that contains the boot loader code if any")
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gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
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@@ -69,8 +69,9 @@ ISA::params() const
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void
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ISA::clear()
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{
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const Params *p(params());
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SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
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uint32_t midr = miscRegs[MISCREG_MIDR];
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memset(miscRegs, 0, sizeof(miscRegs));
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CPSR cpsr = 0;
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cpsr.mode = MODE_USER;
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@@ -89,9 +90,6 @@ ISA::clear()
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miscRegs[MISCREG_SCTLR] = sctlr;
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miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
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// Preserve MIDR across reset
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miscRegs[MISCREG_MIDR] = midr;
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/* Start with an event in the mailbox */
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miscRegs[MISCREG_SEV_MAILBOX] = 1;
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@@ -152,16 +150,28 @@ ISA::clear()
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0; // 1:0
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miscRegs[MISCREG_CPACR] = 0;
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miscRegs[MISCREG_FPSID] = 0x410430A0;
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// See section B4.1.84 of ARM ARM
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// All values are latest for ARMv7-A profile
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miscRegs[MISCREG_ID_ISAR0] = 0x02101111;
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miscRegs[MISCREG_ID_ISAR1] = 0x02112111;
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miscRegs[MISCREG_ID_ISAR2] = 0x21232141;
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miscRegs[MISCREG_ID_ISAR3] = 0x01112131;
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miscRegs[MISCREG_ID_ISAR4] = 0x10010142;
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miscRegs[MISCREG_ID_ISAR5] = 0x00000000;
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// Initialize configurable default values
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miscRegs[MISCREG_MIDR] = p->midr;
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miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
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miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
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miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
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miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
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miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
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miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
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miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
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miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
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miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
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miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
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miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
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miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
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miscRegs[MISCREG_FPSID] = p->fpsid;
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//XXX We need to initialize the rest of the state.
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}
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@@ -214,14 +224,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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tc->cpuId();
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}
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break;
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case MISCREG_ID_MMFR0:
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return 0x03; // VMSAv7 support
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case MISCREG_ID_MMFR2:
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return 0x01230000; // no HW access | WFI stalling | ISB and DSB
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// | all TLB maintenance | no Harvard
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case MISCREG_ID_MMFR3:
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return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
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// BP Maint | Cache Maint Set/way | Cache Maint MVA
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case MISCREG_CLIDR:
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warn_once("The clidr register always reports 0 caches.\n");
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warn_once("clidr LoUIS field of 0b001 to match current "
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@@ -231,12 +233,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
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warn_once("The ccsidr register isn't implemented and "
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"always reads as 0.\n");
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break;
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case MISCREG_ID_PFR0:
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warn("Returning thumbEE disabled for now since we don't support CP14"
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"config registers and jumping to ThumbEE vectors\n");
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return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM
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case MISCREG_ID_PFR1:
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return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
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case MISCREG_CTR:
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{
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//all caches have the same line size in gem5
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@@ -463,12 +459,29 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
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}
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return;
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}
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case MISCREG_MIDR:
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case MISCREG_ID_PFR0:
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case MISCREG_ID_PFR1:
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case MISCREG_ID_MMFR0:
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case MISCREG_ID_MMFR1:
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case MISCREG_ID_MMFR2:
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case MISCREG_ID_MMFR3:
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case MISCREG_ID_ISAR0:
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case MISCREG_ID_ISAR1:
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case MISCREG_ID_ISAR2:
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case MISCREG_ID_ISAR3:
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case MISCREG_ID_ISAR4:
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case MISCREG_ID_ISAR5:
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case MISCREG_MPIDR:
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case MISCREG_FPSID:
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case MISCREG_TLBTR:
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case MISCREG_MVFR0:
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case MISCREG_MVFR1:
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case MISCREG_MPIDR:
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case MISCREG_FPSID:
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// ID registers are constants.
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return;
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case MISCREG_TLBIALLIS:
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case MISCREG_TLBIALL:
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sys = tc->getSystemPtr();
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@@ -105,11 +105,6 @@ ArmSystem::initState()
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// Set the initial PC to be at start of the kernel code
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threadContexts[0]->pcState(kernelEntry & loadAddrMask);
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}
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for (int i = 0; i < threadContexts.size(); i++) {
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threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR,
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p->midr_regval);
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}
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}
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ArmSystem::~ArmSystem()
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