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arch-arm: Fix bug in VQRSHL.

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If shiftAmt is 0, bits raise assert, causing core dump.

Change-Id: Ic4285f51a866ffc017645655e98674ca69a15a40
This commit is contained in:
Junshi Wang
2024-11-17 16:53:36 +08:00
committed by Bobby R. Bruce
parent 1e5021c2e3
commit 0a22e63467
1 changed files with 2 additions and 0 deletions
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2
src/arch/arm/isa/insts/neon.isa
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@@ -2551,6 +2551,8 @@ let {{
destElem = (srcElem1 >> shiftAmt); destElem = (srcElem1 >> shiftAmt);
} }
destElem += rBit; destElem += rBit;
} else if (shiftAmt == 0) {
destElem = srcElem1;
} else { } else {
if (shiftAmt >= sizeof(Element) * 8) { if (shiftAmt >= sizeof(Element) * 8) {
if (srcElem1 != 0) { if (srcElem1 != 0) {