From 0a22e63467dc5f4175a663dce94f9d754d7511cb Mon Sep 17 00:00:00 2001
From: Junshi Wang <junshi.wang@arm.com>
Date: Sun, 17 Nov 2024 16:53:36 +0800
Subject: [PATCH] arch-arm: Fix bug in VQRSHL.

If shiftAmt is 0, bits raise assert, causing core dump.

Change-Id: Ic4285f51a866ffc017645655e98674ca69a15a40
---
 src/arch/arm/isa/insts/neon.isa | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 7db7f2125d..65cfc2ee59 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -2551,6 +2551,8 @@ let {{
                 destElem = (srcElem1 >> shiftAmt);
             }
             destElem += rBit;
+        } else if (shiftAmt == 0) {
+            destElem = srcElem1;
         } else {
             if (shiftAmt >= sizeof(Element) * 8) {
                 if (srcElem1 != 0) {