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arch-arm: Remove SCTLR.VE bit

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ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are
removing it from gem5 since we were not handling it anyway.

Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13998
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-11-02 10:33:30 +00:00
parent 46a79f7d10
commit 07a2fd7ec2
2 changed files with 1 additions and 5 deletions
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5
src/arch/arm/faults.cc
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@@ -300,10 +300,6 @@ ArmFault::getVector(ThreadContext *tc)
// ARM ARM issue C B1.8.1
bool haveSecurity = ArmSystem::haveSecurity(tc);
// panic if SCTLR.VE because I have no idea what to do with vectored
// interrupts
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
assert(!sctlr.ve);
// Check for invalid modes
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
assert(haveSecurity || cpsr.mode != MODE_MON);
@@ -318,6 +314,7 @@ ArmFault::getVector(ThreadContext *tc)
base = tc->readMiscReg(MISCREG_HVBAR);
break;
default:
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
if (sctlr.v) {
base = HighVecs;
} else {

1
src/arch/arm/miscregs_types.hh
View File

@@ -319,7 +319,6 @@ namespace ArmISA
// DC CVAC and IC IVAU instructions
// (AArch64 SCTLR_EL1 only)
Bitfield<25> ee; // Exception Endianness
Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
// (AArch64 SCTLR_EL1 only)
Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)