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misc: Replace TARGET_ISA with USE_${ISA} variables.

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The TARGET_ISA variable would let you select one ISA from a list of
possible ISAs. That has now been replaced with USE_ARM_ISA, USE_X86_ISA,
etc, variables which are boolean on or off. That will allow any number
of ISAs to be enabled or disabled individually. Enabling something other
than exactly one of these will probably prevent you from getting a
working gem5 binary, but those problems are being addressed in other,
parallel change series.

I decided to use the USE_ prefix since it was consistent with most other
on/off variables we have in gem5. One noteable exception is the
BUILD_GPU setting which, you could convincingly argue, is a better
prefix than USE_. Another option would be to use CONFIG_, in
anticipation of using a kconfig style config mechanism in gem5.

It seemed premature to start using a CONFIG_ prefix here, and if we
decide to switch to some other prefix like BUILD_, it should be a
purposeful choice and not something somebody just starts using.

Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52491
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-11-01 02:38:26 -07:00
parent daf0cbb134
commit 073c32be2c
56 changed files with 181 additions and 147 deletions
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4
tests/configs/o3-timing-mt.py
View File

@@ -41,11 +41,13 @@ from m5.defines import buildEnv
from base_config import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv["TARGET_ISA"] == "arm":
if get_runtime_isa() == ISA.ARM:
root = ArmSESystemUniprocessor(
mem_mode="timing",
mem_class=DDR3_1600_8x8,

4
tests/configs/o3-timing.py
View File

@@ -41,11 +41,13 @@ from m5.defines import buildEnv
from base_config import *
from arm_generic import *
from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
# If we are running ARM regressions, use a more sensible CPU
# configuration. This makes the results more meaningful, and also
# increases the coverage of the regressions.
if buildEnv["TARGET_ISA"] == "arm":
if get_runtime_isa() == ISA.ARM:
root = ArmSESystemUniprocessor(
mem_mode="timing", mem_class=DDR3_1600_8x8, cpu_class=O3_ARM_v7a_3
).create_root()

6
tests/gem5/cpu_tests/run.py
View File

@@ -29,6 +29,8 @@ import os
import argparse
import m5
from gem5.isas import ISA
from gem5.runtime import get_runtime_isa
from m5.objects import *
@@ -97,7 +99,7 @@ class MySimpleMemory(SimpleMemory):
latency = "1ns"
if buildEnv["TARGET_ISA"] == "x86":
if get_runtime_isa() == ISA.X86:
valid_cpu = {
"AtomicSimpleCPU": AtomicSimpleCPU,
"TimingSimpleCPU": TimingSimpleCPU,
@@ -155,7 +157,7 @@ else:
system.l2cache.connectMemSideBus(system.membus)
system.cpu.createInterruptController()
if m5.defines.buildEnv["TARGET_ISA"] == "x86":
if get_runtime_isa() == ISA.X86:
system.cpu.interrupts[0].pio = system.membus.mem_side_ports
system.cpu.interrupts[0].int_master = system.membus.cpu_side_ports
system.cpu.interrupts[0].int_slave = system.membus.mem_side_ports