misc: Replace TARGET_ISA with USE_${ISA} variables.

The TARGET_ISA variable would let you select one ISA from a list of
possible ISAs. That has now been replaced with USE_ARM_ISA, USE_X86_ISA,
etc, variables which are boolean on or off. That will allow any number
of ISAs to be enabled or disabled individually. Enabling something other
than exactly one of these will probably prevent you from getting a
working gem5 binary, but those problems are being addressed in other,
parallel change series.

I decided to use the USE_ prefix since it was consistent with most other
on/off variables we have in gem5. One noteable exception is the
BUILD_GPU setting which, you could convincingly argue, is a better
prefix than USE_. Another option would be to use CONFIG_, in
anticipation of using a kconfig style config mechanism in gem5.

It seemed premature to start using a CONFIG_ prefix here, and if we
decide to switch to some other prefix like BUILD_, it should be a
purposeful choice and not something somebody just starts using.

Change-Id: I90fef2835aa4712782e6c1313fbf564d0ed45538
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52491
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

configs/common/CacheConfig.py

@@ -42,6 +42,9 @@
 
 import m5
 from m5.objects import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
+
 from common.Caches import *
 from common import ObjectList
 
@@ -114,7 +117,7 @@ def config_cache(options, system):
             None,
         )
 
-        if buildEnv["TARGET_ISA"] in ["x86", "riscv"]:
+        if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
             walk_cache_class = PageTableWalkerCache
 
     # Set the cache line size of the system
@@ -189,7 +192,7 @@ def config_cache(options, system):
             # on these names.  For simplicity, we would advise configuring
             # it to use this naming scheme; if this isn't possible, change
             # the names below.
-            if buildEnv["TARGET_ISA"] in ["x86", "arm", "riscv"]:
+            if get_runtime_isa() in [ISA.X86, ISA.ARM, ISA.RISCV]:
                 system.cpu[i].addPrivateSplitL1Caches(
                     ExternalCache("cpu%d.icache" % i),
                     ExternalCache("cpu%d.dcache" % i),

configs/common/Caches.py

@@ -39,6 +39,8 @@
 
 from m5.defines import buildEnv
 from m5.objects import *
+from gem5.isas import ISA
+from gem5.runtime import get_runtime_isa
 
 # Base implementations of L1, L2, IO and TLB-walker caches. There are
 # used in the regressions and also as base components in the
@@ -96,7 +98,7 @@ class PageTableWalkerCache(Cache):
     tgts_per_mshr = 12
 
     # the x86 table walker actually writes to the table-walker cache
-    if buildEnv["TARGET_ISA"] in ["x86", "riscv"]:
+    if get_runtime_isa() in [ISA.X86, ISA.RISCV]:
         is_read_only = False
     else:
         is_read_only = True

configs/common/FSConfig.py

@@ -39,26 +39,35 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import m5
+import m5.defines
 from m5.objects import *
 from m5.util import *
 from common.Benchmarks import *
 from common import ObjectList
 
 # Populate to reflect supported os types per target ISA
-os_types = {
-    "mips": ["linux"],
-    "riscv": ["linux"],  # TODO that's a lie
-    "sparc": ["linux"],
-    "x86": ["linux"],
-    "arm": [
-        "linux",
-        "android-gingerbread",
-        "android-ics",
-        "android-jellybean",
-        "android-kitkat",
-        "android-nougat",
-    ],
-}
+os_types = set()
+if m5.defines.buildEnv["USE_ARM_ISA"]:
+    os_types.update(
+        [
+            "linux",
+            "android-gingerbread",
+            "android-ics",
+            "android-jellybean",
+            "android-kitkat",
+            "android-nougat",
+        ]
+    )
+if m5.defines.buildEnv["USE_MIPS_ISA"]:
+    os_types.add("linux")
+if m5.defines.buildEnv["USE_POWER_ISA"]:
+    os_types.add("linux")
+if m5.defines.buildEnv["USE_RISCV_ISA"]:
+    os_types.add("linux")  # TODO that's a lie
+if m5.defines.buildEnv["USE_SPARC_ISA"]:
+    os_types.add("linux")
+if m5.defines.buildEnv["USE_X86_ISA"]:
+    os_types.add("linux")
 
 
 class CowIdeDisk(IdeDisk):

configs/common/ObjectList.py

@@ -34,6 +34,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from gem5.runtime import get_supported_isas
 import m5.objects
 import m5.internal.params
 import inspect
@@ -139,13 +140,14 @@ class CPUList(ObjectList):
     def _add_objects(self):
         super(CPUList, self)._add_objects()
 
-        from m5.defines import buildEnv
         from importlib import import_module
 
-        for package in ["generic", buildEnv["TARGET_ISA"]]:
+        for isa in {
+            "generic",
+        } | {isa.name.lower() for isa in get_supported_isas()}:
             try:
                 package = import_module(
-                    ".cores." + package, package=__name__.rpartition(".")[0]
+                    ".cores." + isa, package=__name__.rpartition(".")[0]
                 )
             except ImportError:
                 # No timing models for this ISA

configs/common/Options.py

@@ -772,7 +772,7 @@ def addFSOptions(parser):
     parser.add_argument(
         "--os-type",
         action="store",
-        choices=os_types[str(buildEnv["TARGET_ISA"])],
+        choices=os_types,
         default="linux",
         help="Specifies type of OS to boot",
     )
@@ -784,7 +784,7 @@ def addFSOptions(parser):
         "files in the gem5 output directory",
     )
 
-    if buildEnv["TARGET_ISA"] == "arm":
+    if buildEnv["USE_ARM_ISA"]:
         parser.add_argument(
             "--bare-metal",
             action="store_true",