derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

cpu/inorder: merge register class enums

Browse Source 
The previous patch introduced a RegClass enum to clean
up register classification.  The inorder model already
had an equivalent enum (RegType) that was used internally.
This patch replaces RegType with RegClass to get rid
of the now-redundant code.
This commit is contained in:
Steve Reinhardt
2013-10-15 14:22:43 -04:00
parent 7aa423acad
commit 06d246ab4a
5 changed files with 32 additions and 56 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/cpu/inorder/cpu.cc
View File

@@ -1257,21 +1257,20 @@ InOrderCPU::getPipeStage(int stage_num)
RegIndex
InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid)
{
RegIndex rel_idx;
switch (regIdxToClass(reg_idx, &rel_idx)) {
reg_type = regIdxToClass(reg_idx, &rel_idx);
switch (reg_type) {
case IntRegClass:
reg_type = IntType;
return isa[tid]->flattenIntIndex(rel_idx);
case FloatRegClass:
reg_type = FloatType;
return isa[tid]->flattenFloatIndex(rel_idx);
case MiscRegClass:
reg_type = MiscType;
return rel_idx;
default:

22
src/cpu/inorder/cpu.hh
View File

@@ -334,9 +334,6 @@ class InOrderCPU : public BaseCPU
/** Dependency Tracker for Integer & Floating Point Regs */
RegDepMap archRegDepMap[ThePipeline::MaxThreads];
/** Register Types Used in Dependency Tracking */
enum RegType { IntType, FloatType, MiscType, NumRegTypes};
/** Global communication structure */
TimeBuffer<TimeStruct> timeBuffer;
@@ -599,24 +596,7 @@ class InOrderCPU : public BaseCPU
void setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid);
RegType inline getRegType(RegIndex reg_idx)
{
switch (regIdxToClass(reg_idx)) {
case IntRegClass:
return IntType;
case FloatRegClass:
return FloatType;
case MiscRegClass:
return MiscType;
default:
panic("register %d out of range\n", reg_idx);
}
}
RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
RegIndex flattenRegIdx(RegIndex reg_idx, RegClass &reg_type, ThreadID tid);
/** Reads a miscellaneous register. */
MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);

26
src/cpu/inorder/reg_dep_map.cc
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -43,10 +44,10 @@ using namespace ThePipeline;
RegDepMap::RegDepMap(int size)
{
regMap.resize(InOrderCPU::NumRegTypes);
regMap[InOrderCPU::IntType].resize(NumIntRegs);
regMap[InOrderCPU::FloatType].resize(NumFloatRegs);
regMap[InOrderCPU::MiscType].resize(NumMiscRegs);
regMap.resize(NumRegClasses);
regMap[IntRegClass].resize(NumIntRegs);
regMap[FloatRegClass].resize(NumFloatRegs);
regMap[MiscRegClass].resize(NumMiscRegs);
}
RegDepMap::~RegDepMap()
@@ -60,9 +61,6 @@ RegDepMap::name()
return cpu->name() + ".RegDepMap";
}
std::string RegDepMap::mapNames[InOrderCPU::NumRegTypes] =
{"IntReg", "FloatReg", "MiscReg"};
void
RegDepMap::setCPU(InOrderCPU *_cpu)
{
@@ -93,7 +91,7 @@ RegDepMap::insert(DynInstPtr inst)
dest_regs);
for (int i = 0; i < dest_regs; i++) {
InOrderCPU::RegType reg_type;
RegClass reg_type;
TheISA::RegIndex raw_idx = inst->destRegIdx(i);
TheISA::RegIndex flat_idx = cpu->flattenRegIdx(raw_idx,
reg_type,
@@ -104,7 +102,7 @@ RegDepMap::insert(DynInstPtr inst)
inst->flattenDestReg(i, flat_idx);
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
if (flat_idx == TheISA::ZeroReg && reg_type == IntRegClass) {
DPRINTF(RegDepMap, "[sn:%i]: Ignoring Insert-Dependency tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
@@ -120,7 +118,7 @@ void
RegDepMap::insert(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
{
DPRINTF(RegDepMap, "Inserting [sn:%i] onto %s dep. list for "
"reg. idx %i.\n", inst->seqNum, mapNames[reg_type],
"reg. idx %i.\n", inst->seqNum, RegClassStrings[reg_type],
idx);
regMap[reg_type][idx].push_back(inst);
@@ -143,11 +141,11 @@ RegDepMap::remove(DynInstPtr inst)
for (int i = 0; i < dest_regs; i++) {
RegIndex flat_idx = inst->flattenedDestRegIdx(i);
InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
RegClass reg_type = regIdxToClass(inst->destRegIdx(i));
// Merge Dyn Inst & CPU Result Types
if (flat_idx == TheISA::ZeroReg &&
reg_type == InOrderCPU::IntType) {
reg_type == IntRegClass) {
DPRINTF(RegDepMap, "[sn:%i]: Ignoring Remove-Dependency tracking for "
"ISA-ZeroReg (Int. Reg %i).\n", inst->seqNum,
flat_idx);
@@ -172,7 +170,7 @@ RegDepMap::remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
while (list_it != list_end) {
if((*list_it) == inst) {
DPRINTF(RegDepMap, "Removing [sn:%i] from %s dep. list for "
"reg. idx %i.\n", inst->seqNum, mapNames[reg_type],
"reg. idx %i.\n", inst->seqNum, RegClassStrings[reg_type],
idx);
regMap[reg_type][idx].erase(list_it);
return;
@@ -285,7 +283,7 @@ RegDepMap::canWrite(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
void
RegDepMap::dump()
{
for (int reg_type = 0; reg_type < InOrderCPU::NumRegTypes; reg_type++) {
for (int reg_type = 0; reg_type < NumRegClasses; reg_type++) {
for (int idx=0; idx < regMap.size(); idx++) {
if (regMap[idx].size() > 0) {
cprintf("Reg #%i (size:%i): ", idx, regMap[reg_type][idx].size());

4
src/cpu/inorder/reg_dep_map.hh
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -45,13 +46,10 @@ class RegDepMap
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
typedef TheISA::RegIndex RegIndex;
typedef uint8_t RegType;
RegDepMap(int size = TheISA::TotalNumRegs);
~RegDepMap();
static std::string mapNames[];
std::string name();
void setCPU(InOrderCPU *_cpu);

27
src/cpu/inorder/resources/use_def.cc
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -205,12 +206,12 @@ UseDefUnit::execute(int slot_idx)
{
case ReadSrcReg:
{
InOrderCPU::RegType reg_type;
RegClass reg_type;
RegIndex reg_idx = inst->_srcRegIdx[ud_idx];
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
inst->flattenSrcReg(ud_idx, flat_idx);
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
if (flat_idx == TheISA::ZeroReg && reg_type == IntRegClass) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Ignoring Reading of ISA-ZeroReg "
"(Int. Reg %i).\n", tid, inst->seqNum, flat_idx);
ud_req->done();
@@ -224,7 +225,7 @@ UseDefUnit::execute(int slot_idx)
if (regDepMap[tid]->canRead(reg_type, flat_idx, inst)) {
switch (reg_type)
{
case InOrderCPU::IntType:
case IntRegClass:
{
uniqueIntRegMap[flat_idx] = true;
@@ -240,7 +241,7 @@ UseDefUnit::execute(int slot_idx)
}
break;
case InOrderCPU::FloatType:
case FloatRegClass:
{
uniqueFloatRegMap[flat_idx] = true;
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Float Reg %i"
@@ -262,7 +263,7 @@ UseDefUnit::execute(int slot_idx)
}
break;
case InOrderCPU::MiscType:
case MiscRegClass:
{
uniqueMiscRegMap[flat_idx] = true;
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i]: Reading Misc Reg %i "
@@ -294,7 +295,7 @@ UseDefUnit::execute(int slot_idx)
switch (reg_type)
{
case InOrderCPU::IntType:
case IntRegClass:
{
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
" reg %i (%i), value 0x%x from "
@@ -309,7 +310,7 @@ UseDefUnit::execute(int slot_idx)
}
break;
case InOrderCPU::FloatType:
case FloatRegClass:
{
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
" reg %i (%i) value 0x%x from "
@@ -323,7 +324,7 @@ UseDefUnit::execute(int slot_idx)
}
break;
case InOrderCPU::MiscType:
case MiscRegClass:
{
DPRINTF(InOrderUseDef, "[tid:%i]: Forwarding dest."
" reg %i (%i) value 0x%x from "
@@ -359,11 +360,11 @@ UseDefUnit::execute(int slot_idx)
case WriteDestReg:
{
InOrderCPU::RegType reg_type;
RegClass reg_type;
RegIndex reg_idx = inst->_destRegIdx[ud_idx];
RegIndex flat_idx = cpu->flattenRegIdx(reg_idx, reg_type, tid);
if (flat_idx == TheISA::ZeroReg && reg_type == InOrderCPU::IntType) {
if (flat_idx == TheISA::ZeroReg && reg_type == IntRegClass) {
DPRINTF(IntRegs, "[tid:%i]: Ignoring Writing of ISA-ZeroReg "
"(Int. Reg %i)\n", tid, flat_idx);
ud_req->done();
@@ -377,7 +378,7 @@ UseDefUnit::execute(int slot_idx)
switch (reg_type)
{
case InOrderCPU::IntType:
case IntRegClass:
{
uniqueIntRegMap[flat_idx] = true;
@@ -396,7 +397,7 @@ UseDefUnit::execute(int slot_idx)
}
break;
case InOrderCPU::FloatType:
case FloatRegClass:
{
uniqueFloatRegMap[flat_idx] = true;
@@ -451,7 +452,7 @@ UseDefUnit::execute(int slot_idx)
}
break;
case InOrderCPU::MiscType:
case MiscRegClass:
{
uniqueMiscRegMap[flat_idx] = true;