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cpu: Eliminate the unused "lane" interface from the ThreadContext.

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If someone needs to access a component of a vector register, they can do
so through the other interfaces.

Change-Id: Idf1d9b68339eb31b95d4a347548240aa9d2a85cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41899
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-02-25 00:50:11 -08:00
parent 4315b368d3
commit 05e580f146
7 changed files with 0 additions and 393 deletions
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56
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -283,62 +283,6 @@ class ThreadContext : public ::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
ConstVecLane8
readVec8BitLaneReg(const RegId &reg) const override
{
panic("%s not implemented.", __FUNCTION__);
}
/** Reads source vector 16bit operand. */
ConstVecLane16
readVec16BitLaneReg(const RegId &reg) const override
{
panic("%s not implemented.", __FUNCTION__);
}
/** Reads source vector 32bit operand. */
ConstVecLane32
readVec32BitLaneReg(const RegId &reg) const override
{
panic("%s not implemented.", __FUNCTION__);
}
/** Reads source vector 64bit operand. */
ConstVecLane64
readVec64BitLaneReg(const RegId &reg) const override
{
panic("%s not implemented.", __FUNCTION__);
}
/** Write a lane of the destination vector register. */
void
setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecLane(const RegId &reg,
const LaneData<LaneSize::TwoByte> &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecLane(const RegId &reg,
const LaneData<LaneSize::FourByte> &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setVecLane(const RegId &reg,
const LaneData<LaneSize::EightByte> &val) override
{
panic("%s not implemented.", __FUNCTION__);
}
/** @} */
const VecElem &
readVecElem(const RegId &reg) const override
{

57
src/cpu/checker/thread_context.hh
View File

@@ -249,63 +249,6 @@ class CheckerThreadContext : public ThreadContext
return actualTC->getWritableVecReg(reg);
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
ConstVecLane8
readVec8BitLaneReg(const RegId &reg) const override
{
return actualTC->readVec8BitLaneReg(reg);
}
/** Reads source vector 16bit operand. */
ConstVecLane16
readVec16BitLaneReg(const RegId &reg) const override
{
return actualTC->readVec16BitLaneReg(reg);
}
/** Reads source vector 32bit operand. */
ConstVecLane32
readVec32BitLaneReg(const RegId &reg) const override
{
return actualTC->readVec32BitLaneReg(reg);
}
/** Reads source vector 64bit operand. */
ConstVecLane64
readVec64BitLaneReg(const RegId &reg) const override
{
return actualTC->readVec64BitLaneReg(reg);
}
/** Write a lane of the destination vector register. */
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::Byte> &val) override
{
return actualTC->setVecLane(reg, val);
}
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::TwoByte> &val) override
{
return actualTC->setVecLane(reg, val);
}
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::FourByte> &val) override
{
return actualTC->setVecLane(reg, val);
}
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::EightByte> &val) override
{
return actualTC->setVecLane(reg, val);
}
/** @} */
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{

52
src/cpu/o3/cpu.hh
View File

@@ -345,37 +345,6 @@ class FullO3CPU : public BaseO3CPU
void vecRenameMode(Enums::VecRegRenameMode vec_mode)
{ vecMode = vec_mode; }
/**
* Read physical vector register lane
*/
template<typename VE, int LaneIdx>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
return regFile.readVecLane<VE, LaneIdx>(phys_reg);
}
/**
* Read physical vector register lane
*/
template<typename VE>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
cpuStats.vecRegfileReads++;
return regFile.readVecLane<VE>(phys_reg);
}
/** Write a lane of the destination vector register. */
template<typename LD>
void
setVecLane(PhysRegIdPtr phys_reg, const LD& val)
{
cpuStats.vecRegfileWrites++;
return regFile.setVecLane(phys_reg, val);
}
const TheISA::VecElem& readVecElem(PhysRegIdPtr reg_idx) const;
const TheISA::VecPredRegContainer&
@@ -407,27 +376,6 @@ class FullO3CPU : public BaseO3CPU
/** Read architectural vector register for modification. */
TheISA::VecRegContainer& getWritableArchVecReg(int reg_idx, ThreadID tid);
/** Read architectural vector register lane. */
template<typename VE>
VecLaneT<VE, true>
readArchVecLane(int reg_idx, int lId, ThreadID tid) const
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
return readVecLane<VE>(phys_reg);
}
/** Write a lane of the destination vector register. */
template<typename LD>
void
setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val)
{
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
RegId(VecRegClass, reg_idx));
setVecLane(phys_reg, val);
}
const TheISA::VecElem& readArchVecElem(const RegIndex& reg_idx,
const ElemIndex& ldx, ThreadID tid) const;

30
src/cpu/o3/regfile.hh
View File

@@ -216,36 +216,6 @@ class PhysRegFile
return const_cast<TheISA::VecRegContainer&>(readVecReg(phys_reg));
}
/** Reads a vector register lane. */
template <typename VE, int LaneIdx>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
return readVecReg(phys_reg).laneView<VE, LaneIdx>();
}
/** Reads a vector register lane. */
template <typename VE>
VecLaneT<VE, true>
readVecLane(PhysRegIdPtr phys_reg) const
{
return readVecReg(phys_reg).laneView<VE>(phys_reg->elemIndex());
}
/** Get a vector register lane for modification. */
template <typename LD>
void
setVecLane(PhysRegIdPtr phys_reg, const LD& val)
{
assert(phys_reg->isVectorPhysReg());
DPRINTF(IEW, "RegFile: Setting vector register %i[%d] to %lx\n",
int(phys_reg->index()), phys_reg->elemIndex(), val);
vectorRegFile[phys_reg->index()].laneView<typename LD::UnderlyingType>(
phys_reg->elemIndex()) = val;
}
/** Reads a vector element. */
const TheISA::VecElem &
readVecElem(PhysRegIdPtr phys_reg) const

76
src/cpu/o3/thread_context.hh
View File

@@ -219,67 +219,6 @@ class O3ThreadContext : public ThreadContext
return getWritableVecRegFlat(flattenRegId(id).index());
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
ConstVecLane8
readVec8BitLaneReg(const RegId& id) const override
{
return readVecLaneFlat<uint8_t>(flattenRegId(id).index(),
id.elemIndex());
}
/** Reads source vector 16bit operand. */
ConstVecLane16
readVec16BitLaneReg(const RegId& id) const override
{
return readVecLaneFlat<uint16_t>(flattenRegId(id).index(),
id.elemIndex());
}
/** Reads source vector 32bit operand. */
ConstVecLane32
readVec32BitLaneReg(const RegId& id) const override
{
return readVecLaneFlat<uint32_t>(flattenRegId(id).index(),
id.elemIndex());
}
/** Reads source vector 64bit operand. */
ConstVecLane64
readVec64BitLaneReg(const RegId& id) const override
{
return readVecLaneFlat<uint64_t>(flattenRegId(id).index(),
id.elemIndex());
}
/** Write a lane of the destination vector register. */
void
setVecLane(const RegId& reg,
const LaneData<LaneSize::Byte>& val) override
{
return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
void
setVecLane(const RegId& reg,
const LaneData<LaneSize::TwoByte>& val) override
{
return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
void
setVecLane(const RegId& reg,
const LaneData<LaneSize::FourByte>& val) override
{
return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
void
setVecLane(const RegId& reg,
const LaneData<LaneSize::EightByte>& val) override
{
return setVecLaneFlat(flattenRegId(reg).index(), reg.elemIndex(), val);
}
/** @} */
const TheISA::VecElem &
readVecElem(const RegId& reg) const override
{
@@ -443,21 +382,6 @@ class O3ThreadContext : public ThreadContext
void setVecRegFlat(RegIndex idx,
const TheISA::VecRegContainer& val) override;
template <typename VE>
VecLaneT<VE, true>
readVecLaneFlat(RegIndex idx, int lId) const
{
return cpu->template readArchVecLane<VE>(idx, lId,
thread->threadId());
}
template <typename LD>
void
setVecLaneFlat(int idx, int lId, const LD& val)
{
cpu->template setArchVecLane(idx, lId, thread->threadId(), val);
}
const TheISA::VecElem &readVecElemFlat(RegIndex idx,
const ElemIndex& elemIndex) const override;
void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,

93
src/cpu/simple_thread.hh
View File

@@ -310,85 +310,6 @@ class SimpleThread : public ThreadState, public ThreadContext
return regVal;
}
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector <T> operand. */
template <typename T>
VecLaneT<T, true>
readVecLane(const RegId& reg) const
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
auto regVal = readVecLaneFlat<T>(flatIndex, reg.elemIndex());
DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] as %lx.\n",
reg.index(), flatIndex, reg.elemIndex(), regVal);
return regVal;
}
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
readVec8BitLaneReg(const RegId &reg) const override
{
return readVecLane<uint8_t>(reg);
}
/** Reads source vector 16bit operand. */
virtual ConstVecLane16
readVec16BitLaneReg(const RegId &reg) const override
{
return readVecLane<uint16_t>(reg);
}
/** Reads source vector 32bit operand. */
virtual ConstVecLane32
readVec32BitLaneReg(const RegId &reg) const override
{
return readVecLane<uint32_t>(reg);
}
/** Reads source vector 64bit operand. */
virtual ConstVecLane64
readVec64BitLaneReg(const RegId &reg) const override
{
return readVecLane<uint64_t>(reg);
}
/** Write a lane of the destination vector register. */
template <typename LD>
void
setVecLaneT(const RegId &reg, const LD &val)
{
int flatIndex = isa->flattenVecIndex(reg.index());
assert(flatIndex < TheISA::NumVecRegs);
setVecLaneFlat(flatIndex, reg.elemIndex(), val);
DPRINTF(VecRegs, "Reading vector lane %d (%d)[%d] to %lx.\n",
reg.index(), flatIndex, reg.elemIndex(), val);
}
virtual void
setVecLane(const RegId &reg, const LaneData<LaneSize::Byte> &val) override
{
return setVecLaneT(reg, val);
}
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::TwoByte> &val) override
{
return setVecLaneT(reg, val);
}
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::FourByte> &val) override
{
return setVecLaneT(reg, val);
}
virtual void
setVecLane(const RegId &reg,
const LaneData<LaneSize::EightByte> &val) override
{
return setVecLaneT(reg, val);
}
/** @} */
const TheISA::VecElem &
readVecElem(const RegId &reg) const override
{
@@ -609,20 +530,6 @@ class SimpleThread : public ThreadState, public ThreadContext
vecRegs[reg] = val;
}
template <typename T>
VecLaneT<T, true>
readVecLaneFlat(RegIndex reg, int lId) const
{
return vecRegs[reg].laneView<T>(lId);
}
template <typename LD>
void
setVecLaneFlat(RegIndex reg, int lId, const LD &val)
{
vecRegs[reg].laneView<typename LD::UnderlyingType>(lId) = val;
}
const TheISA::VecElem &
readVecElemFlat(RegIndex reg, const ElemIndex &elemIndex) const override
{

29
src/cpu/thread_context.hh
View File

@@ -205,35 +205,6 @@ class ThreadContext : public PCEventScope
readVecReg(const RegId& reg) const = 0;
virtual TheISA::VecRegContainer& getWritableVecReg(const RegId& reg) = 0;
/** Vector Register Lane Interfaces. */
/** @{ */
/** Reads source vector 8bit operand. */
virtual ConstVecLane8
readVec8BitLaneReg(const RegId& reg) const = 0;
/** Reads source vector 16bit operand. */
virtual ConstVecLane16
readVec16BitLaneReg(const RegId& reg) const = 0;
/** Reads source vector 32bit operand. */
virtual ConstVecLane32
readVec32BitLaneReg(const RegId& reg) const = 0;
/** Reads source vector 64bit operand. */
virtual ConstVecLane64
readVec64BitLaneReg(const RegId& reg) const = 0;
/** Write a lane of the destination vector register. */
virtual void setVecLane(const RegId& reg,
const LaneData<LaneSize::Byte>& val) = 0;
virtual void setVecLane(const RegId& reg,
const LaneData<LaneSize::TwoByte>& val) = 0;
virtual void setVecLane(const RegId& reg,
const LaneData<LaneSize::FourByte>& val) = 0;
virtual void setVecLane(const RegId& reg,
const LaneData<LaneSize::EightByte>& val) = 0;
/** @} */
virtual const TheISA::VecElem& readVecElem(const RegId& reg) const = 0;
virtual const TheISA::VecPredRegContainer& readVecPredReg(