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configs, tests: Amend stdlib configs to use WalkCache hierarchy

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As X86 and RISCV are relying on a Table Walker cache, we
change their stdlib configs to use the newly defined

PrivateL1PrivateL2WalkCacheHierarchy

Change-Id: I63c3f70a9daa3b2c7a8306e51af8065bf1bea92b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-03-14 15:15:46 +00:00
parent d32a438913
commit 058dd7e195
10 changed files with 30 additions and 30 deletions
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6
tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py
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@@ -34,8 +34,8 @@ This configuration serves as a test of restoring a checkpoint with X86 ISA in fs
"""
from gem5.components.boards.x86_board import X86Board
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
PrivateL1PrivateL2WalkCacheHierarchy,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
@@ -54,7 +54,7 @@ requires(isa_required=ISA.X86)
# Setup the cache hierarchy.
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
)

6
tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py
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@@ -34,8 +34,8 @@ with X86 ISA in fs mode.
import argparse
from gem5.components.boards.x86_board import X86Board
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
PrivateL1PrivateL2WalkCacheHierarchy,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
@@ -63,7 +63,7 @@ requires(isa_required=ISA.X86)
# Setup the cache hierarchy.
# For classic, PrivateL1PrivateL2 and NoCache have been tested.
# For Ruby, MESI_Two_Level and MI_example have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32kB", l1i_size="32kB", l2_size="512kB"
)

6
tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py
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@@ -146,11 +146,11 @@ args = parser.parse_args()
# Setup the cachie hierarchy.
if args.mem_system == "classic":
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
PrivateL1PrivateL2WalkCacheHierarchy,
)
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32kB", l1i_size="32kB", l2_size="256kB"
)
elif args.mem_system == "mesi_two_level":

6
tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py
View File

@@ -104,12 +104,12 @@ args = parser.parse_args()
requires(isa_required=ISA.RISCV)
if args.mem_system == "classic":
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
PrivateL1PrivateL2WalkCacheHierarchy,
)
# Setup the cache hierarchy.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)
elif args.mem_system == "mesi_two_level":

6
tests/gem5/suite_tests/configs/suite_run_workload.py
View File

@@ -35,8 +35,8 @@ import argparse
from m5.util import panic
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import (
PrivateL1PrivateL2CacheHierarchy,
from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import (
PrivateL1PrivateL2WalkCacheHierarchy,
)
from gem5.components.memory import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
@@ -92,7 +92,7 @@ parser.add_argument(
args = parser.parse_args()
# Setup the cache hierarchy.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy(
l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
)