From 058dd7e195b8e0875d5ad1aaaebdbd4d7838f633 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 14 Mar 2024 15:15:46 +0000 Subject: [PATCH] configs, tests: Amend stdlib configs to use WalkCache hierarchy As X86 and RISCV are relying on a Table Walker cache, we change their stdlib configs to use the newly defined PrivateL1PrivateL2WalkCacheHierarchy Change-Id: I63c3f70a9daa3b2c7a8306e51af8065bf1bea92b Signed-off-by: Giacomo Travaglini --- .../gem5_library/checkpoints/simpoints-se-restore.py | 6 +++--- .../gem5_library/looppoints/restore-looppoint-checkpoint.py | 6 +++--- configs/example/gem5_library/riscv-fs.py | 6 +++--- configs/example/gem5_library/riscv-ubuntu-run.py | 6 +++--- configs/example/lupv/run_lupv.py | 6 +++--- .../checkpoint_tests/configs/x86-fs-restore-checkpoint.py | 6 +++--- .../gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py | 6 +++--- tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py | 6 +++--- tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py | 6 +++--- tests/gem5/suite_tests/configs/suite_run_workload.py | 6 +++--- 10 files changed, 30 insertions(+), 30 deletions(-) diff --git a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py index a3639a63bb..ac3d8c9e23 100644 --- a/configs/example/gem5_library/checkpoints/simpoints-se-restore.py +++ b/configs/example/gem5_library/checkpoints/simpoints-se-restore.py @@ -60,8 +60,8 @@ from m5.stats import ( ) from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) from gem5.components.memory import DualChannelDDR4_2400 from gem5.components.processors.cpu_types import CPUTypes @@ -80,7 +80,7 @@ requires(isa_required=ISA.X86) # The cache hierarchy can be different from the cache hierarchy used in taking # the checkpoints -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32kB", l1i_size="32kB", l2_size="256kB", diff --git a/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py b/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py index 781b2f7281..a97ea39d17 100644 --- a/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py +++ b/configs/example/gem5_library/looppoints/restore-looppoint-checkpoint.py @@ -48,8 +48,8 @@ from m5.stats import ( ) from gem5.components.boards.simple_board import SimpleBoard -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) from gem5.components.memory import DualChannelDDR4_2400 from gem5.components.processors.cpu_types import CPUTypes @@ -90,7 +90,7 @@ args = parser.parse_args() # The cache hierarchy can be different from the cache hierarchy used in taking # the checkpoints -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32kB", l1i_size="32kB", l2_size="256kB", diff --git a/configs/example/gem5_library/riscv-fs.py b/configs/example/gem5_library/riscv-fs.py index 914d9a7023..1d1b01e560 100644 --- a/configs/example/gem5_library/riscv-fs.py +++ b/configs/example/gem5_library/riscv-fs.py @@ -40,8 +40,8 @@ Characteristics """ from gem5.components.boards.riscv_board import RiscvBoard -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes @@ -57,7 +57,7 @@ requires(isa_required=ISA.RISCV) # Setup the cache hierarchy. # For classic, PrivateL1PrivateL2 and NoCache have been tested. # For Ruby, MESI_Two_Level and MI_example have been tested. -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB" ) diff --git a/configs/example/gem5_library/riscv-ubuntu-run.py b/configs/example/gem5_library/riscv-ubuntu-run.py index 1d31b055de..3ec51bd3a4 100644 --- a/configs/example/gem5_library/riscv-ubuntu-run.py +++ b/configs/example/gem5_library/riscv-ubuntu-run.py @@ -57,12 +57,12 @@ from gem5.utils.requires import requires requires(isa_required=ISA.RISCV) # With RISCV, we use simple caches. -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) # Here we setup the parameters of the l1 and l2 caches. -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="16kB", l1i_size="16kB", l2_size="256kB" ) diff --git a/configs/example/lupv/run_lupv.py b/configs/example/lupv/run_lupv.py index 4be6b924a5..44a4b2dd31 100644 --- a/configs/example/lupv/run_lupv.py +++ b/configs/example/lupv/run_lupv.py @@ -49,8 +49,8 @@ from gem5.utils.requires import requires # Run a check to ensure the right version of gem5 is being used. requires(isa_required=ISA.RISCV) -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) parser = argparse.ArgumentParser(description="Runs Linux fs test with RISCV.") @@ -72,7 +72,7 @@ parser.add_argument( args = parser.parse_args() -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB" ) diff --git a/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py b/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py index 6286fc0544..7fb9a483ff 100644 --- a/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/x86-fs-restore-checkpoint.py @@ -34,8 +34,8 @@ This configuration serves as a test of restoring a checkpoint with X86 ISA in fs """ from gem5.components.boards.x86_board import X86Board -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes @@ -54,7 +54,7 @@ requires(isa_required=ISA.X86) # Setup the cache hierarchy. # For classic, PrivateL1PrivateL2 and NoCache have been tested. # For Ruby, MESI_Two_Level and MI_example have been tested. -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32kB", l1i_size="32kB", l2_size="512kB" ) diff --git a/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py b/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py index fb800209e0..e206cb39b8 100644 --- a/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py +++ b/tests/gem5/checkpoint_tests/configs/x86-fs-save-checkpoint.py @@ -34,8 +34,8 @@ with X86 ISA in fs mode. import argparse from gem5.components.boards.x86_board import X86Board -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes @@ -63,7 +63,7 @@ requires(isa_required=ISA.X86) # Setup the cache hierarchy. # For classic, PrivateL1PrivateL2 and NoCache have been tested. # For Ruby, MESI_Two_Level and MI_example have been tested. -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32kB", l1i_size="32kB", l2_size="512kB" ) diff --git a/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py b/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py index 606205f103..5a9d5e6e47 100644 --- a/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py +++ b/tests/gem5/parsec_benchmarks/configs/parsec_disk_run.py @@ -146,11 +146,11 @@ args = parser.parse_args() # Setup the cachie hierarchy. if args.mem_system == "classic": - from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, + from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) - cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( + cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32kB", l1i_size="32kB", l2_size="256kB" ) elif args.mem_system == "mesi_two_level": diff --git a/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py b/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py index 0192d3dbff..5dfc082e66 100644 --- a/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py +++ b/tests/gem5/riscv_boot_tests/configs/riscv_boot_exit_run.py @@ -104,12 +104,12 @@ args = parser.parse_args() requires(isa_required=ISA.RISCV) if args.mem_system == "classic": - from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, + from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) # Setup the cache hierarchy. - cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( + cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB" ) elif args.mem_system == "mesi_two_level": diff --git a/tests/gem5/suite_tests/configs/suite_run_workload.py b/tests/gem5/suite_tests/configs/suite_run_workload.py index a9f980d53f..ebf86b5eb0 100644 --- a/tests/gem5/suite_tests/configs/suite_run_workload.py +++ b/tests/gem5/suite_tests/configs/suite_run_workload.py @@ -35,8 +35,8 @@ import argparse from m5.util import panic -from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy import ( - PrivateL1PrivateL2CacheHierarchy, +from gem5.components.cachehierarchies.classic.private_l1_private_l2_walk_cache_hierarchy import ( + PrivateL1PrivateL2WalkCacheHierarchy, ) from gem5.components.memory import SingleChannelDDR3_1600 from gem5.components.processors.cpu_types import CPUTypes @@ -92,7 +92,7 @@ parser.add_argument( args = parser.parse_args() # Setup the cache hierarchy. -cache_hierarchy = PrivateL1PrivateL2CacheHierarchy( +cache_hierarchy = PrivateL1PrivateL2WalkCacheHierarchy( l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB" )