SPARC: Truncate syscall args and return values appropriately.
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@@ -50,13 +50,23 @@ namespace SparcISA
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tc->setIntReg(NumIntArchRegs + 2,
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tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
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//tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
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tc->setIntReg(ReturnValueReg, return_value.value());
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IntReg val = return_value.value();
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if (bits(tc->readMiscRegNoEffect(
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SparcISA::MISCREG_PSTATE), 3, 3)) {
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val = bits(val, 31, 0);
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}
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tc->setIntReg(ReturnValueReg, val);
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} else {
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// got an error, set XCC.C
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tc->setIntReg(NumIntArchRegs + 2,
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tc->readIntReg(NumIntArchRegs + 2) | 0x11);
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//tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
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tc->setIntReg(ReturnValueReg, -return_value.value());
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IntReg val = -return_value.value();
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if (bits(tc->readMiscRegNoEffect(
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SparcISA::MISCREG_PSTATE), 3, 3)) {
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val = bits(val, 31, 0);
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}
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tc->setIntReg(ReturnValueReg, val);
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}
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}
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};
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@@ -385,8 +385,15 @@ class SimpleThread : public ThreadState
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TheISA::IntReg getSyscallArg(int i)
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{
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assert(i < TheISA::NumArgumentRegs);
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return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
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TheISA::ArgumentReg[i]));
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TheISA::IntReg val = regs.readIntReg(
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TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
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#if THE_ISA == SPARC_ISA
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if (bits(this->readMiscRegNoEffect(
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SparcISA::MISCREG_PSTATE), 3, 3)) {
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val = bits(val, 31, 0);
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}
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#endif
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return val;
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}
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// used to shift args for indirect syscall
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