Get rid of bogus cache assertion.

I was asserting that the only reason you would defer targets is if
a write came in while you had an outstanding read miss, but there's
another case where you could get a read access after you've snooped
an invalidation and buffered it because it applies to a prior
outstanding miss.

src/mem/cache/cache_impl.hh

@@ -823,7 +823,6 @@ Cache<TagStore>::handleResponse(PacketPtr pkt)
     }
 
     if (mshr->promoteDeferredTargets()) {
-        assert(mshr->needsExclusive() && !blk->isWritable());
         // avoid later read getting stale data while write miss is
         // outstanding.. see comment in timingAccess()
         blk->status &= ~BlkReadable;