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fastmodel: Implement the vecPredReg accessor functions.

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Change-Id: Iaf6f7d8d1db427bfd486e4bd43f67cc006751873
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23789
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2019-11-06 14:05:58 -08:00
parent 0b52c24da6
commit 0233515ebf
2 changed files with 39 additions and 11 deletions
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36
src/arch/arm/fastmodel/iris/thread_context.cc
View File

@@ -244,7 +244,8 @@ ThreadContext::ThreadContext(
BaseCPU *cpu, int id, System *system, ::BaseTLB *dtb, ::BaseTLB *itb,
iris::IrisConnectionInterface *iris_if, const std::string &iris_path) :
_cpu(cpu), _threadId(id), _system(system), _dtb(dtb), _itb(itb),
_irisPath(iris_path), vecRegs(TheISA::NumVecRegs),
_irisPath(iris_path), vecRegs(ArmISA::NumVecRegs),
vecPredRegs(ArmISA::NumVecPredRegs),
comInstEventQueue("instruction-based event queue"),
client(iris_if, "client." + iris_path)
{
@@ -545,4 +546,37 @@ ThreadContext::readVecRegFlat(RegIndex idx) const
return readVecReg(RegId(VecRegClass, idx));
}
const ArmISA::VecPredRegContainer &
ThreadContext::readVecPredReg(const RegId &reg_id) const
{
RegIndex idx = reg_id.index();
if (idx >= vecPredRegIds.size())
return vecPredRegs.at(idx);
ArmISA::VecPredRegContainer &reg = vecPredRegs.at(idx);
iris::ResourceReadResult result;
call().resource_read(_instId, result, vecPredRegIds.at(idx));
size_t offset = 0;
size_t num_bits = reg.NUM_BITS;
uint8_t *bytes = (uint8_t *)result.data.data();
while (num_bits > 8) {
reg.set_bits(offset, 8, *bytes);
offset += 8;
num_bits -= 8;
bytes++;
}
if (num_bits)
reg.set_bits(offset, num_bits, *bytes);
return reg;
}
const ArmISA::VecPredRegContainer &
ThreadContext::readVecPredRegFlat(RegIndex idx) const
{
return readVecPredReg(RegId(VecPredRegClass, idx));
}
} // namespace Iris

14
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -68,6 +68,7 @@ class ThreadContext : public ::ThreadContext
// Temporary holding places for the vector reg accessors to return.
// These are not updated live, only when requested.
mutable std::vector<ArmISA::VecRegContainer> vecRegs;
mutable std::vector<ArmISA::VecPredRegContainer> vecPredRegs;
Status _status = Active;
@@ -87,6 +88,7 @@ class ThreadContext : public ::ThreadContext
iris::ResourceId icountRscId;
ResourceIds vecRegIds;
ResourceIds vecPredRegIds;
std::vector<iris::MemorySpaceInfo> memorySpaces;
std::vector<iris::MemorySupportedAddressTranslationResult> translations;
@@ -374,11 +376,7 @@ class ThreadContext : public ::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
const VecPredRegContainer &
readVecPredReg(const RegId &reg) const override
{
panic("%s not implemented.", __FUNCTION__);
}
const VecPredRegContainer &readVecPredReg(const RegId &reg) const override;
VecPredRegContainer &
getWritableVecPredReg(const RegId &reg) override
{
@@ -537,11 +535,7 @@ class ThreadContext : public ::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
const VecPredRegContainer &
readVecPredRegFlat(RegIndex idx) const override
{
panic("%s not implemented.", __FUNCTION__);
}
const VecPredRegContainer &readVecPredRegFlat(RegIndex idx) const override;
VecPredRegContainer &
getWritableVecPredRegFlat(RegIndex idx) override
{