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Change the way the hierarchy is separated. Now all virtual functions are in the interfaces. This allows new bus models to be used without major hassle. And I thought it was time to change it all again anyways.

Browse Source 
cpu/simple_cpu/simple_cpu.cc:
    Switch doEvents to doEvents()

--HG--
extra : convert_revision : 14b9517017e76c7b941247004393bf260f397d9a
This commit is contained in:
Erik Hallnor
2004-01-25 05:01:00 -05:00
parent fde0b7bfaf
commit 01059eaded
1 changed files with 3 additions and 3 deletions
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6
cpu/simple_cpu/simple_cpu.cc
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@@ -349,7 +349,7 @@ SimpleCPU::read(Addr addr, T& data, unsigned flags)
// Ugly hack to get an event scheduled *only* if the access is
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents) {
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
unscheduleTickEvent();
@@ -432,7 +432,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Ugly hack to get an event scheduled *only* if the access is
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && dcacheInterface->doEvents) {
if (result != MA_HIT && dcacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastDcacheStall = curTick;
unscheduleTickEvent();
@@ -635,7 +635,7 @@ SimpleCPU::tick()
// Ugly hack to get an event scheduled *only* if the access is
// a miss. We really should add first-class support for this
// at some point.
if (result != MA_HIT && icacheInterface->doEvents) {
if (result != MA_HIT && icacheInterface->doEvents()) {
memReq->completionEvent = &cacheCompletionEvent;
lastIcacheStall = curTick;
unscheduleTickEvent();