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ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

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This eliminates a use of the ExtMachInst type outside of the ISAs.
This commit is contained in:
Gabe Black
2012-06-04 10:57:23 -07:00
parent 6437f3f4ee
commit 008b17d816
17 changed files with 224 additions and 19 deletions
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1
src/arch/alpha/SConscript
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@@ -40,6 +40,7 @@ if env['TARGET_ISA'] == 'alpha':
Source('interrupts.cc')
Source('ipr.cc')
Source('isa.cc')
Source('isa_traits.cc')
Source('kernel_stats.cc')
Source('linux/linux.cc')
Source('linux/process.cc')

41
src/arch/alpha/isa_traits.cc Normal file
View File

@@ -0,0 +1,41 @@
/*
* Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/alpha/generated/decoder.hh"
#include "arch/alpha/isa_traits.hh"
namespace AlphaISA
{
// Alpha UNOP (ldq_u r31,0(r0))
const StaticInstPtr NoopStaticInst =
AlphaISAInst::makeNop(new AlphaISAInst::Ldq_u(0x2ffe0000));
}

3
src/arch/alpha/isa_traits.hh
View File

@@ -123,8 +123,7 @@ enum {
};
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
const ExtMachInst NoopMachInst = 0x2ffe0000;
const extern StaticInstPtr NoopStaticInst;
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;

1
src/arch/mips/SConscript
View File

@@ -40,6 +40,7 @@ if env['TARGET_ISA'] == 'mips':
Source('idle_event.cc')
Source('interrupts.cc')
Source('isa.cc')
Source('isa_traits.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('linux/system.cc')

39
src/arch/mips/isa_traits.cc Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/mips/generated/decoder.hh"
#include "arch/mips/isa_traits.hh"
namespace MipsISA
{
const StaticInstPtr NoopStaticInst = new MipsISAInst::Nop("", 0x00000000);
}

2
src/arch/mips/isa_traits.hh
View File

@@ -143,7 +143,7 @@ enum mode_type
};
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
const extern StaticInstPtr NoopStaticInst;
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);

1
src/arch/power/SConscript
View File

@@ -42,6 +42,7 @@ if env['TARGET_ISA'] == 'power':
Source('insts/condition.cc')
Source('insts/static_inst.cc')
Source('interrupts.cc')
Source('isa_traits.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('pagetable.cc')

40
src/arch/power/isa_traits.cc Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/power/generated/decoder.hh"
#include "arch/power/isa_traits.hh"
namespace PowerISA
{
// This is ori 0, 0, 0
const StaticInstPtr NoopStaticInst = new PowerISAInst::Or(0x60000000);
}

3
src/arch/power/isa_traits.hh
View File

@@ -66,8 +66,7 @@ const int VMPageSize = (1 << LogVMPageSize);
const int MachineBytes = 4;
// This is ori 0, 0, 0
const ExtMachInst NoopMachInst = 0x60000000;
const extern StaticInstPtr NoopStaticInst;
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;

1
src/arch/sparc/SConscript
View File

@@ -37,6 +37,7 @@ if env['TARGET_ISA'] == 'sparc':
Source('faults.cc')
Source('interrupts.cc')
Source('isa.cc')
Source('isa_traits.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('linux/syscalls.cc')

40
src/arch/sparc/isa_traits.cc Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/sparc/generated/decoder.hh"
#include "arch/sparc/isa_traits.hh"
namespace SparcISA
{
const StaticInstPtr NoopStaticInst =
new SparcISAInst::Nop("nop", 0x01000000, No_OpClass);
}

2
src/arch/sparc/isa_traits.hh
View File

@@ -50,7 +50,7 @@ using namespace BigEndianGuest;
#define ISA_HAS_DELAY_SLOT 1
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
extern const StaticInstPtr NoopStaticInst;
// 8K. This value is implmentation specific; and should probably
// be somewhere else.

1
src/arch/x86/SConscript
View File

@@ -57,6 +57,7 @@ if env['TARGET_ISA'] == 'x86':
Source('insts/static_inst.cc')
Source('interrupts.cc')
Source('isa.cc')
Source('isa_traits.cc')
Source('linux/linux.cc')
Source('linux/process.cc')
Source('linux/syscalls.cc')

39
src/arch/x86/isa_traits.cc Normal file
View File

@@ -0,0 +1,39 @@
/*
* Copyright (c) 2012 Google
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
*/
#include "arch/x86/generated/decoder.hh"
#include "arch/x86/x86_traits.hh"
namespace X86ISA
{
const StaticInstPtr NoopStaticInst = new X86ISAInst::NOP(NoopMachInst);
}

13
src/arch/x86/isa_traits.hh
View File

@@ -43,6 +43,7 @@
#include "arch/x86/types.hh"
#include "arch/x86/x86_traits.hh"
#include "base/types.hh"
#include "cpu/static_inst_fwd.hh"
namespace LittleEndianGuest {}
@@ -71,17 +72,7 @@ namespace X86ISA
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;
const ExtMachInst NoopMachInst = {
0x0, // No legacy prefixes.
0x0, // No rex prefix.
{ 1, 0x0, 0x0, 0x90 }, // One opcode byte, 0x90.
0x0, 0x0, // No modrm or sib.
0, 0, // No immediate or displacement.
8, 8, 8, // All sizes are 8.
0, // Displacement size is 0.
SixtyFourBitMode // Behave as if we're in 64 bit
// mode (this doesn't actually matter).
};
extern const StaticInstPtr NoopStaticInst;
}
#endif // __ARCH_X86_ISATRAITS_HH__

13
src/arch/x86/x86_traits.hh
View File

@@ -40,6 +40,7 @@
#include <cassert>
#include "arch/x86/types.hh"
#include "base/types.hh"
namespace X86ISA
@@ -104,6 +105,18 @@ namespace X86ISA
assert(addr < PhysAddrAPICRangeSize);
return PhysAddrPrefixInterrupts | (id * PhysAddrAPICRangeSize) | addr;
}
const ExtMachInst NoopMachInst = {
0x0, // No legacy prefixes.
0x0, // No rex prefix.
{ 1, 0x0, 0x0, 0x90 }, // One opcode byte, 0x90.
0x0, 0x0, // No modrm or sib.
0, 0, // No immediate or displacement.
8, 8, 8, // All sizes are 8.
0, // Displacement size is 0.
SixtyFourBitMode // Behave as if we're in 64 bit
// mode (this doesn't actually matter).
};
}
#endif //__ARCH_X86_X86TRAITS_HH__

3
src/cpu/o3/fetch_impl.hh
View File

@@ -661,8 +661,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
// We will use a nop in ordier to carry the fault.
DynInstPtr instruction = buildInst(tid,
decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()),
DynInstPtr instruction = buildInst(tid, TheISA::NoopStaticInst,
NULL, fetchPC, fetchPC, false);
instruction->setPredTarg(fetchPC);