5543 lines
258 KiB
BibTeX
5543 lines
258 KiB
BibTeX
% Encoding: UTF-8
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@Misc{boxsmartbench15,
|
||
author = {\mbox{123 SmartMobile}},
|
||
title = {{SmartBench: A multi-core friendly benchmark application}},
|
||
howpublished = {\url{play.google.com/store/apps/details?id=com.smartbench.eleven}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.18},
|
||
year = {2011, Last Access: 18.02.2015},
|
||
}
|
||
|
||
@Other{boxvis_07,
|
||
author = {\mbox{Automotive Electronics Council}},
|
||
groups = {MJ:1},
|
||
institution = {Component Technical Committee},
|
||
month = {May},
|
||
organization = {Automotive Electronics Council},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-26},
|
||
title = {{FAILURE} {MECHANISM} {BASED} {STRESS} {TEST} {QUALIFICATION} {FOR} {INTEGRATED} {CIRCUITS}},
|
||
year = {2007},
|
||
}
|
||
|
||
@Misc{boxcadence14,
|
||
author = {\mbox{Cadence Inc.}},
|
||
title = {{C}adence {D}enali {DDR} {M}emory {IP}},
|
||
howpublished = {\url{http://ip.cadence.com/ipportfolio/ip-portfolio-overview/memory-ip/ddr-lpddr}},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2020-06-09},
|
||
year = {2014, last access 18.02.2015},
|
||
}
|
||
|
||
@Misc{boxvirtual15,
|
||
author = {\mbox{Cadence, Inc}},
|
||
editor = {Synopsys, Inc},
|
||
title = {{V}irtual {S}ystem {P}latform},
|
||
howpublished = {\url{http://www.cadence.com/products/sd/virtual_system/pages/default.aspx}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2015, last access: 20.01.2015},
|
||
}
|
||
|
||
@Misc{boxaceexplorer14,
|
||
author = {\mbox{DOCEA Power}},
|
||
title = {{A}ce{T}hermal{M}odeler and {A}ceplorer},
|
||
howpublished = {\url{http://www.doceapower.com}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2014, last access: 20.01.2015},
|
||
}
|
||
|
||
@Misc{boxandebench15,
|
||
author = {\mbox{EEMBC Inc.}},
|
||
title = {{A}nd{EB}ench: {A}n {EEMBC} {B}enchmark for {A}ndroid {D}evices},
|
||
howpublished = {\url{http://www.eembc.org/andebench/about.php}},
|
||
url = {\url{http://www.eembc.org/andebench/about.php}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.18},
|
||
year = {2013, last access 18.02.2015},
|
||
}
|
||
|
||
@Misc{box0xbench13,
|
||
author = {\mbox{Google Inc.}},
|
||
title = {{0xBench: Comprehensive Benchmark Suite for Android}},
|
||
url = {\url{http://code.google.com/p/0xbench/}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.18},
|
||
year = {2013},
|
||
}
|
||
|
||
@Other{boxhmc_13,
|
||
author = {\mbox{Hybrid Memory Cube Consortium}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
revision = {1.0},
|
||
timestamp = {2019-06-16},
|
||
title = {{H}ybrid {M}emory {C}ube {S}pecification},
|
||
url = {http://www.hybridmemorycube.org/},
|
||
year = {2013},
|
||
}
|
||
|
||
@Article{box_12a,
|
||
author = {\mbox{IEEE Computer Society}},
|
||
title = {{IEEE} {S}tandard for {S}tandard {S}ystem{C} {L}anguage {R}eference {M}anual},
|
||
number = {IEEE Std 1666-2011},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-09},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{box_15,
|
||
author = {\mbox{JEDEC Solid State Technology Association}},
|
||
title = {{H}igh {B}andwidth {M}emory ({HBM}) {DRAM}},
|
||
groups = {MJ:1},
|
||
journal = {JEDEC Standard JESD235A},
|
||
owner = {MJ},
|
||
timestamp = {2016-08-19},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{box_14,
|
||
author = {\mbox{Jedec Solid State Technology Association}},
|
||
title = {{LPDDR}4 ({JESD} 209-4)},
|
||
booktitle = {{JEDEC STANDARD}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
series = {{Jedec Standard}},
|
||
timestamp = {2016-08-19},
|
||
year = {2014},
|
||
}
|
||
|
||
@Article{box_12,
|
||
author = {\mbox{JEDEC Solid State Technology Association}},
|
||
title = {{L}ow {P}ower {D}ouble {D}ata {R}ate 3 ({LPDDR}3)},
|
||
groups = {MJ:1},
|
||
journal = {JEDEC Standard JESD209-3},
|
||
owner = {MJ},
|
||
timestamp = {2016-08-19},
|
||
year = {2012},
|
||
}
|
||
|
||
@Misc{boxddr312,
|
||
author = {\mbox{Jedec Solid State Technology Association}},
|
||
title = {{DDR}3 {SDRAM} ({JESD} 79-3)},
|
||
booktitle = {{JEDEC STANDARD}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
series = {{Jedec Standard}},
|
||
timestamp = {2015.01.20},
|
||
year = {2012},
|
||
}
|
||
|
||
@Misc{boxddr412,
|
||
author = {\mbox{Jedec Solid State Technology Association}},
|
||
title = {{DDR}4 {SDRAM} ({JESD} 79-4)},
|
||
booktitle = {{JEDEC STANDARD}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
series = {{Jedec Standard}},
|
||
timestamp = {2015.01.20},
|
||
year = {2012},
|
||
}
|
||
|
||
@Misc{boxwide11,
|
||
author = {\mbox{Jedec Solid State Technology Association}},
|
||
title = {{W}ide {I}/{O} {S}ingle {D}ata {R}ate ({JESD} 229)},
|
||
booktitle = {{JEDEC STANDARD}},
|
||
groups = {MJ:1},
|
||
month = {Dec.},
|
||
owner = {MJ},
|
||
series = {{Jedec Standard}},
|
||
timestamp = {2015.01.20},
|
||
year = {2011},
|
||
}
|
||
|
||
@Misc{boxmediabench,
|
||
author = {\mbox{MediaBench Consortium}},
|
||
title = {{M}ediabench},
|
||
howpublished = {\url{http://euler.slu.edu/~fritts/mediabench/}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.12},
|
||
year = {2015, last access 28.02.2015},
|
||
}
|
||
|
||
@Article{mictec_13,
|
||
author = {\mbox{Micron Technology Inc.}},
|
||
title = {4{G}b: x16, x32 {M}obile {LPDDR}3 {SDRAM}},
|
||
groups = {MJ:1},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.06},
|
||
year = {2013},
|
||
}
|
||
|
||
@Article{box_06,
|
||
author = {\mbox{Micron Technology Inc.}},
|
||
title = {1{G}b: x4, x8, x16 {DDR}3 {SDRAM}},
|
||
groups = {MJ:1},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-08},
|
||
year = {2006},
|
||
}
|
||
|
||
@Electronic{box_16,
|
||
author = {\mbox{Micron Technology, Inc.}},
|
||
title = {{DDR}4 {SDRAM} - {MT}40{A}2{G}4},
|
||
url = {https://www.micron.com/products/dram/ddr4-sdram/8Gb#/},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@Electronic{box_16a,
|
||
author = {\mbox{Micron Technology, Inc.}},
|
||
title = {{A}utomotive {DDR}4 {SDRAM} ({MT}40{A}1{G}8)},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-26},
|
||
year = {2016},
|
||
}
|
||
|
||
@Electronic{box_15a,
|
||
author = {\mbox{Micron Technology, Inc.}},
|
||
title = {8{GB} (x64, {SR}) 288-{P}in {DDR}4 {UDIMM} - {MTA}8{ATF}1{G}64{AZ} – 8{GB}},
|
||
url = {https://www.micron.com/parts/modules/ddr4-sdram/mta8atf1g64az-2g3},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{boxmemmax,
|
||
author = {\mbox{Sonics}},
|
||
title = {{M}em{M}ax-{S}cheduler},
|
||
howpublished = {\url{http://sonicsinc.com/products/memory-subsystems/memmax-scheduler/}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.17},
|
||
}
|
||
|
||
@Misc{boxdesignware,
|
||
author = {\mbox{Synopsys Inc.}},
|
||
title = {{DesignWare TLM Library}},
|
||
howpublished = {\url{http://www.synopsys.com/Systems/VirtualPrototyping/VPModels/Pages/DW-TLM-Library.aspx}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.17},
|
||
}
|
||
|
||
@Misc{boxdesignware15,
|
||
author = {\mbox{Synopsys, Inc.}},
|
||
title = {{D}esign{W}are {DDR} {IP}},
|
||
howpublished = {http://www.synopsys.com/IP/InterfaceIP/DDRn/Pages/},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-04-19},
|
||
year = {2015, Last Access: 18.02.2015},
|
||
}
|
||
|
||
@Misc{synsynopsys12,
|
||
author = {\mbox{Synopsys, Inc}},
|
||
editor = {Synopsys, Inc},
|
||
title = {{S}ynopsys {V}irtual {P}rototyping {S}olution},
|
||
howpublished = {\url{http://www.synopsys.com/Systems/VirtualPrototyping/Pages/default.aspx}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2015, last access: 20.01.2015},
|
||
}
|
||
|
||
@Misc{boxmemory15,
|
||
author = {\mbox{Xilinx, Inc.}},
|
||
title = {{M}emory {I}nterface {G}enerator ({MIG})},
|
||
howpublished = {\url{http://www.xilinx.com/products/intellectual-property/mig.html}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.18},
|
||
year = {2015, Last Access: 18.02.2015},
|
||
}
|
||
|
||
@Article{boxxilinx_15,
|
||
author = {\mbox{Xilinx}},
|
||
title = {z{C}706 {E}valuation {B}oard for the {Z}ynq-7000 {XC}7{Z}045 {A}ll {P}rogrammable {S}oc {U}ser {G}uide},
|
||
groups = {MJ:1},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.15},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{aarbru_87,
|
||
author = {Aardenne-Ehrenfest, T and de Bruijn, NG},
|
||
title = {{C}ircuits and {T}rees in {O}riented {L}inear {G}raphs},
|
||
pages = {149--163},
|
||
groups = {MJ:1},
|
||
journal = {Classic Papers in Combinatorics},
|
||
owner = {MJ},
|
||
publisher = {Springer},
|
||
timestamp = {2019-09-12},
|
||
year = {1987},
|
||
}
|
||
|
||
@InProceedings{adlfet_16,
|
||
author = {Adler, Rasmus and Feth, Patrick and Schneider, Daniel},
|
||
booktitle = {2016 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshop (DSN-W)},
|
||
title = {{S}afety {E}ngineering for {A}utonomous {V}ehicles},
|
||
doi = {10.1109/DSN-W.2016.30},
|
||
pages = {200-205},
|
||
groups = {MJ:1},
|
||
keywords = {decision making;safety;vehicles;safety engineering;autonomous vehicles;nonautonomous vehicles;safety criticality;decision making process;control commands;Safety;Vehicles;Accidents;Acceleration;Standards;Road transportation;Runtime;safety engineering;autonomous driving;safety cage},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-02},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{advcha_14,
|
||
author = {Advani, Siddharth and Chandramoorthy, N. and Swaminathan, K. and Irick, K. and Cho, Y.C.P. and Sampson, J. and Narayanan, V.},
|
||
booktitle = {32nd IEEE International Conference on Computer Design (ICCD)},
|
||
title = {{R}efresh {E}nabled {V}ideo {A}nalytics ({REVA}): {I}mplications on power and performance of {DRAM} supported embedded visual systems},
|
||
doi = {10.1109/ICCD.2014.6974727},
|
||
pages = {501-504},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;embedded systems;image sensors;low-power electronics;video signal processing;DRAM memory refresh energy;DRAM refresh scheme;Google Glasses;REVA system;battery lifetimes;computational power;embedded architecture;embedded systems;embedded video analytics applications;embedded visual systems;image sensors;memory storage;mobile systems;multiobject scene;refresh enabled video analytics;ubiquitous;video applications;wearable video systems;Computational modeling;Computer architecture;Object recognition;Random access memory;Standards;Streaming media;Visualization},
|
||
month = {Oct},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{agefly_73,
|
||
author = {Agerwala, Tilak and Flynn, Mike},
|
||
booktitle = {Proceedings of the 1st Annual Symposium on Computer Architecture},
|
||
title = {{C}omments on {C}apabilities, {L}imitations and {C}orrectness of {P}etri {N}ets},
|
||
doi = {10.1145/800123.803973},
|
||
pages = {81--86},
|
||
publisher = {ACM},
|
||
series = {ISCA '73},
|
||
url = {http://doi.acm.org/10.1145/800123.803973},
|
||
acmid = {803973},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-27},
|
||
year = {1973},
|
||
}
|
||
|
||
@InProceedings{agrfoh_17,
|
||
author = {Agrawal, Ankit and Fohler, Gerhard},
|
||
booktitle = {Proceedings of the International Symposium on Memory Systems},
|
||
title = {{DRAM}-related {C}hallenges in {T}ask {S}cheduling with {T}iming {P}redictability on {COTS} {M}ulti-cores for {S}afety-critical {S}ystems},
|
||
doi = {10.1145/3132402.3132417},
|
||
isbn = {978-1-4503-5335-9},
|
||
location = {Alexandria, Virginia},
|
||
pages = {265--267},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '17},
|
||
url = {http://doi.acm.org/10.1145/3132402.3132417},
|
||
acmid = {3132417},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {COTS DRAM controller, COTS multi-cores, inter-core interference, safety-critical systems, timing predictability},
|
||
numpages = {3},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-18},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{agroc_16,
|
||
author = {Agrawal, Aditya and O'Connor, Mike and Bolotin, Evgeny and Chatterjee, Niladrish and Emer, Joel and Keckler, Stephen},
|
||
booktitle = {Proceedings of the Second International Symposium on Memory Systems},
|
||
title = {{CLARA}: {C}ircular {L}inked-{L}ist {A}uto and {S}elf {R}efresh {A}rchitecture},
|
||
doi = {10.1145/2989081.2989084},
|
||
isbn = {978-1-4503-4305-3},
|
||
location = {Alexandria, VA, USA},
|
||
pages = {338--349},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '16},
|
||
url = {http://doi.acm.org/10.1145/2989081.2989084},
|
||
acmid = {2989084},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {Auto refresh, DRAM, Self refresh},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{aicant_21,
|
||
author = {Aichroth, Patrick and Antes, Christoph and Gembatzka, Pierre and Graf, Holger and Johnson, David and Jung, Matthias and Kämpfe, Thomas and Kleinberger, Thomas and Köllmer, Thomas and Kuhn, Thomas and Kutter, Christoph and Krüger, Jens and Loroch, Dominik and Lukashevich, Hanna and Zhang, Lei and Laleni, Nellie and Leugering, Johannes and Fernandez, Rodrigo and Mateu, Loreto and Mojumder, Shaown and Prautsch, Benjamin and Roscher, Karsten and Schneickert, Sören and Vanselow, Frank and Wallbott, Paul and Walter, Oliver and Weber, Nico},
|
||
booktitle = {Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXI)},
|
||
title = {{SEC}-{L}earn: {S}ensor {E}dge {C}loud for {F}ederated {L}earning},
|
||
groups = {MJ:1},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2021-10-07},
|
||
year = {2021},
|
||
}
|
||
|
||
@InProceedings{akegoo_07,
|
||
author = {B. Akesson and K. Goossens and M. Ringhofer},
|
||
booktitle = {2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
|
||
title = {{P}redator: {A} predictable {SDRAM} memory controller},
|
||
doi = {10.1145/1289816.1289877},
|
||
pages = {251-256},
|
||
groups = {MJ:1},
|
||
keywords = {CMOS memory circuits;DRAM chips;industrial property;integrated circuit design;microprocessor chips;multiprocessing systems;network interfaces;network-on-chip;CMOS technology;Predator;frequency 200 MHz;high-speed external memories;intellectual property component;memory access group;memory controller design;multiprocessor systems-on-chip;network interface;network-on-chip;predictable SDRAM memory controller;size 0.13 mum;Bandwidth;Clocks;Delay;Memory management;SDRAM;Switches;System-on-a-chip;Memory Controller;Predictability;SDRAM;System-on-Chip},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2007},
|
||
}
|
||
|
||
@InProceedings{akejrh_11,
|
||
author = {B. Akesson and W. Hayes Jr. and K. Goossens},
|
||
booktitle = {2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications},
|
||
title = {{A}utomatic {G}eneration of {E}fficient {P}redictable {M}emory {P}atterns},
|
||
doi = {10.1109/RTCSA.2011.33},
|
||
pages = {177-184},
|
||
volume = {1},
|
||
groups = {MJ:1},
|
||
issn = {2325-1271},
|
||
keywords = {DRAM chips;automatic test pattern generation;embedded systems;formal verification;storage management chips;DDR2-DDR3 memory;SDRAM command;SDRAM controller;automatic generation;efficient predictable memory pattern;embedded system;error-prone process;formal verification;hardware component;real-time requirement;software component;Algorithm design and analysis;Bandwidth;Clocks;Memory management;SDRAM;Time factors;Timing;SDRAM;memory controller;memory efficiency;memory patterns;pattern generation;predictability;real-time},
|
||
month = {Aug},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{akihoe_14,
|
||
author = {B. Akin and J. C. Hoe and F. Franchetti},
|
||
booktitle = {High Performance Extreme Computing Conference (HPEC), 2014 IEEE},
|
||
title = {{HAML}e{T}: {H}ardware accelerated memory layout transform within 3{D}-stacked {DRAM}},
|
||
doi = {10.1109/HPEC.2014.7040954},
|
||
pages = {1-6},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;3D stacked DRAM layers;CPU memory subsystems;GPU memory subsystems;HAMLeT system;data intensive applications;data reorganization;energy efficiency potentials;hardware accelerated memory layout transform;layout transform algorithms;logic layer;magnitude performance improvement;matrix layout transform operations;memory hierarchy;memory layout transformations;parallelism;peak system utilization;performance optimization;roundtrip data movement;Bandwidth;Hardware;Layout;Parallel processing;Random access memory;Through-silicon vias;Transforms},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{alsbha_11,
|
||
author = {Sara Alspaugh and Arka Bhattacharya and David Culler and Randy Katz},
|
||
title = {{T}he {T}ao of {S}ystems: {D}oing {N}othing {W}ell},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{amagom_17,
|
||
author = {A. Amaya and H. Gomez and E. Roa},
|
||
booktitle = {2017 IEEE International Conference on Consumer Electronics (ICCE)},
|
||
title = {{M}itigating {R}ow {H}ammer attacks based on dummy cells in {DRAM}},
|
||
doi = {10.1109/ICCE.2017.7889389},
|
||
pages = {442-443},
|
||
groups = {MJ:1},
|
||
keywords = {CMOS memory circuits;DRAM chips;security;CMOS 64×64 memory array;DRAM memories;Row Hammer attacks;coupling noise;data corruption;dummy cells;Capacitors;Couplings;Discharges (electric);Leakage currents;Random access memory;Semiconductor device modeling;Standards},
|
||
month = {Jan},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-03},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{olijun_18,
|
||
author = {Antonino, Pablo Oliveira and Jung, Matthias and Morgenstern, Andreas and Fa{\ss}nacht, Florian and Bauer, Thomas and Bachorek, Adam and Kuhn, Thomas and Nakagawa, Elisa Yumi},
|
||
booktitle = {Software Architecture},
|
||
title = {{E}nabling {C}ontinuous {S}oftware {E}ngineering for {E}mbedded {S}ystems {A}rchitectures with {V}irtual {P}rototypes},
|
||
editor = {Cuesta, Carlos E. and Garlan, David and P{\'e}rez, Jennifer},
|
||
isbn = {978-3-030-00761-4},
|
||
pages = {115--130},
|
||
publisher = {Springer International Publishing},
|
||
abstract = {Continuous software engineering aims at orchestrating engineering knowledge from various disciplines in order to deal with the rapid changes within the ecosystems of which software-based systems are part of. The literature claims that one means to ensure these prompt responses is to incorporate virtual prototypes of the system as early as possible in the development process, such that requirements and architecture decisions are verified early and continuously by means of simulations. Despite the maturity of practices for designing and assessing architectures, as well as for virtual prototyping, it is still not clear how to jointly consider the practices from these disciplines within development processes, in order to address the dynamics imposed by continuous software engineering. In this regard, we discuss in this paper how to orchestrate architecture drivers and design specification techniques with virtual prototypes, to address the demands of continuous software engineering in development processes. Our proposals are based on experiences from research and industry projects in various domains such as automotive, agriculture, construction, and medical devices.},
|
||
address = {Cham},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-24},
|
||
year = {2018},
|
||
}
|
||
|
||
@Article{app_13,
|
||
author = {Applebaum, Benny},
|
||
title = {{P}seudorandom {G}enerators with {L}ong {S}tretch and {L}ow {L}ocality from {R}andom {L}ocal {O}ne-{W}ay {F}unctions},
|
||
number = {5},
|
||
pages = {2008-2037},
|
||
volume = {42},
|
||
groups = {MJ:1},
|
||
journal = {SIAM Journal on Computing},
|
||
owner = {MJ},
|
||
timestamp = {2019-02-25},
|
||
year = {2013},
|
||
}
|
||
|
||
@Article{arakas_76,
|
||
author = {Toshiro Araki and Tadao Kasami},
|
||
title = {{S}ome decision problems related to the reachability problem for {P}etri nets},
|
||
doi = {http://dx.doi.org/10.1016/0304-3975(76)90067-0},
|
||
issn = {0304-3975},
|
||
number = {1},
|
||
pages = {85 - 104},
|
||
url = {http://www.sciencedirect.com/science/article/pii/0304397576900670},
|
||
volume = {3},
|
||
groups = {MJ:1},
|
||
journal = {Theoretical Computer Science},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-27},
|
||
year = {1976},
|
||
}
|
||
|
||
@InProceedings{auscha_12,
|
||
author = {Ausavarungnirun, Rachata and Chang, Kevin Kai-Wei and Subramanian, Lavanya and Loh, Gabriel H. and Mutlu, Onur},
|
||
booktitle = {Proceedings of the 39th Annual International Symposium on Computer Architecture},
|
||
title = {{S}taged {M}emory {S}cheduling: {A}chieving {H}igh {P}erformance and {S}calability in {H}eterogeneous {S}ystems},
|
||
isbn = {978-1-4503-1642-2},
|
||
location = {Portland, Oregon},
|
||
pages = {416--427},
|
||
publisher = {IEEE Computer Society},
|
||
series = {ISCA '12},
|
||
url = {http://dl.acm.org/citation.cfm?id=2337159.2337207},
|
||
acmid = {2337207},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{avilap_04,
|
||
author = {Avizienis, Algirdas and Laprie, Jean-Claude and Randell, Brian and Landwehr, Carl},
|
||
title = {{B}asic {C}oncepts and {T}axonomy of {D}ependable and {S}ecure {C}omputing},
|
||
doi = {10.1109/TDSC.2004.2},
|
||
issn = {1545-5971},
|
||
number = {1},
|
||
pages = {11--33},
|
||
url = {http://dx.doi.org/10.1109/TDSC.2004.2},
|
||
volume = {1},
|
||
acmid = {1026492},
|
||
address = {Los Alamitos, CA, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {January 2004},
|
||
journal = {IEEE Trans. Dependable Secur. Comput.},
|
||
keywords = {65, Index Terms- Dependability, Index Terms- Dependability, security, trust, faults, errors, failures, vulnerabilities, attacks, fault tolerance, fault removal, fault forecasting., attacks, errors, failures, fault forecasting., fault removal, fault tolerance, faults, security, trust, vulnerabilities},
|
||
month = jan,
|
||
numpages = {23},
|
||
owner = {MJ},
|
||
publisher = {IEEE Computer Society Press},
|
||
timestamp = {2018-05-03},
|
||
year = {2004},
|
||
}
|
||
|
||
@InProceedings{ayoind_10,
|
||
author = {Ayoub, Raid Zuhair and Indukuri, Krishnam Raju and Rosing, Tajana Simunic},
|
||
booktitle = {Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design},
|
||
title = {{E}nergy {E}fficient {P}roactive {T}hermal {M}anagement in {M}emory {S}ubsystem},
|
||
doi = {10.1145/1840845.1840884},
|
||
isbn = {978-1-4503-0146-6},
|
||
location = {Austin, Texas, USA},
|
||
pages = {195--200},
|
||
publisher = {ACM},
|
||
series = {ISLPED '10},
|
||
url = {http://doi.acm.org/10.1145/1840845.1840884},
|
||
acmid = {1840884},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {energy, memory subsystem, performance, proactive, thermal management},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-22},
|
||
year = {2010},
|
||
}
|
||
|
||
@Article{azapfi_16,
|
||
author = {E. Azarkhish and C. Pfister and D. Rossi and I. Loi and L. Benini},
|
||
title = {{L}ogic-{B}ase {I}nterconnect {D}esign for {N}ear {M}emory {C}omputing in the {S}mart {M}emory {C}ube},
|
||
doi = {10.1109/TVLSI.2016.2570283},
|
||
issn = {1063-8210},
|
||
number = {99},
|
||
pages = {1-14},
|
||
volume = {PP},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
|
||
keywords = {Bandwidth;Memory management;Program processors;Random access memory;Robustness;Standards;3-D integration;address scrambling;cycle accurate (CA) model;interconnect design;smart memory cube (SMC).},
|
||
owner = {MJ},
|
||
timestamp = {2016-07-20},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{baecho_14,
|
||
author = {Baek, Sanghoon and Cho, Sangyeun and Melhem, Rami},
|
||
title = {{R}efresh now and then},
|
||
number = {12},
|
||
pages = {3114--3126},
|
||
volume = {63},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
owner = {MJ},
|
||
publisher = {IEEE},
|
||
timestamp = {2015.07.10},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{baycon_11,
|
||
author = {Bayliss, Samuel and Constantinides, George A.},
|
||
booktitle = {Proceedings of the 7th International Conference on Reconfigurable Computing: Architectures, Tools and Applications},
|
||
title = {{A}pplication {S}pecific {M}emory {A}ccess, {R}euse and {R}eordering for {SDRAM}},
|
||
isbn = {978-3-642-19474-0},
|
||
location = {Belfast, UK},
|
||
pages = {41--52},
|
||
publisher = {Springer-Verlag},
|
||
series = {ARC'11},
|
||
url = {http://dl.acm.org/citation.cfm?id=1987535.1987544},
|
||
acmid = {1987544},
|
||
address = {Berlin, Heidelberg},
|
||
groups = {MJ:1},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-07},
|
||
year = {2011},
|
||
}
|
||
|
||
@Article{becmoy_16,
|
||
author = {Becker, Denis and Moy, Matthieu and Cornet, J{\'e}r{\^o}me},
|
||
title = {{Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study}},
|
||
doi = {10.3390/electronics5020022},
|
||
number = {2},
|
||
pages = {22},
|
||
url = {https://hal.archives-ouvertes.fr/hal-01321055},
|
||
volume = {5},
|
||
file = {electronics-05-00022.pdf:https\://hal.archives-ouvertes.fr/hal-01321055/file/electronics-05-00022.pdf:PDF},
|
||
groups = {MJ:1},
|
||
hal_id = {hal-01321055},
|
||
hal_version = {v1},
|
||
journal = {{Electronics}},
|
||
keywords = {hardware modeling ; parallelization ; simulation ; loose timing ; TLM ; SystemC},
|
||
month = May,
|
||
owner = {MJ},
|
||
publisher = {{MDPI}},
|
||
timestamp = {2018-09-11},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{berdia_91,
|
||
author = {B. Berthomieu and M. Diaz},
|
||
title = {{M}odeling and verification of time dependent systems using time {P}etri nets},
|
||
doi = {10.1109/32.75415},
|
||
issn = {0098-5589},
|
||
number = {3},
|
||
pages = {259-273},
|
||
volume = {17},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Software Engineering},
|
||
keywords = {Petri nets;formal specification;parallel programming;program verification;protocols;alternating bit protocol;communication systems;concurrent systems;explicit values;formal verification;specification;time Petri nets;time dependent systems;time-dependent systems;verification;Fires;Petri nets;Protocols;Reachability analysis},
|
||
month = {Mar},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-27},
|
||
year = {1991},
|
||
}
|
||
|
||
@InProceedings{bhamue_10,
|
||
author = {Bhat, B. and Mueller, F.},
|
||
booktitle = {Real-Time Systems (ECRTS), 2010 22nd Euromicro Conference on},
|
||
title = {{M}aking {DRAM} {R}efresh {P}redictable},
|
||
doi = {10.1109/ECRTS.2010.23},
|
||
pages = {145-154},
|
||
groups = {MJ:1},
|
||
issn = {1068-3070},
|
||
keywords = {DRAM chips;hardware-software codesign;program diagnostics;scheduling;task analysis;DRAM refresh predictable;caching;embedded control systems;pipelining;schedulability theory;static timing analysis;task execution times;worst-case execution times;Delay;Hardware;Real time systems;SDRAM;Software;DRAM;DRAM Refresh;Real-Time Systems;Timing Analysis;Timing Predictability;Worst-Case Execution Time},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.13},
|
||
year = {2010},
|
||
}
|
||
|
||
@Article{bhacha_16,
|
||
author = {I. Bhati and M. T. Chang and Z. Chishti and S. L. Lu and B. Jacob},
|
||
title = {{DRAM} {R}efresh {M}echanisms, {P}enalties, and {T}rade-{O}ffs},
|
||
doi = {10.1109/TC.2015.2417540},
|
||
issn = {0018-9340},
|
||
number = {1},
|
||
pages = {108-121},
|
||
volume = {65},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {DRAM chips;multiprocessing systems;performance evaluation;power aware computing;storage management;DRAM cell;DRAM chip speed;DRAM chips size;DRAM refresh mechanism;data footprint demand;data retention time;modern asynchronous DRAM;multicore processor;power dissipation;refresh operation;total memory capacity;Computer architecture;Performance evaluation;SDRAM;Temperature sensors;Timing;DRAM Refresh;Multicore processor;performance;power},
|
||
month = {Jan},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{bhacha_15,
|
||
author = {Bhati, Ishwar and Chang, Mu-Tien and Chishti, Z. and Lu, Shih-Lien and Jacob, B.},
|
||
title = {{DRAM} {R}efresh {M}echanisms, {T}rade-offs, and {P}enalties},
|
||
doi = {10.1109/TC.2015.2417540},
|
||
issn = {0018-9340},
|
||
number = {99},
|
||
pages = {1-1},
|
||
volume = {PP},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {Clocks;Computer architecture;Performance evaluation;SDRAM;Temperature sensors;Timing;DRAM Refresh;Multicore processor;performance;power},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.06},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{bhachi_13,
|
||
author = {Bhati, Ishwar and Chishti, Zeshan and Jacob, Bruce},
|
||
booktitle = {Proceedings of the 2013 International Symposium on Low Power Electronics and Design},
|
||
title = {{C}oordinated {R}efresh: {E}nergy {E}fficient {T}echniques for {DRAM} {R}efresh {S}cheduling},
|
||
isbn = {978-1-4799-1235-3},
|
||
location = {Beijing, China},
|
||
pages = {205--210},
|
||
publisher = {IEEE Press},
|
||
series = {ISLPED '13},
|
||
url = {http://dl.acm.org/citation.cfm?id=2648668.2648720},
|
||
acmid = {2648720},
|
||
address = {Piscataway, NJ, USA},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM refresh, energy efficiency, self refresh mode},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.13},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{bhachi_15,
|
||
author = {Bhati, Ishwar and Chishti, Zeshan and Lu, Shih-Lien and Jacob, Bruce},
|
||
booktitle = {Proceedings of the 42nd Annual International Symposium on Computer Architecture},
|
||
title = {{F}lexible auto-refresh: enabling scalable and energy-efficient {DRAM} refresh reductions},
|
||
organization = {ACM},
|
||
pages = {235--246},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{binbec_11,
|
||
author = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
|
||
title = {{T}he gem5 simulator},
|
||
doi = {10.1145/2024716.2024718},
|
||
issn = {0163-5964},
|
||
number = {2},
|
||
pages = {1--7},
|
||
url = {http://doi.acm.org/10.1145/2024716.2024718},
|
||
volume = {39},
|
||
acmid = {2024718},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {May 2011},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
month = aug,
|
||
numpages = {7},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2015.01.20},
|
||
year = {2011},
|
||
}
|
||
|
||
@Book{bladon_09,
|
||
author = {Black, D.C. and Donovan, J. and Bunton, B. and Keist, A.},
|
||
title = {{S}ystem{C}: {F}rom the {G}round {U}p, {S}econd {E}dition},
|
||
isbn = {9780387699578},
|
||
publisher = {Springer US},
|
||
groups = {MJ:1},
|
||
lccn = {2009933997},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.23},
|
||
year = {2009},
|
||
}
|
||
|
||
@Misc{blo_16,
|
||
author = {Bloor, Thomas},
|
||
title = {{T}he {A}utomotive {S}hift to {S}oftware-{D}efined, {C}onsolidated {C}ontroller {A}rchitectures},
|
||
url = {http://qnxauto.blogspot.de/2016/10/automotive-shifting-software-defined.html},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-03},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{bogde_14,
|
||
author = {Bogue, E.T. and {{de Souza}}, C.C. and Xavie, E.C. and Freire, A.S.},
|
||
booktitle = {Combinatorial Optimization},
|
||
title = {{A}n {I}nteger {P}rogramming {F}ormulation for the {M}aximum $k$-{S}ubset {I}ntersection {P}roblem},
|
||
pages = {87--99},
|
||
publisher = {Springer International Publishing},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-02-25},
|
||
year = {2014},
|
||
}
|
||
|
||
@Article{bojipe_12,
|
||
author = {Bojnordi, Mahdi Nazm and Ipek, Engin},
|
||
title = {{PARDIS}: {A} {P}rogrammable {M}emory {C}ontroller for the {DDR}x {I}nterfacing {S}tandards},
|
||
doi = {10.1145/2366231.2337162},
|
||
issn = {0163-5964},
|
||
number = {3},
|
||
pages = {13--24},
|
||
volume = {40},
|
||
acmid = {2337162},
|
||
address = {New York, NY, USA},
|
||
file = {bojipe_12.pdf:bojipe_12.pdf:PDF},
|
||
groups = {MJ:1},
|
||
issue_date = {June 2012},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
month = jun,
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2015.02.12},
|
||
year = {2012},
|
||
}
|
||
|
||
@Book{bos_14,
|
||
author = {Bosch, Jan},
|
||
title = {{C}ontinuous {S}oftware {E}ngineering},
|
||
isbn = {3319112821, 9783319112824},
|
||
publisher = {Springer Publishing Company, Incorporated},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2020-02-09},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{bra_09,
|
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author = {Brandner, Florian},
|
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booktitle = {Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems},
|
||
title = {{P}recise {S}imulation of {I}nterrupts {U}sing a {R}ollback {M}echanism},
|
||
isbn = {978-1-60558-696-0},
|
||
location = {Nice, France},
|
||
pages = {71--80},
|
||
publisher = {ACM},
|
||
series = {SCOPES '09},
|
||
url = {http://dl.acm.org/citation.cfm?id=1543820.1543833},
|
||
acmid = {1543833},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
numpages = {10},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-11},
|
||
year = {2009},
|
||
}
|
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|
||
@InProceedings{brieck_15,
|
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author = {O. Bringmann and W. Ecker and A. Gerstlauer and A. Goyal and D. Mueller-Gritschneder and P. Sasidharan and S. Singh},
|
||
booktitle = {2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
|
||
title = {{T}he next generation of virtual prototyping: {U}ltra-fast yet accurate simulation of {HW}/{SW} systems},
|
||
doi = {10.7873/DATE.2015.1105},
|
||
pages = {1698-1707},
|
||
groups = {MJ:1},
|
||
issn = {1530-1591},
|
||
keywords = {digital simulation;formal verification;hardware-software codesign;multiprocessing systems;operating systems (computers);software performance evaluation;system-on-chip;virtual prototyping;virtual prototyping methods;hardware-software system simulation;hardware-software coverification;hardware-software performance analysis;hardware-software architecture exploration;software functionality;design complexity;ultra-fast host-compiled software models;execution times;timing behavior;operating system;target processor;memory system;abstract TLM-based communication models;simulation speed;hardware peripheral models;industrial flow;model development;multiprocessor system-on-chip platforms;Timing;Accuracy;Computational modeling;Kernel;Hardware;Time-varying systems},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-11},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{brugri_17,
|
||
author = {Brugger, Christian and Grigorovici, Valentin and Jung, Matthias and De Schryver, Christian and Weis, Christian and Wehn, Norbert and Zweig, Katharina Anna},
|
||
title = {{A} {M}emory {C}entric {A}rchitecture of the {L}ink {A}ssessment {A}lgorithm in {L}arge {G}raphs},
|
||
doi = {10.1109/MDAT.2017.2750900},
|
||
issn = {2168-2356},
|
||
number = {1},
|
||
pages = {7-15},
|
||
volume = {35},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design \& Test},
|
||
keywords = {computer graphics;storage management;graph detection;hardware architecture;link assessment algorithm;memory centric architecture;Algorithm design and analysis;Hardware;Memory architecture;Optimization;Random access memory;Social network services;ASIC;Cluster;Graph Processing;Hardware Accelerator;Link Assessment;Network Motifs;Noisy Large-scale Data;Structural Node Similarity},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2018-02-20},
|
||
year = {2018},
|
||
}
|
||
|
||
@Article{buraus_97,
|
||
author = {Burger, Doug and Austin, Todd M.},
|
||
title = {{T}he {S}imple{S}calar tool set, version 2.0},
|
||
doi = {10.1145/268806.268810},
|
||
number = {3},
|
||
url = {http://doi.acm.org/10.1145/268806.268810},
|
||
volume = {25},
|
||
acmid = {268810},
|
||
groups = {MJ:1},
|
||
issue_date = {June 1997},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
month = jun,
|
||
numpages = {13},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {1997},
|
||
}
|
||
|
||
@InProceedings{carhei_13,
|
||
author = {Carroll, Aaron and Heiser, Gernot},
|
||
booktitle = {Proceedings of the 4th Asia-Pacific Workshop on Systems},
|
||
title = {{T}he {S}ystems {H}acker's {G}uide to the {G}alaxy {E}nergy {U}sage in a {M}odern {S}martphone},
|
||
doi = {10.1145/2500727.2500734},
|
||
isbn = {978-1-4503-2316-1},
|
||
location = {Singapore, Singapore},
|
||
pages = {5:1--5:7},
|
||
publisher = {ACM},
|
||
series = {APSys '13},
|
||
url = {http://doi.acm.org/10.1145/2500727.2500734},
|
||
acmid = {2500734},
|
||
address = {New York, NY, USA},
|
||
articleno = {5},
|
||
groups = {MJ:1},
|
||
numpages = {7},
|
||
owner = {MJ},
|
||
timestamp = {2016-05-09},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{carhsi_99,
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author = {Carter, John and Hsieh, Wilson and Stoller, Leigh and Swanson, Mark. and Zhang, Lixin and Brunvand, Erik. and Davis, Al. and Kuo, Chen-Chi and Kuramkote, Ravindra and Parker, Michael and Schaelicke, Lambert and Tateyama, Terry},
|
||
booktitle = {High-Performance Computer Architecture, 1999. Proceedings. Fifth International Symposium On},
|
||
title = {{I}mpulse: building a smarter memory controller},
|
||
doi = {10.1109/HPCA.1999.744334},
|
||
pages = {70-79},
|
||
groups = {MJ:1},
|
||
keywords = {cache storage;conjugate gradient methods;database management systems;memory architecture;multimedia computing;DRAM access latency hiding;Impulse memory system architecture;NAS conjugate gradient benchmark;application-specific optimization;bus design;cache design;configurable physical address remapping;data access;data caching;database programs;memory controller;memory-bound program performance;multimedia programs;performance;prefetching;processor design;scientific applications;Bandwidth;Cities and towns;Computer science;Databases;Delay;Electronic switching systems;Microprocessors;Prefetching;Random access memory;Sparse matrices},
|
||
month = {Jan},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {1999},
|
||
}
|
||
|
||
@Article{cha_14,
|
||
author = {Chandrasekar, Karthik},
|
||
title = {{H}igh-level power estimation and optimization of {DRAM}s},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
publisher = {Technische Universiteit Delft},
|
||
timestamp = {2020-04-15},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{chaake_12,
|
||
author = {Chandrasekar, Karthik and Akesson, Benny and Goossens, Kees},
|
||
booktitle = {Proceedings of the 49th Annual Design Automation Conference},
|
||
title = {{R}un-time {P}ower-down {S}trategies for {R}eal-time {SDRAM} {M}emory {C}ontrollers},
|
||
doi = {10.1145/2228360.2228538},
|
||
isbn = {978-1-4503-1199-1},
|
||
location = {San Francisco, California},
|
||
pages = {988--993},
|
||
publisher = {ACM},
|
||
series = {DAC '12},
|
||
url = {http://doi.acm.org/10.1145/2228360.2228538},
|
||
acmid = {2228538},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {SDRAM, memory controller, power-down, real-time},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-22},
|
||
year = {2012},
|
||
}
|
||
|
||
@InProceedings{chaake_11,
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author = {Chandrasekar, Karthik and Akesson, Benny and Goossens, Kees},
|
||
booktitle = {{proc. DSD'11}},
|
||
title = {{Improved Power Modeling of DDR SDRAMs}},
|
||
doi = {10.1109/DSD.2011.17},
|
||
url = {http://dx.doi.org/10.1109/DSD.2011.17},
|
||
acmid = {2056663},
|
||
groups = {MJ:1},
|
||
keywords = {DDR SDRAMs; Power Modeling; Power Estimation; State Transitions; Power-Down; Self-Refresh; Bank-Interleaving; Open-page; Close-page; SDRAM Command Trace},
|
||
numpages = {10},
|
||
owner = {MJ},
|
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timestamp = {2015.01.20},
|
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year = {2011},
|
||
}
|
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|
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@InProceedings{chagoo_14,
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author = {Chandrasekar, Karthik and Goossens, Sven and Weis, Christian and Koedam, Martijn and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
|
||
booktitle = {Proceedings of the Conference on Design, Automation \& Test in Europe},
|
||
title = {{E}xploiting {E}xpendable {P}rocess-margins in {DRAM}s for {R}un-time {P}erformance {O}ptimization},
|
||
isbn = {978-3-9815370-2-4},
|
||
location = {Dresden, Germany},
|
||
pages = {173:1--173:6},
|
||
publisher = {European Design and Automation Association},
|
||
series = {DATE '14},
|
||
url = {http://dl.acm.org/citation.cfm?id=2616606.2616820},
|
||
acmid = {2616820},
|
||
address = {3001 Leuven, Belgium, Belgium},
|
||
articleno = {173},
|
||
groups = {MJ:1},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-14},
|
||
year = {2014},
|
||
}
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||
|
||
@InProceedings{chawei_13,
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author = {K. Chandrasekar and C. Weis and B. Akesson and N. Wehn and K.G.W. Goossens},
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booktitle = {Proc. 50th Design Automation Conference},
|
||
title = {{T}owards {V}ariation-{A}ware {S}ystem-{L}evel {P}ower {E}stimation of {DRAM}s: {A}n {E}mpirical {A}pproach},
|
||
address = {Austin, USA},
|
||
groups = {MJ:1},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2016-02-19},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{chawei_13a,
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||
author = {Chandrasekar, Karthik and Weis, Christian and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
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||
booktitle = {2013 Design, Automation Test in Europe Conference Exhibition (DATE)},
|
||
title = {{S}ystem and circuit level power modeling of energy-efficient 3{D}-stacked wide {I}/{O} {DRAM}s},
|
||
pages = {236-241},
|
||
groups = {MJ:1},
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||
owner = {MJ},
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||
timestamp = {2020-04-15},
|
||
year = {2013},
|
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}
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@InProceedings{chalee_14,
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author = {Chang, Kevin Kai-Wei and Lee, Donghyuk and Chishti, Zeshan and Alameldeen, Alaa R and Wilkerson, Chris and Kim, Yoongu and Mutlu, Onur},
|
||
booktitle = {High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on},
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||
title = {{I}mproving {DRAM} performance by parallelizing refreshes with accesses},
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||
organization = {IEEE},
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||
pages = {356--367},
|
||
groups = {MJ:1},
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||
owner = {MJ},
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timestamp = {2015.07.10},
|
||
year = {2014},
|
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}
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|
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@Article{chabal_12,
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author = {Chatterjee, Niladrish and Balasubramonian, Rajeev and Shevgoor, Manjunath and Pugsley, Seth and Udipi, Aniruddha and Shafiee, Ali and Sudan, Kshitij amd Awasthi, Manu and Chishti, Zeshan},
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title = {{USIMM}: the {U}tah {SI}mulated {M}emory {M}odule, {A} {S}imulation {I}nfrastructure for the {JWAC} {M}emory {S}cheduling {C}hampionship},
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groups = {MJ:1},
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journal = {Utah and Intel Corp.},
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month = {February},
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owner = {MJ},
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timestamp = {2015.02.17},
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year = {2012},
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}
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@InProceedings{chepra_15,
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author = {Ren Chen and Viktor K. Prasanna},
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booktitle = {Applied Reconfigurable Computing - 11th International Symposium, {ARC} 2015, Bochum, Germany, April 13-17, 2015, Proceedings},
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title = {{DRAM} {R}ow {A}ctivation {E}nergy {O}ptimization for {S}tride {M}emory {A}ccess on {FPGA}-{B}ased {S}ystems},
|
||
doi = {10.1007/978-3-319-16214-0},
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||
pages = {349--356},
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url = {http://dx.doi.org/10.1007/978-3-319-16214-0},
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||
bibsource = {dblp computer science bibliography, http://dblp.org},
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||
groups = {MJ:1},
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owner = {MJ},
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timestamp = {2016-04-11},
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||
year = {2015},
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||
}
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@InBook{cheede_14,
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author = {Cheng, Betty H. C. and Eder, Kerstin I. and Gogolla, Martin and Grunske, Lars and Litoiu, Marin and M{\"u}ller, Hausi A. and Pelliccione, Patrizio and Perini, Anna and Qureshi, Nauman A. and Rumpe, Bernhard and Schneider, Daniel and Trollmann, Frank and Villegas, Norha M.},
|
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booktitle = {Models@run.time: Foundations, Applications, and Roadmaps},
|
||
title = {{U}sing {M}odels at {R}untime to {A}ddress {A}ssurance for {S}elf-{A}daptive {S}ystems},
|
||
doi = {10.1007/978-3-319-08915-7_4},
|
||
editor = {Bencomo, Nelly and France, Robert and Cheng, Betty H. C. and A{\ss}mann, Uwe},
|
||
isbn = {978-3-319-08915-7},
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||
pages = {101--136},
|
||
publisher = {Springer International Publishing},
|
||
url = {https://doi.org/10.1007/978-3-319-08915-7_4},
|
||
abstract = {A self-adaptive software system modifies its behavior at runtime in response to changes within the system or in its execution environment. The fulfillment of the system requirements needs to be guaranteed even in the presence of adverse conditions and adaptations. Thus, a key challenge for self-adaptive software systems is assurance. Traditionally, confidence in the correctness of a system is gained through a variety of activities and processes performed at development time, such as design analysis and testing. In the presence of self-adaptation, however, some of the assurance tasks may need to be performed at runtime. This need calls for the development of techniques that enable continuous assurance throughout the software life cycle. Fundamental to the development of runtime assurance techniques is research into the use of models at runtime (M@RT). This chapter explores the state of the art for using M@RT to address the assurance of self-adaptive software systems. It defines what information can be captured by M@RT, specifically for the purpose of assurance, and puts this definition into the context of existing work. We then outline key research challenges for assurance at runtime and characterize assurance methods. The chapter concludes with an exploration of selected application areas where M@RT could provide significant benefits beyond existing assurance techniques for adaptive systems.},
|
||
address = {Cham},
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||
groups = {MJ:1},
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||
owner = {MJ},
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||
timestamp = {2019-01-02},
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||
year = {2014},
|
||
}
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||
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@Article{chldin_18,
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author = {Chlamt\'{a}\v{c}, Eden and Dinitz, Michael and Konrad, Christian and Kortsarz, Guy and Rabanca, George},
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||
title = {{T}he {D}ensest $k$-{S}ubhypergraph {P}roblem},
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number = {2},
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pages = {1458--1477},
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volume = {32},
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groups = {MJ:1},
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journal = {SIAM Journal on Discrete Math},
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owner = {MJ},
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timestamp = {2019-02-20},
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year = {2018},
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||
}
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||
|
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@Conference{chldin_16,
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author = {Chlamt\'{a}\v{c}, Eden and Dinitz, Michael and Konrad, Christian and Kortsarz, Guy and Rabanca, George},
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||
booktitle = {Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques (APPROX/RANDOM 2016)},
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||
title = {{T}he {D}ensest $k$-{S}ubhypergraph {P}roblem},
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pages = {6:1--6:19},
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groups = {MJ:1},
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owner = {MJ},
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timestamp = {2019-02-25},
|
||
year = {2016},
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||
}
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||
|
||
@InProceedings{chldin_17,
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author = {Chlamt\'{a}\v{c}, Eden and Dinitz, Michael and Makarychev, Yury},
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booktitle = {SODA '17 Proceedings of the Twenty-Eighth Annual ACM-SIAM Symposium on Discrete Algorithms},
|
||
title = {{M}inimizing the {U}nion: {T}ight {A}pproximations for {S}mall {S}et {B}ipartite {V}ertex {E}xpansion},
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pages = {881-899},
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groups = {MJ:1},
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owner = {MJ},
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timestamp = {2019-02-25},
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year = {2017},
|
||
}
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@Article{choche_15,
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author = {Hyungmin Cho and Chen{-}Yong Cher and Thomas Shepherd and Subhasish Mitra},
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||
title = {{U}nderstanding {S}oft {E}rrors in {U}ncore {C}omponents},
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url = {http://arxiv.org/abs/1504.01381},
|
||
volume = {abs/1504.01381},
|
||
bibsource = {dblp computer science bibliography, http://dblp.org},
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||
biburl = {http://dblp.uni-trier.de/rec/bib/journals/corr/ChoCSM15},
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||
groups = {MJ:1},
|
||
journal = {CoRR},
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owner = {MJ},
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timestamp = {Sat, 02 May 2015 17:50:32 +0200},
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year = {2015},
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}
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@InProceedings{ciojah_17,
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author = {E. Cioroaica and J. Jahić and T. Kuhn and C. Peper and D. Uecker and C. Dropmann and P. Munk and A. Rakshith and E. Thaden},
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||
booktitle = {2017 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)},
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||
title = {{A}ccelerated {S}imulated {F}ault {I}njection {T}esting},
|
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doi = {10.1109/ISSREW.2017.35},
|
||
pages = {228-233},
|
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groups = {MJ:1},
|
||
keywords = {embedded systems;middleware;operating systems (computers);program testing;safety-critical software;software fault tolerance;software behavior;platform software;embedded systems;operating systems;middleware platforms;accelerated simulated fault injection testing;fault injection testing approaches;critical software;software complexity;execution environments reliability;software components testing;Testing;Safety;Operating systems;Hardware;Computational modeling;Registers;simulated fault injection technique;accelerated fault injection;gem5;FERAL},
|
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month = {Oct},
|
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owner = {MJ},
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timestamp = {2018-12-18},
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year = {2017},
|
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}
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|
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@Article{clipop_11,
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author = {Clifford, R. and Popa, A.},
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title = {{M}aximum {S}ubset {I}ntersection},
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number = {7},
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pages = {323--325},
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volume = {111},
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groups = {MJ:1},
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journal = {Information Processing Letters},
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owner = {MJ},
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timestamp = {2019-02-25},
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year = {2011},
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}
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@InProceedings{cooros_12,
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author = {E. Cooper-Balis and P. Rosenfeld and B. Jacob},
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booktitle = {Computer Architecture (ISCA), 2012 39th Annual International Symposium on},
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||
title = {{B}uffer-on-board memory systems},
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||
doi = {10.1109/ISCA.2012.6237034},
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||
pages = {392-403},
|
||
groups = {MJ:1},
|
||
issn = {1063-6897},
|
||
keywords = {DRAM chips;buffer storage;logic circuits;memory architecture;queueing theory;system buses;CPU;DRAM;buffer-on-board memory systems;bus organization;capacity limitations;clock rates;commodity memory architecture;full system simulations;hardware-verified simulation suite;implementation costs;intermediate logic;mapping schemes;performance limitations;queue storage;signal integrity;simulated configurations;Bandwidth;Clocks;Protocols;SDRAM;Standards;Timing},
|
||
month = {June},
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owner = {MJ},
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timestamp = {2016-08-19},
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year = {2012},
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}
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@InProceedings{cuimck_14,
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author = {Cui, Zehan and McKee, Sally A. and Zha, Zhongbin and Bao, Yungang and Chen, Mingyu},
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booktitle = {Proceedings of the 28th ACM International Conference on Supercomputing},
|
||
title = {{DT}ail: {A} {F}lexible {A}pproach to {DRAM} {R}efresh {M}anagement},
|
||
doi = {10.1145/2597652.2597663},
|
||
isbn = {978-1-4503-2642-1},
|
||
location = {Munich, Germany},
|
||
pages = {43--52},
|
||
publisher = {ACM},
|
||
series = {ICS '14},
|
||
url = {http://doi.acm.org/10.1145/2597652.2597663},
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acmid = {2597663},
|
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address = {New York, NY, USA},
|
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groups = {MJ:1},
|
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keywords = {dram refresh, energy saving, refresh management},
|
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numpages = {10},
|
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owner = {MJ},
|
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timestamp = {2015.07.10},
|
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year = {2014},
|
||
}
|
||
|
||
@InProceedings{cupjac_01,
|
||
author = {V. Cuppu and B. Jacob},
|
||
booktitle = {Proceedings 28th Annual International Symposium on Computer Architecture},
|
||
title = {{C}oncurrency, latency, or system overhead: {W}hich has the largest impact on uniprocessor {DRAM}-system performance?},
|
||
doi = {10.1109/ISCA.2001.937433},
|
||
pages = {62-71},
|
||
groups = {MJ:1},
|
||
issn = {1063-6897},
|
||
keywords = {parallel architectures;performance evaluation;processor scheduling;protocols;timing;SPEC CPU 2000 integer suite;application execution times;burst sizes;concurrency;fixed CPU architecture;fixed DRAM timing specification;ganged direct rambles organization;high-performance DRAM systems;latency;memory-controller page protocol;organizations;queue sizes;system overhead;uniprocessor DRAM-system performance;Bandwidth;Concurrent computing;Delay;Dynamic scheduling;Performance loss;Protocols;Random access memory;Read-write memory;Scheduling algorithm;Timing},
|
||
owner = {MJ},
|
||
timestamp = {2017-04-06},
|
||
year = {2001},
|
||
}
|
||
|
||
@InProceedings{damgri_08,
|
||
author = {M. Damm and C. Grimm and J. Haas and A. Herrholz and W. Nebel},
|
||
booktitle = {2008 Forum on Specification, Verification and Design Languages},
|
||
title = {{C}onnecting {S}ystem{C}-{AMS} models with {OSCI} {TLM} 2.0 models using temporal decoupling},
|
||
doi = {10.1109/FDL.2008.4641416},
|
||
pages = {25-30},
|
||
groups = {MJ:1},
|
||
keywords = {electronic engineering computing;embedded systems;simulation languages;SystemC-AMS models;OSCI TLM 2.0 models;temporal decoupling;system modelling language;embedded systems;computation models;Converters;Time domain analysis;Time varying systems;Computational modeling;Digital signal processing;Kernel;Synchronization},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-11},
|
||
year = {2008},
|
||
}
|
||
|
||
@Misc{davgm_18,
|
||
author = {Davies, Alex},
|
||
title = {{GM} {W}ill {L}aunch {R}obocars {W}ithout {S}teering {W}heels {N}ext {Y}ear},
|
||
howpublished = {https://www.wired.com/story/gm-cruise-self-driving-car-launch-2019/},
|
||
groups = {MJ:1},
|
||
month = {January},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-01},
|
||
year = {2018},
|
||
}
|
||
|
||
@Book{deschutter_14,
|
||
author = {De Schutter, Tom},
|
||
title = {{B}etter {S}oftware. {F}aster!: {B}est {P}ractices in {V}irtual {P}rototyping},
|
||
isbn = {1617300136, 9781617300134},
|
||
publisher = {Synopsys Press},
|
||
address = {USA},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-04-05},
|
||
year = {2014},
|
||
}
|
||
|
||
@Article{delcan_01,
|
||
author = {Delaluz, Victor and Kandemir, Mahmut and Vijaykrishnan, N. and Sivasubramaniam, Anand and Irwin, Mary Jane},
|
||
title = {{H}ardware and {S}oftware {T}echniques for {C}ontrolling {DRAM} {P}ower {M}odes},
|
||
doi = {10.1109/12.966492},
|
||
issn = {0018-9340},
|
||
number = {11},
|
||
pages = {1154--1173},
|
||
url = {http://dx.doi.org/10.1109/12.966492},
|
||
volume = {50},
|
||
acmid = {507061},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {November 2001},
|
||
journal = {IEEE Trans. Comput.},
|
||
keywords = {Memory architecture, low power, low power compilation, software-directed energy management.},
|
||
month = nov,
|
||
numpages = {20},
|
||
owner = {MJ},
|
||
publisher = {IEEE Computer Society},
|
||
timestamp = {2016-12-13},
|
||
year = {2001},
|
||
}
|
||
|
||
@InProceedings{desdra_15,
|
||
author = {Deshpande, Aditya M. and Draper, Jeffrey T. and Rigdon, J. Brian and Barrett, Richard F.},
|
||
booktitle = {Proceedings of the 5th Workshop on Irregular Applications: Architectures and Algorithms},
|
||
title = {{P}ath{F}inder: {A} {S}ignature-search {M}iniapp and {I}ts {R}untime {C}haracteristics},
|
||
doi = {10.1145/2833179.2833190},
|
||
isbn = {978-1-4503-4001-4},
|
||
location = {Austin, Texas},
|
||
pages = {9:1--9:4},
|
||
publisher = {ACM},
|
||
series = {IA3 '15},
|
||
url = {http://doi.acm.org/10.1145/2833179.2833190},
|
||
acmid = {2833190},
|
||
address = {New York, NY, USA},
|
||
articleno = {9},
|
||
groups = {MJ:1},
|
||
keywords = {HPC application, binary signature search, graph application, performance characterization},
|
||
numpages = {4},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{donher_16,
|
||
author = {Dongarra, Jack and Heroux, Michael A. and Luszczek, Piotr},
|
||
title = {{A} new metric for ranking high-performance computing systems},
|
||
doi = {10.1093/nsr/nwv084},
|
||
eprint = {/oup/backfile/content_public/journal/nsr/3/1/10.1093_nsr_nwv084/2/nwv084.pdf},
|
||
number = {1},
|
||
pages = {30},
|
||
url = {+ http://dx.doi.org/10.1093/nsr/nwv084},
|
||
volume = {3},
|
||
groups = {MJ:1},
|
||
journal = {National Science Review},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{dri_10,
|
||
author = {Driskill-Smith, A},
|
||
title = {{STT}-{RAM}: {T}he {C}oming {R}evolution in {M}emory},
|
||
pages = {26-32},
|
||
volume = {35},
|
||
groups = {MJ:1},
|
||
journal = {Future Fab Intl.},
|
||
month = {November},
|
||
owner = {MJ},
|
||
timestamp = {2016-08-16},
|
||
year = {2010},
|
||
}
|
||
|
||
@InProceedings{drotha_18,
|
||
author = {Dropmann, Christoph and Thaden, Eike and Trapp, Mario and Uecker, Denis and Amarnath, Rakshith and da Silva, Leandro Avila and Munk, Peter and Schweizer, Markus and Jung, Matthias and Adler, Rasmus},
|
||
booktitle = {Computer Safety, Reliability, and Security},
|
||
title = {{A} {M}odel-{B}ased {S}afety {A}nalysis of {D}ependencies {A}cross {A}bstraction {L}ayers},
|
||
doi = {10.1007/978-3-319-99130-6_6},
|
||
editor = {Gallina, Barbara and Skavhaug, Amund and Bitsch, Friedemann},
|
||
isbn = {978-3-319-99130-6},
|
||
pages = {73--87},
|
||
publisher = {Springer International Publishing},
|
||
abstract = {Identifying and mitigating possible failure propagation from one safety-critical application to another through common infrastructural components is a challenging task. Examples of such dependencies across software-stack layers (e.g., between application and middleware layer) are common causes and failure propagation scenarios in which a failure of one software component propagates to another software component through shared services and/or common computational resources. To account for this, safety standards demand freedom from interference in order to control failure propagation between mixed-critical software components. Safety analysis is typically focused on one abstraction layer, while robustness tests try to find failure propagation paths across abstraction layers. To this end, this paper presents a model-based failure propagation analysis combining failure propagation within and across abstraction layers. A classification of dependencies in combination with fault trees is used to perform a model-based dependency analysis. In addition, a novel modeling technique for integrating failure propagation aspects resulting from shared services and resources is presented. The analysis was used to carry out an early safety assessment of a real-world automotive redundancy mechanism within an integrated architecture. The results show that the method improved reusability and modularity, and made it easier to estimate failure propagation issues, including possible violations of freedom from interference within an integrated system.},
|
||
address = {Cham},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-02},
|
||
year = {2018},
|
||
}
|
||
|
||
@InProceedings{ebrmif_11,
|
||
author = {Ebrahimi, Eiman and Miftakhutdinov, Rustam and Fallin, Chris and Lee, Chang Joo and Joao, Jos{\'e} A. and Mutlu, Onur and Patt, Yale N.},
|
||
booktitle = {Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture},
|
||
title = {{P}arallel {A}pplication {M}emory {S}cheduling},
|
||
doi = {10.1145/2155620.2155663},
|
||
isbn = {978-1-4503-1053-6},
|
||
location = {Porto Alegre, Brazil},
|
||
pages = {362--373},
|
||
publisher = {ACM},
|
||
series = {MICRO-44},
|
||
url = {http://doi.acm.org/10.1145/2155620.2155663},
|
||
acmid = {2155663},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {CMP, memory controller, memory interference, multi-core, parallel applications, shared resources},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-02},
|
||
year = {2011},
|
||
}
|
||
|
||
@Article{eccern_17,
|
||
author = {Ecco, Leonardo and Ernst, Rolf},
|
||
title = {{T}ackling the {B}us {T}urnaround {O}verhead in {R}eal-{T}ime {SDRAM} {C}ontrollers},
|
||
doi = {10.1109/TC.2017.2714672},
|
||
issn = {0018-9340},
|
||
number = {11},
|
||
pages = {1961-1974},
|
||
volume = {66},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {DRAM chips;cache storage;real-time systems;SDRAM controller;bank privatization;complex two-stage access protocol;data bus turnaround overhead;explicitly managed caching;internal level;many-core platforms;open-rowpolicy;predictability challenge;read and write operations;real-time SDRAM controllers;real-time guarantees;single data bus;synchronous dynamic random access memories;DRA chips;Decoding;Memory management;Power demand;Random access memory;Real-time systems;SDRAM;Transmission line matrix methods;Real-time and embedded systems;dynamic random access memory (DRAM);memory control and access},
|
||
month = {Nov},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-03},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{eccern_17a,
|
||
author = {L. Ecco and R. Ernst},
|
||
booktitle = {Design, Automation Test in Europe Conference Exhibition (DATE), 2017},
|
||
title = {{A}rchitecting high-speed command schedulers for open-row real-time {SDRAM} controllers},
|
||
doi = {10.23919/DATE.2017.7927063},
|
||
pages = {626-629},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;parallel architectures;real-time systems;hardware overhead;multistage architecture;open-row real-time SDRAM controllers;open-row real-time command scheduler;parallel architecture;Computer architecture;Hardware;Real-time systems;Registers;SDRAM;Switches;Timing},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{eccsai_15,
|
||
author = {L. Ecco and S. Saidi and A. Kostrzewa and R. Ernst},
|
||
booktitle = {10th IEEE International Symposium on Industrial Embedded Systems (SIES)},
|
||
title = {{R}eal-time {DRAM} throughput guarantees for latency sensitive mixed {Q}o{S} {MPS}o{C}s},
|
||
doi = {10.1109/SIES.2015.7185038},
|
||
pages = {1-10},
|
||
groups = {MJ:1},
|
||
issn = {2150-3109},
|
||
keywords = {DRAM chips;quality of service;real-time systems;system-on-chip;BE requestors;GT requestors;formal timing analysis;latency reduction;latency-sensitive mixed QoS MPSoC;low-latency BE service;low-latency best-effort service;real-time DRAM throughput guarantees;real-time memory controllers;tight guarantees;traffic classes;DRAM chips;Delays;Privatization;Real-time systems;Throughput},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{ecctob_14,
|
||
author = {Leonardo Ecco and Sebastian Tobuschat and Selma Saidi and Rolf Ernst},
|
||
booktitle = {{RTCSA}},
|
||
title = {{A} mixed critical memory controller using bank privatization and fixed priority scheduling},
|
||
pages = {1--10},
|
||
publisher = {{IEEE} Computer Society},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-18},
|
||
year = {2014},
|
||
}
|
||
|
||
@Misc{eco_15,
|
||
author = {The Economist},
|
||
title = {{T}he end of {M}oore's law},
|
||
howpublished = {\url{http://www.economist.com/blogs/economist-explains/2015/04/economist-explains-17}},
|
||
groups = {MJ:1},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2016.02.07},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{eng_17,
|
||
author = {Engblom, Jakob},
|
||
title = {{V}irtual {P}latform {C}heckpointing ({S}ystem{C} {E}volution {D}ay 2017)},
|
||
howpublished = {https://software.intel.com/en-us/blogs/2017/09/12/virtual-platform-checkpointing-systemc-evolution-day-2017},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-09},
|
||
year = {2017},
|
||
}
|
||
|
||
@Electronic{eve_17,
|
||
author = {Sven Evers},
|
||
title = {{C}inco-{P}lay: {M}emory {IS} that {C}ritical to {A}utonomous {D}riving},
|
||
url = {https://www.micron.com/about/blogs/2017/october/cinco-play-memory-is-that-critical-to-autonomous-driving},
|
||
groups = {MJ:1},
|
||
month = {November},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-17},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{fanell_01,
|
||
author = {Fan, Xiaobo and Ellis, Carla and Lebeck, Alvin},
|
||
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics and Design},
|
||
title = {{M}emory {C}ontroller {P}olicies for {DRAM} {P}ower {M}anagement},
|
||
doi = {10.1145/383082.383118},
|
||
isbn = {1-58113-371-5},
|
||
location = {Huntington Beach, California, USA},
|
||
pages = {129--134},
|
||
publisher = {ACM},
|
||
series = {ISLPED '01},
|
||
url = {http://doi.acm.org/10.1145/383082.383118},
|
||
acmid = {383118},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-13},
|
||
year = {2001},
|
||
}
|
||
|
||
@InProceedings{fanell_03,
|
||
author = {Fan, Xiaobo and Ellis, Carla S. and Lebeck, Alvin R.},
|
||
booktitle = {Proceedings of the 2Nd International Conference on Power-aware Computer Systems},
|
||
title = {{M}odeling of {DRAM} {P}ower {C}ontrol {P}olicies {U}sing {D}eterministic and {S}tochastic {P}etri {N}ets},
|
||
isbn = {3-540-01028-9},
|
||
location = {Cambridge, MA, USA},
|
||
pages = {130--140},
|
||
publisher = {Springer-Verlag},
|
||
series = {PACS'02},
|
||
url = {http://dl.acm.org/citation.cfm?id=1766991.1767003},
|
||
acmid = {1767003},
|
||
address = {Berlin, Heidelberg},
|
||
groups = {MJ:1},
|
||
numpages = {11},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-26},
|
||
year = {2003},
|
||
}
|
||
|
||
@InProceedings{farhem_14,
|
||
author = {Farahini, N. and Hemani, A. and Lansner, A. and Clermidy, F. and Svensson, C.},
|
||
booktitle = {Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific},
|
||
title = {{A} scalable custom simulation machine for the {B}ayesian {C}onfidence {P}ropagation {N}eural {N}etwork model of the brain},
|
||
doi = {10.1109/ASPDAC.2014.6742953},
|
||
pages = {578-585},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;belief networks;biomedical electronics;brain;mainframes;medical computing;neural chips;neurophysiology;parallel machines;3D stacked DRAM memories;BCPNN model;Bayesian confidence propagation neural network model;custom designed logic chip;eBrain;general purpose supercomputers;human brain;hybrid memory cube;multichip custom digital supercomputer;scalable custom simulation machine;synaptic weights;technology node;Aggregates;Bandwidth;Brain modeling;Computational modeling;Delays;Random access memory;Three-dimensional displays},
|
||
month = {Jan},
|
||
owner = {MJ},
|
||
timestamp = {2015.10.30},
|
||
year = {2014},
|
||
}
|
||
|
||
@Misc{finnis_17,
|
||
author = {Fingas, Jon},
|
||
title = {{N}issan's {R}ogue is its first {US} car with semi-autonomous driving},
|
||
howpublished = {https://www.engadget.com/2017/10/19/nissans-rogue-is-its-first-us-car-with-semi-autonomous-driving/},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-01},
|
||
year = {2017},
|
||
}
|
||
|
||
@Article{fitsto_17,
|
||
author = {Brian Fitzgerald and Klaas-Jan Stol},
|
||
title = {{C}ontinuous software engineering: {A} roadmap and agenda},
|
||
doi = {https://doi.org/10.1016/j.jss.2015.06.063},
|
||
issn = {0164-1212},
|
||
pages = {176 - 189},
|
||
url = {http://www.sciencedirect.com/science/article/pii/S0164121215001430},
|
||
volume = {123},
|
||
groups = {MJ:1},
|
||
journal = {Journal of Systems and Software},
|
||
keywords = {Continuous software engineering, Lean software development, DevOps},
|
||
owner = {MJ},
|
||
timestamp = {2020-02-09},
|
||
year = {2017},
|
||
}
|
||
|
||
@Book{fla_11a,
|
||
author = {Flanagan, D.},
|
||
title = {{J}ava{S}cript: {T}he {D}efinitive {G}uide},
|
||
isbn = {9780596805524},
|
||
publisher = {O'Reilly Media, Incorporated},
|
||
series = {Definitive Guide Series},
|
||
url = {https://books.google.de/books?id=4RChxt67lvwC},
|
||
groups = {MJ:1},
|
||
lccn = {2011377767},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-15},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{ghasud_20,
|
||
author = {Ghaffar, Muhammad Mohsin and Sudarshan, Chirag and Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {International Symposium on Memory Systems (MEMSYS 2020)},
|
||
title = {{A}n {I}n-{DRAM} {A}rchitecture for {Q}uantized {CNN}s using {F}ast {W}inograd {C}onvolutions},
|
||
publisher = {ACM/IEEE},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2020-09-19},
|
||
year = {2020},
|
||
}
|
||
|
||
@InProceedings{ghagar_15,
|
||
author = {Ghasempour, Mohsen and Jaleel, Aamer and Garside, Jim D. and Luj\'{a}n, Mikel},
|
||
booktitle = {Proceedings of the Second International Symposium on Memory Systems},
|
||
title = {{DR}e{AM}: {D}ynamic {R}e-arrangement of {A}ddress {M}apping to {I}mprove the {P}erformance of {DRAM}s},
|
||
doi = {10.1145/2989081.2989102},
|
||
isbn = {978-1-4503-4305-3},
|
||
location = {Alexandria, VA, USA},
|
||
pages = {362--373},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '16},
|
||
url = {http://doi.acm.org/10.1145/2989081.2989102},
|
||
acmid = {2989102},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {Address Mapping, DRAM, Memory Systems},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-19},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{gholee_07,
|
||
author = {Ghosh, M. and Lee, H.-H.S.},
|
||
booktitle = {Microarchitecture, 2007. MICRO 2007. 40th Annual IEEE/ACM International Symposium on},
|
||
title = {{S}mart {R}efresh: {A}n {E}nhanced {M}emory {C}ontroller {D}esign for {R}educing {E}nergy in {C}onventional and 3{D} {D}ie-{S}tacked {DRAM}s},
|
||
doi = {10.1109/MICRO.2007.13},
|
||
pages = {134-145},
|
||
groups = {MJ:1},
|
||
issn = {1072-4451},
|
||
keywords = {DRAM chips;integrated circuit design;3D die-stacked DRAMs;Biobench benchmark programs;SPECint2000;SPLASH-2;data correctness maintenance;energy reduction;enhanced memory controller design;periodic refreshing;power reduction;time-out counter;Bandwidth;Counting circuits;Data engineering;Design engineering;Microarchitecture;Packaging;Power engineering and energy;Process design;Random access memory;Temperature},
|
||
month = {Dec},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2007},
|
||
}
|
||
|
||
@Book{girval_13,
|
||
author = {Girault, Claude and Valk, R{\"u}diger},
|
||
title = {{P}etri nets for systems engineering: a guide to modeling, verification, and applications},
|
||
publisher = {Springer Science \& Business Media},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-27},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{girmor_13,
|
||
author = {S. Girbal and M. Moretó and A. Grasset and J. Abella and E. Quiñones and F. J. Cazorla and S. Yehia},
|
||
booktitle = {2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)},
|
||
title = {{O}n the convergence of mainstream and mission-critical markets},
|
||
doi = {10.1145/2463209.2488962},
|
||
pages = {1-10},
|
||
groups = {MJ:1},
|
||
issn = {0738-100X},
|
||
keywords = {consumer behaviour;consumer electronics;avionic;computing industry;consumer electronics market;high performance computing market;mission critical functionality;mission critical market;mobile market;Convergence;Mission critical systems;Mobile communication;Multicore processing;Program processors;Quality of service;Timing;High Performance;Mission Critical;Quality of Service},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-17},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{glanit_15,
|
||
author = {G. Glaser and G. Nitschey and E. Hennig},
|
||
booktitle = {2015 Forum on Specification and Design Languages (FDL)},
|
||
title = {{T}emporal decoupling with error-bounded predictive quantum control},
|
||
pages = {1-6},
|
||
groups = {MJ:1},
|
||
issn = {1636-9874},
|
||
keywords = {digital control;discrete systems;embedded systems;intelligent sensors;mixed analogue-digital integrated circuits;predictive control;virtual prototyping;temporal decoupling;error-bounded predictive quantum control;integrated mixed-signal smart-sensor systems;virtual prototyping;analog frontend circuitry;digital controller hardware;embedded real-time software;SystemC-TLM 2.0;digital components;firmware code execution;clock cycle accuracy;time quantum boundaries;optimal time quanta;blackbox sources;a-priori event timing information;coupled analog simulators;hardware in the loop;event processing latency;SystemC model;linear prediction scheme;smart-sensor system model;quasiperiodic events;Synchronization;Stochastic processes;Predictive models;Simulation;Microcontrollers;Signal processing algorithms},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-08},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{glotra_17,
|
||
author = {Global Trade, Staff},
|
||
title = {{D}eutsche {P}ost {DHL} {S}elects {NVIDIA} for {A}utonomous {T}rucks},
|
||
howpublished = {http://www.globaltrademag.com/global-logistics/deutsche-post-dhl-selects-nvidia-autonomous-trucks},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-01},
|
||
year = {2017},
|
||
}
|
||
|
||
@Article{goebos_17,
|
||
author = {M. Goedicke and J. Bosch and H. H. Olsson and E. Almeida},
|
||
title = {3rd {I}nternational {W}orkshop on {R}apid {C}ontinuous {S}oftware {E}ngineering ({RC}o{S}e 2017)},
|
||
doi = {10.1109/RCoSE.2017.12},
|
||
pages = {1-1},
|
||
booktitle = {2017 IEEE/ACM 3rd International Workshop on Rapid Continuous Software Engineering (RCoSE)},
|
||
groups = {MJ:1},
|
||
keywords = {Requirements engineering;Research and development;Software;Software engineering;System integration},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2020-02-09},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{gomwei_12a,
|
||
author = {Gomony, Manil Dev and Weis, Christian and Akesson, Benny and Wehn, Norbert and Goossens, Kees},
|
||
booktitle = {{DATE}},
|
||
title = {{DRAM selection and configuration for real-time mobile systems}},
|
||
pages = {51--56},
|
||
bibsource = {DBLP, http://dblp.uni-trier.de},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.10},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{gonchu_15,
|
||
author = {Gong, Young-Ho and Chung, S.W.},
|
||
title = {{E}xploiting {R}efresh {E}ffect of {DRAM} {R}ead {O}perations: {A} {P}ractical {A}pproach to {L}ow-power {R}efresh},
|
||
doi = {10.1109/TC.2015.2448079},
|
||
issn = {0018-9340},
|
||
number = {99},
|
||
pages = {1-1},
|
||
volume = {PP},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {Buffer storage;DRAM chips;Hardware;Memory management;Temperature dependence;Temperature distribution;DRAM Refresh;Low-power Scheme;Main Memory;Refresh Interval},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{gonchu_16,
|
||
author = {Gong, Young-Ho and Chung, Sung Woo},
|
||
title = {{E}xploiting {R}efresh {E}ffect of {DRAM} {R}ead {O}perations: {A} {P}ractical {A}pproach to {L}ow-{P}ower {R}efresh},
|
||
doi = {10.1109/TC.2015.2448079},
|
||
issn = {0018-9340},
|
||
number = {5},
|
||
pages = {1507--1517},
|
||
url = {http://dx.doi.org/10.1109/TC.2015.2448079},
|
||
volume = {65},
|
||
acmid = {2925338},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {May 2016},
|
||
journal = {IEEE Trans. Comput.},
|
||
month = may,
|
||
numpages = {11},
|
||
owner = {MJ},
|
||
publisher = {IEEE Computer Society},
|
||
timestamp = {2016-11-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{gooake_13,
|
||
author = {S. Goossens and B. Akesson and K. Goossens},
|
||
booktitle = {2013 Design, Automation Test in Europe Conference Exhibition (DATE)},
|
||
title = {{C}onservative open-page policy for mixed time-criticality memory controllers},
|
||
doi = {10.7873/DATE.2013.118},
|
||
pages = {525-530},
|
||
groups = {MJ:1},
|
||
issn = {1530-1591},
|
||
keywords = {Bandwidth;Bismuth;Real-time systems;SDRAM;Schedules;Time factors;Timing},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2013},
|
||
}
|
||
|
||
@Book{gooake_16,
|
||
author = {Goossens, Sven and Akesson, Benny and Goossens, Kees and Chandrasekar, Karthik},
|
||
title = {{M}emory {C}ontrollers for {M}ixed-{T}ime-{C}riticality {S}ystems},
|
||
publisher = {Springer},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Book{goocha_16,
|
||
author = {Goossens, S. and Chandrasekar, K. and Akesson, B. and Goossens, K.},
|
||
title = {{M}emory {C}ontrollers for {M}ixed-{T}ime-{C}riticality {S}ystems: {A}rchitectures, {M}ethodologies and {T}rade-offs},
|
||
isbn = {9783319320946},
|
||
publisher = {Springer International Publishing},
|
||
series = {Embedded Systems},
|
||
url = {https://books.google.de/books?id=l9\_7CwAAQBAJ},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-18},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{goocha_16a,
|
||
author = {S. Goossens and K. Chandrasekar and B. Akesson and K. Goossens},
|
||
title = {{P}ower/{P}erformance {T}rade-{O}ffs in {R}eal-{T}ime {SDRAM} {C}ommand {S}cheduling},
|
||
doi = {10.1109/TC.2015.2458859},
|
||
issn = {0018-9340},
|
||
number = {6},
|
||
pages = {1882-1895},
|
||
volume = {65},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {DRAM chips;processor scheduling;real-time systems;DDR4 memories;ILP formulation;bounded worst-case bandwidth;generalized close-page memory command scheduling algorithm;hard bounds;memory devices;memory generations;pairwise bank-group interleaving scheme;power consumption;power usage;real-time SDRAM command scheduling;real-time SDRAM controllers;real-time safety-critical systems;response time;schedule length;scheduler-configuration design space;schedulers performance;Bandwidth;Bismuth;Performance evaluation;Real-time systems;SDRAM;Scheduling algorithms;Timing;Dynamic random access memory (DRAM);Memory control and access,;Real-time and embedded systems;dynamic random access memory (DRAM),;memory control and access;real-time and embedded systems},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2016},
|
||
}
|
||
|
||
@Misc{gotperformance15,
|
||
author = {Goto, Hiroshige},
|
||
title = {{P}erformance {M}emory {B}andwidth {R}oadmap},
|
||
howpublished = {https://pc.watch.impress.co.jp/video/pcw/docs/1054/618/p5.pdf},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-07},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{gra_15,
|
||
author = {Robert Graham},
|
||
title = {{S}ome notes on {DRAM} {R}owhammer},
|
||
howpublished = {\url{http://blog.erratasec.com/2015/03/some-notes-on-dram-rowhammer.html}},
|
||
groups = {MJ:1},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-23},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{green_17,
|
||
author = {Greenberg, Marc},
|
||
title = {{U}nderstanding {A}utomotive {DDR} {DRAM}},
|
||
url = {https://www.synopsys.com/designware-ip/technical-bulletin/automotive-ddr-dram.html},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-03},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{gri_98,
|
||
author = {Matthias Gries},
|
||
booktitle = {Workshop Hardware Design and Petri Nets HWPN98},
|
||
title = {{M}odeling a {M}emory {S}ubsystem with {P}etri {N}ets: a {C}ase {S}tudy},
|
||
pages = {186--201},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-05},
|
||
year = {1998},
|
||
}
|
||
|
||
@Book{gumamm_14,
|
||
author = {van Gumster, J. and Ammann, C.},
|
||
title = {{F}arming {S}imulator {M}odding {F}or {D}ummies},
|
||
isbn = {9781118940273},
|
||
publisher = {Wiley},
|
||
series = {--For dummies},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.25},
|
||
year = {2014},
|
||
}
|
||
|
||
@Patent{cho_01,
|
||
author = {{H.Y. Cho et al.}},
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||
title = {{Self-Refresh Apparatus for a Semiconductor Memory Device}},
|
||
address = {{US Patent 6,229,747}},
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||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-15},
|
||
year = {2001},
|
||
}
|
||
|
||
@TechReport{hac_76,
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||
author = {Hack, M.},
|
||
title = {{PETRI} {NET} {LANGUAGE}},
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||
address = {Cambridge, MA, USA},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
publisher = {Massachusetts Institute of Technology},
|
||
source = {http://www.ncstrl.org:8900/ncstrl/servlet/search?formname=detail\&id=oai%3Ancstrlh%3Amitai%3AMIT-LCS%2F%2FMIT%2FLCS%2FTR-159},
|
||
timestamp = {2017-02-27},
|
||
year = {1976},
|
||
}
|
||
|
||
@Article{halsch_09,
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||
author = {Halderman, J. Alex and Schoen, Seth D. and Heninger, Nadia and Clarkson, William and Paul, William and Calandrino, Joseph A. and Feldman, Ariel J. and Appelbaum, Jacob and Felten, Edward W.},
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||
title = {{L}est {W}e {R}emember: {C}old-boot {A}ttacks on {E}ncryption {K}eys},
|
||
doi = {10.1145/1506409.1506429},
|
||
issn = {0001-0782},
|
||
number = {5},
|
||
pages = {91--98},
|
||
url = {http://doi.acm.org/10.1145/1506409.1506429},
|
||
volume = {52},
|
||
acmid = {1506429},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {May 2009},
|
||
journal = {Commun. ACM},
|
||
month = may,
|
||
numpages = {8},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2017-09-11},
|
||
year = {2009},
|
||
}
|
||
|
||
@Article{hamsug_98,
|
||
author = {Hamamoto, T. and Sugiura, S. and Sawada, S.},
|
||
title = {{On the retention time distribution of dynamic random access memory (DRAM)}},
|
||
number = {6},
|
||
pages = {1300-1309},
|
||
volume = {45},
|
||
groups = {MJ:1},
|
||
journal = {Electron Devices, IEEE Transactions on},
|
||
month = {Jun},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.10},
|
||
year = {1998},
|
||
}
|
||
|
||
@InProceedings{hanors_13,
|
||
author = {Jie Han and Orshansky, M.},
|
||
booktitle = {Test Symposium (ETS), 2013 18th IEEE European},
|
||
title = {{A}pproximate computing: {A}n emerging paradigm for energy-efficient design},
|
||
doi = {10.1109/ETS.2013.6569370},
|
||
pages = {1-6},
|
||
groups = {MJ:1},
|
||
keywords = {adders;logic design;probability;stochastic processes;algorithm-level techniques;approximate arithmetic block design;approximate arithmetic circuits;approximate computing techniques;approximate full adders;digital systems;energy-efficient design;pertinent error;probabilistic computing;quality measures;stochastic computing;Adders;Algorithm design and analysis;Approximation algorithms;Probabilistic logic;Signal processing algorithms;Timing;adder;approximate computing;low-energy design;multiplier;probabilistic computing;stochastic computation},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2015.10.26},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{hanaga_14,
|
||
author = {Hansson, A. and Agarwal, N. and Kolli, A. and Wenisch, T. and Udipi, A.N.},
|
||
booktitle = {Performance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on},
|
||
title = {{S}imulating {DRAM} controllers for future system architecture exploration},
|
||
doi = {10.1109/ISPASS.2014.6844484},
|
||
pages = {201-210},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;logic design;parallel architectures;CPU;DRAM controllers;GPU;LPDDR3;WideIO;contemporary controller architecture;event-based model;full-system exploration;future system architectures;high-level memory controller model;mobile devices;multiprocessor memory system;open-source gem5 simulation framework;parallel architectures;servers;Bandwidth;Computer architecture;Data models;Generators;Random access memory;Switches;Timing},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.17},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{harbak_10,
|
||
author = {Q. Harvard and R. J. Baker and R. Drost},
|
||
booktitle = {2010 IEEE Workshop on Microelectronics and Electron Devices},
|
||
title = {{M}ain {M}emory with {P}roximity {C}ommunication: {A} {W}ide {I}/{O} {DRAM} {A}rchitecture},
|
||
doi = {10.1109/WMED.2010.5453754},
|
||
pages = {1-4},
|
||
groups = {MJ:1},
|
||
issn = {1947-3834},
|
||
keywords = {DRAM chips;I/O DRAM architecture;computer system;dynamic random access memory;efficiency 59.9 percent;main memory system;power consumption;proximity communication;storage capacity 4 Gbit;Bandwidth;Capacitors;Circuits;Computer architecture;Delay;Energy consumption;Manufacturing processes;Power engineering computing;Random access memory;Sun},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2016-08-10},
|
||
year = {2010},
|
||
}
|
||
|
||
@InProceedings{haskau_15,
|
||
author = {Mohamed Hassan and A. M. Kaushik and H. Patel},
|
||
booktitle = {21st IEEE Real-Time and Embedded Technology and Applications Symposium},
|
||
title = {{R}everse-engineering embedded memory controllers through latency-based analysis},
|
||
doi = {10.1109/RTAS.2015.7108453},
|
||
pages = {297-306},
|
||
groups = {MJ:1},
|
||
issn = {1545-3421},
|
||
keywords = {DRAM chips;reverse engineering;storage management;DRAM MC;DRAM memory controllers;address mapping scheme;command arbitration scheme;embedded memory controllers;latency-based analysis;microarchitecture simulation framework;microbenchmark;page policies;reverse-engineering;worst-case bound;Data transfer;Delays;Hardware;Radiation detectors;Random access memory;Software},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-23},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{haspat_18,
|
||
author = {M. {Hassan} and H. {Patel}},
|
||
title = {{MCX}plore: {A}utomating the {V}alidation {P}rocess of {DRAM} {M}emory {C}ontroller {D}esigns},
|
||
doi = {10.1109/TCAD.2017.2705123},
|
||
issn = {0278-0070},
|
||
number = {5},
|
||
pages = {1050-1063},
|
||
volume = {37},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
|
||
keywords = {DRAM chips;formal specification;program testing;MCXplore;validation process;DRAM memory controller designs;automated framework;memory controllers;formal models;memory requests;NuSMV model-checker;test templates;memory tests;regression test suites;Random access memory;Space exploration;Model checking;Computational modeling;Delays;Benchmark testing;Dynamic random access memory (DRAM);memory controller (MC);model checking;testing;validation;verification},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2019-05-27},
|
||
year = {2018},
|
||
}
|
||
|
||
@InProceedings{haspat_16,
|
||
author = {M. Hassan and H. Patel},
|
||
booktitle = {2016 Design, Automation Test in Europe Conference Exhibition (DATE)},
|
||
title = {{MCX}plore: {A}n automated framework for validating memory controller designs},
|
||
pages = {1357-1362},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;formal specification;integrated circuit design;regression analysis;temporal logic;DRAM MC;DRAM command interaction;MCXplore;NuSMV model-checker;automated framework;dynamic random access memory controllers;formal models;hard-to-detect timing violations;memory controller designs;open-source framework;regression tests;temporal logic specifications;Benchmark testing;Delays;Model checking;Random access memory;Space exploration;Switches},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-15},
|
||
year = {2016},
|
||
}
|
||
|
||
@Misc{hawfor_18,
|
||
author = {Hawkins, Andrew J.},
|
||
title = {{F}ord wants to be the self-driving {OS} for the future of transportation},
|
||
howpublished = {https://www.theverge.com/2018/1/9/16868814/ford-self-driving-autonomous-vehicle-ces-2018},
|
||
groups = {MJ:1},
|
||
month = {January},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-01},
|
||
year = {2018},
|
||
}
|
||
|
||
@InProceedings{helwun_99,
|
||
author = {Hellebrand, S. and Wunderlich, H. J. and Ivaniuk, A. and Klimets, Y. and Yarmolik, V. N.},
|
||
booktitle = {Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146)},
|
||
title = {{E}rror detecting refreshment for embedded {DRAM}s},
|
||
doi = {10.1109/VTEST.1999.766693},
|
||
pages = {384-390},
|
||
groups = {MJ:1},
|
||
issn = {1093-0167},
|
||
keywords = {DRAM chips;data compression;error detection;integrated circuit testing;memory architecture;embedded DRAMs;error detecting refreshment;error detection latency;high error coverage;low hardware costs;memory contents;online consistency checking;periodic refresh operation;precomputed reference characteristic;test characteristic;Built-in self-test;Code standards;Computer architecture;Computer errors;Concurrent computing;Delay;Memory architecture;Random access memory;Test pattern generators;Testing},
|
||
owner = {MJ},
|
||
timestamp = {2017-01-23},
|
||
year = {1999},
|
||
}
|
||
|
||
@Article{hen_16,
|
||
author = {Henkel, J.},
|
||
title = {{A}pproximate {C}omputing: {S}olving {C}omputing's {I}nefficiency {P}roblem?},
|
||
number = {1},
|
||
volume = {33},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design and Test},
|
||
month = {February},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Misc{hipsqlite15,
|
||
author = {Hipp, D. Richard and Kennedy, Dan and Mistachkin, Joe},
|
||
title = {{SQL}ite},
|
||
howpublished = {http://www.sqlite.org},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.18},
|
||
year = {Last Access: 18.02.2015},
|
||
}
|
||
|
||
@Book{hoebar_09,
|
||
author = {Hoelzle, Urs and Barroso, Luiz Andre},
|
||
title = {{T}he {D}atacenter {A}s a {C}omputer: {A}n {I}ntroduction to the {D}esign of {W}arehouse-{S}cale {M}achines},
|
||
edition = {1st},
|
||
isbn = {159829556X, 9781598295566},
|
||
publisher = {Morgan and Claypool Publishers},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-05-09},
|
||
year = {2009},
|
||
}
|
||
|
||
@InProceedings{houli_13,
|
||
author = {Chih-Sheng Hou and Jin-Fu Li and Chih-Yen Lo and Ding-Ming Kwai and Yung-Fa Chou and Cheng-Wen Wu},
|
||
booktitle = {VLSI Design, Automation, and Test (VLSI-DAT), 2013 International Symposium on},
|
||
title = {{A}n {FPGA}-based test platform for analyzing data retention time distribution of {DRAM}s},
|
||
doi = {10.1109/VLDI-DAT.2013.6533853},
|
||
pages = {1-4},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;field programmable gate arrays;logic testing;DRAM data retention time distribution analysis;FPGA-based test platform;Micron DRAM;dynamic random access memory;field programmable gate arrays;Built-in self-test;Circuit faults;Current measurement;Leakage currents;Random access memory;Temperature distribution;Temperature measurement},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2016.02.10},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{huashi_05,
|
||
author = {Huang, Hai and Shin, Kang G. and Lefurgy, Charles and Keller, Tom and Krishna T. Malladi and Ian Shaeffer and Liji Gopalakrishnan and David Lo and Benjamin C. Lee and Mark Horowitz},
|
||
booktitle = {Proceedings of the 2005 International Symposium on Low Power Electronics and Design},
|
||
title = {{I}mproving {E}nergy {E}fficiency by {M}aking {DRAM} {L}ess {R}andomly {A}ccessed},
|
||
doi = {10.1145/1077603.1077696},
|
||
isbn = {1-59593-137-6},
|
||
location = {San Diego, CA, USA},
|
||
pages = {393--398},
|
||
publisher = {ACM},
|
||
series = {ISLPED '05},
|
||
url = {http://doi.acm.org/10.1145/1077603.1077696},
|
||
acmid = {1077696},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {DDR, low power, memory system},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-22},
|
||
year = {2005},
|
||
}
|
||
|
||
@PhdThesis{huf_14,
|
||
author = {Simon Hufnagel},
|
||
title = {{T}owards the {E}fficient {C}reation of {A}ccurate and {H}igh-{P}erformance {V}irtual {P}rototypes},
|
||
pages = {135},
|
||
type = {doctoralthesis},
|
||
url = {http://nbn-resolving.de/urn:nbn:de:hbz:386-kluedo-38928},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
school = {Technische Universit{\"a}t Kaiserslautern},
|
||
timestamp = {2018-09-13},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{hurlin_08,
|
||
author = {I. Hur and C. Lin},
|
||
booktitle = {2008 IEEE 14th International Symposium on High Performance Computer Architecture},
|
||
title = {{A} comprehensive approach to {DRAM} power management},
|
||
doi = {10.1109/HPCA.2008.4658648},
|
||
pages = {305-316},
|
||
groups = {MJ:1},
|
||
issn = {1530-0897},
|
||
keywords = {DRAM chips;DRAM energy efficiency;DRAM power management;adaptive history-based memory scheduler;memory controller;Adaptive scheduling;Delay estimation;Energy consumption;Energy efficiency;Energy management;Memory management;Power system management;Random access memory;SDRAM;Technology management},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-22},
|
||
year = {2008},
|
||
}
|
||
|
||
@InProceedings{hurlin_04,
|
||
author = {Hur, Ibrahim and Lin, Calvin},
|
||
booktitle = {Proceedings of the 37th Annual IEEE/ACM International Symposium on Microarchitecture},
|
||
title = {{A}daptive {H}istory-{B}ased {M}emory {S}chedulers},
|
||
doi = {10.1109/MICRO.2004.4},
|
||
isbn = {0-7695-2126-6},
|
||
location = {Portland, Oregon},
|
||
pages = {343--354},
|
||
publisher = {IEEE Computer Society},
|
||
series = {MICRO 37},
|
||
url = {http://dx.doi.org/10.1109/MICRO.2004.4},
|
||
acmid = {1038953},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {2004},
|
||
}
|
||
|
||
@Article{hurrhi_19,
|
||
author = {J. Y. {Hur} and S. W. {Rhim} and B. H. {Lee} and W. {Jang}},
|
||
title = {{A}daptive {L}inear {A}ddress {M}ap for {B}ank {I}nterleaving in {DRAM}s},
|
||
pages = {129604-129616},
|
||
volume = {7},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Access},
|
||
owner = {MJ},
|
||
timestamp = {2020-06-05},
|
||
year = {2019},
|
||
}
|
||
|
||
@Electronic{inf_16,
|
||
author = {Infineon},
|
||
title = {{A}urix {F}amily},
|
||
groups = {MJ:1},
|
||
howpublished = {\url{http://www.infineon.com/cms/de/product/microcontroller/32-bit-tricore-tm-microcontroller/aurix-tm-family/channel.html?channel=db3a30433727a44301372b2eefbb48d9}},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-24},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{isejoh_09,
|
||
author = {Isen, C. and John, L.},
|
||
booktitle = {Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on},
|
||
title = {{ESKIMO} - energy savings using semantic knowledge of inconsequential memory occupancy for {DRAM} subsystem},
|
||
pages = {337-346},
|
||
groups = {MJ:1},
|
||
issn = {1072-4451},
|
||
keywords = {DRAM chips;operating systems (computers);optimisation;power aware computing;power consumption;storage management;DRAM subsystem;DRAMsim;ESKIMO;dynamic random access memory;energy saving;hardware validated DRAM simulator;inconsequential memory occupancy;memory manager;operating systems;optimization;power consumption reduction;semantic knowledge;Computer architecture;DRAM chips;Energy consumption;Energy management;Memory management;Microarchitecture;Operating systems;Power system management;Prefetching;Random access memory;Memory power and energy;allocated and freed memory states;cross-boundary or cross-layer architecture optimizations;program semantic aware architecture},
|
||
month = {Dec},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2009},
|
||
}
|
||
|
||
@Misc{iso26262,
|
||
author = {ISO},
|
||
title = {{Road vehicles -- Functional safety}},
|
||
type = {{Norm}},
|
||
added-at = {2013-09-11T11:25:58.000+0200},
|
||
groups = {MJ:1},
|
||
key = {{ISO 26262}},
|
||
keywords = {26262 iso},
|
||
number = {{ISO 26262}},
|
||
owner = {MJ},
|
||
publisher = {{ISO, Geneva, Switzerland}},
|
||
timestamp = {2013-09-11T11:25:58.000+0200},
|
||
year = {{2011}},
|
||
}
|
||
|
||
@Book{jac_09,
|
||
author = {Jacob, Bruce},
|
||
title = {{T}he {M}emory {S}ystem: {Y}ou {C}an'{T} {A}void {I}t, {Y}ou {C}an'{T} {I}gnore {I}t, {Y}ou {C}an'{T} {F}ake {I}t},
|
||
isbn = {159829587X, 9781598295870},
|
||
publisher = {Morgan and Claypool Publishers},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-10-30},
|
||
year = {2009},
|
||
}
|
||
|
||
@Book{jacng_10,
|
||
author = {Jacob, Bruce and Ng, S. and Wang, D.},
|
||
title = {{M}emory {S}ystems: {C}ache, {DRAM}, {D}isk},
|
||
isbn = {9780080553849},
|
||
publisher = {Elsevier Science},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.12},
|
||
year = {2010},
|
||
}
|
||
|
||
@InProceedings{jacjac_11,
|
||
author = {Jacobsen, Lasse and Jacobsen, Morten and M{\o}ller, Mikael H. and Srba, Ji{\v{r}}{\'i}},
|
||
booktitle = {SOFSEM 2011: Theory and Practice of Computer Science},
|
||
title = {{V}erification of {T}imed-{A}rc {P}etri {N}ets},
|
||
editor = {{\v{C}}ern{\'a}, Ivana and Gyim{\'o}thy, Tibor and Hromkovi{\v{c}}, Juraj and Jefferey, Keith and Kr{\'a}lovi{\'{c}}, Rastislav and Vukoli{\'{c}}, Marko and Wolf, Stefan},
|
||
isbn = {978-3-642-18381-2},
|
||
pages = {46--72},
|
||
publisher = {Springer Berlin Heidelberg},
|
||
abstract = {Timed-Arc Petri Nets (TAPN) are an extension of the classical P/T nets with continuous time. Tokens in TAPN carry an age and arcs between places and transitions are labelled with time intervals restricting the age of tokens available for transition firing. The TAPN model posses a number of interesting theoretical properties distinguishing them from other time extensions of Petri nets. We shall give an overview of the recent theory developed in the verification of TAPN extended with features like read/transport arcs, timed inhibitor arcs and age invariants. We will examine in detail the boundaries of automatic verification and the connections between TAPN and the model of timed automata. Finally, we will mention the tool TAPAAL that supports modelling, simulation and verification of TAPN and discuss a small case study of alternating bit protocol.},
|
||
address = {Berlin, Heidelberg},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-07-15},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{jagdie_16,
|
||
author = {Jagtap, Radhika and Diestelhorst, Stephan and Hansson, Andreas and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS), July, 2016, Samos Island, Greece},
|
||
title = {{E}xploring {S}ystem {P}erformance using {E}lastic {T}races: {F}ast, {A}ccurate and {P}ortable},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-05-14},
|
||
year = {2016},
|
||
}
|
||
|
||
@Conference{jagjun_17,
|
||
author = {Jagtap, Radhika and Jung, Matthias and Elsasser, Wendy and Weis, Christian and Hansson, Andreas and Wehn, Norbert},
|
||
booktitle = {International Symposium on Memory Systems (MEMSYS17)},
|
||
title = {{I}ntegrating {DRAM} {P}ower-{D}own {M}odes in gem5 and {Q}uantifying their {I}mpact},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-29},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{jahjun_18,
|
||
author = {Jahić, Jasmin and Jung, Matthias and Kuhn, Thomas and Kestel, Claus and Wehn, Norbert},
|
||
booktitle = {The 18th International Conference on Runtime Verification (RV 2018)},
|
||
title = {{A} {F}ramework for {N}on-{I}ntrusive {T}race-driven {S}imulation of {M}anycore {A}rchitectures with {D}ynamic {T}racing {C}onfiguration},
|
||
groups = {MJ:1},
|
||
month = {November},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-21},
|
||
year = {2018},
|
||
}
|
||
|
||
@Conference{jahjun_17,
|
||
author = {Jahić, Jasmin and Jung, Matthias and Kuhn, Thomas and Wehn, Norbert},
|
||
booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
|
||
title = {{S}upervised {T}esting of {C}oncurrent {S}oftware in {E}mbedded {S}ystems},
|
||
doi = {10.1109/SAMOS.2017.8344633},
|
||
pages = {233-238},
|
||
groups = {MJ:1},
|
||
keywords = {Computer bugs;Concurrent computing;Instruction sets;Synchronization;Task analysis;Testing;Concurrency;Data Races;FERAL;LLVM;Scheduling;Testing;Virtual Prototyping},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-10},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{jahkuh_18,
|
||
author = {Jahić, Jasmin and Kuhn, Thomas and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation},
|
||
title = {{BOSMI}: {A} {F}ramework for {N}on-intrusive {M}onitoring and {T}esting of {E}mbedded {M}ultithreaded {S}oftware on the {L}ogical {L}evel},
|
||
doi = {10.1145/3229631.3229641},
|
||
isbn = {978-1-4503-6494-2},
|
||
location = {Pythagorion, Greece},
|
||
pages = {131--138},
|
||
publisher = {ACM},
|
||
series = {SAMOS '18},
|
||
url = {http://doi.acm.org/10.1145/3229631.3229641},
|
||
acmid = {3229641},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {LLVM, concurrency, coverage, execution control, execution monitoring},
|
||
numpages = {8},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-25},
|
||
year = {2018},
|
||
}
|
||
|
||
@InProceedings{jahkum_19,
|
||
author = {Jahic, Jasmin and Kumar, Varun and Jung, Matthias and Wirrer, Gerhard and Wehn, Norbert and Kuhn, Thomas},
|
||
booktitle = {Proceedings of the 48th International Conference on Parallel Processing: Workshops},
|
||
title = {{R}apid {I}dentification of {S}hared {M}emory in {M}ultithreaded {E}mbedded {S}ystems with {S}tatic {S}cheduling},
|
||
doi = {10.1145/3339186.3339195},
|
||
isbn = {9781450371964},
|
||
location = {Kyoto, Japan},
|
||
publisher = {Association for Computing Machinery},
|
||
series = {ICPP 2019},
|
||
url = {https://doi.org/10.1145/3339186.3339195},
|
||
address = {New York, NY, USA},
|
||
articleno = {Article 15},
|
||
groups = {MJ:1},
|
||
keywords = {static scheduling, Data races, Lockset, embedded systems},
|
||
numpages = {8},
|
||
owner = {MJ},
|
||
timestamp = {2020-02-03},
|
||
year = {2019},
|
||
}
|
||
|
||
@InProceedings{jayrod_15,
|
||
author = {Jayaraj, Jagan and Rodrigues, Arun F. and Hammond, Simon D. and Voskuilen, Gwendolyn R.},
|
||
booktitle = {Proceedings of the 2015 International Symposium on Memory Systems},
|
||
title = {{T}he {P}otential and {P}erils of {M}ulti-{L}evel {M}emory},
|
||
doi = {10.1145/2818950.2818976},
|
||
isbn = {978-1-4503-3604-8},
|
||
location = {Washington DC, DC, USA},
|
||
pages = {191--196},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '15},
|
||
url = {http://doi.acm.org/10.1145/2818950.2818976},
|
||
acmid = {2818976},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {Application Analysis, Multi-Level Memory, Simulation},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-08},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{jeooh_16,
|
||
author = {Jeong, D. and Oh, Y. H. and Lee, J. W. and Park, Y.},
|
||
title = {{A}n e{DRAM}-{B}ased {A}pproximate {R}egister {F}ile for {GPU}s},
|
||
number = {1},
|
||
pages = {23-31},
|
||
volume = {33},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design \& Test},
|
||
month = {February},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Misc{jeodrsim,
|
||
author = {Min Kyu Jeong and Doe Hyun Yoon and Mattan Erez},
|
||
title = {{D}r{S}im: {A} {P}latform for {F}lexible {DRAM} {S}ystem {R}esearch},
|
||
howpublished = {http://lph.ece.utexas.edu/public/DrSim},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-08-15},
|
||
year = {(Last Access: 15.08.2019)},
|
||
}
|
||
|
||
@Article{jinyi_05,
|
||
author = {Seonghoon Jin and Jeong-Hyong Yi and Jae Hoon Choi and Dae Gwan Kang and Y. J. Park and Hong Shick Min},
|
||
title = {{P}rediction of data retention time distribution of {DRAM} by physics-based statistical {S}imulation},
|
||
doi = {10.1109/TED.2005.857185},
|
||
issn = {0018-9383},
|
||
number = {11},
|
||
pages = {2422-2429},
|
||
volume = {52},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Electron Devices},
|
||
keywords = {DRAM chips;Green's function methods;Monte Carlo methods;circuit simulation;integrated circuit modelling;leakage currents;statistical analysis;technology CAD (electronics);128 Mbit;DRAM cells;DRAM chips;Green function methods;Monte Carlo methods;Shockley-Read-Hall process;TCAD framework;cell transistor;coupled physics-based device simulation;cumulative distribution function;data retention time distribution;dynamic random access memory chip;gate-induced drain leakage;leakage currents;physics-based statistical simulation;statistical analysis;trap-assisted tunneling;DRAM chips;Distribution functions;Energy states;Green's function methods;Land surface temperature;Leakage current;Photonic band gap;Predictive models;Random access memory;Tunneling;Data retention time;Green's function methods;Monte Carlo methods;dynamic random access memory (DRAM);gate-induced drain leakage (GIDL);leakage currents;statistical analysis;stress (mechanical);trap-assisted tunneling (TAT)},
|
||
month = {Nov},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-14},
|
||
year = {2005},
|
||
}
|
||
|
||
@InProceedings{jouyou_17b,
|
||
author = {Jouppi, Norman P. and Young, Cliff and Patil, Nishant and others},
|
||
booktitle = {Proceedings of the 44th Annual International Symposium on Computer Architecture},
|
||
title = {{I}n-{D}atacenter {P}erformance {A}nalysis of a {T}ensor {P}rocessing {U}nit},
|
||
doi = {10.1145/3079856.3080246},
|
||
isbn = {978-1-4503-4892-8},
|
||
location = {Toronto, ON, Canada},
|
||
pages = {1--12},
|
||
publisher = {ACM},
|
||
series = {ISCA '17},
|
||
url = {http://doi.acm.org/10.1145/3079856.3080246},
|
||
acmid = {3080246},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {CNN, DNN, GPU, LSTM, MLP, RNN, TPU, TensorFlow, accelerator, deep learning, domain-specific architecture, neural network},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-17},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{jouyou_17,
|
||
author = {Jouppi, Norman P. and Young, Cliff and Patil, Nishant and Patterson, David and Agrawal, Gaurav and Bajwa, Raminder and Bates, Sarah and Bhatia, Suresh and Boden, Nan and Borchers, Al and Boyle, Rick and Cantin, Pierre-luc and Chao, Clifford and Clark, Chris and Coriell, Jeremy and Daley, Mike and Dau, Matt and Dean, Jeffrey and Gelb, Ben and Ghaemmaghami, Tara Vazir and Gottipati, Rajendra and Gulland, William and Hagmann, Robert and Ho, C. Richard and Hogberg, Doug and Hu, John and Hundt, Robert and Hurt, Dan and Ibarz, Julian and Jaffey, Aaron and Jaworski, Alek and Kaplan, Alexander and Khaitan, Harshit and Killebrew, Daniel and Koch, Andy and Kumar, Naveen and Lacy, Steve and Laudon, James and Law, James and Le, Diemthu and Leary, Chris and Liu, Zhuyuan and Lucke, Kyle and Lundin, Alan and MacKean, Gordon and Maggiore, Adriana and Mahony, Maire and Miller, Kieran and Nagarajan, Rahul and Narayanaswami, Ravi and Ni, Ray and Nix, Kathy and Norrie, Thomas and Omernick, Mark and Penukonda, Narayana and Phelps, Andy and Ross, Jonathan and Ross, Matt and Salek, Amir and Samadiani, Emad and Severn, Chris and Sizikov, Gregory and Snelham, Matthew and Souter, Jed and Steinberg, Dan and Swing, Andy and Tan, Mercedes and Thorson, Gregory and Tian, Bo and Toma, Horia and Tuttle, Erick and Vasudevan, Vijay and Walter, Richard and Wang, Walter and Wilcox, Eric and Yoon, Doe Hyun},
|
||
booktitle = {Proceedings of the 44th Annual International Symposium on Computer Architecture},
|
||
title = {{I}n-{D}atacenter {P}erformance {A}nalysis of a {T}ensor {P}rocessing {U}nit},
|
||
doi = {10.1145/3079856.3080246},
|
||
isbn = {978-1-4503-4892-8},
|
||
location = {Toronto, ON, Canada},
|
||
pages = {1--12},
|
||
publisher = {ACM},
|
||
series = {ISCA '17},
|
||
url = {http://doi.acm.org/10.1145/3079856.3080246},
|
||
acmid = {3080246},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {CNN, DNN, GPU, LSTM, MLP, RNN, TPU, TensorFlow, accelerator, deep learning, domain-specific architecture, neural network},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-17},
|
||
year = {2017},
|
||
}
|
||
|
||
@Book{jun_17,
|
||
author = {Jung, Matthias},
|
||
title = {{S}ystem-{L}evel {M}odeling, {A}nalysis and {O}ptimization of {DRAM} {M}emories and {C}ontroller {A}rchitectures},
|
||
isbn = {978-3-95974-051-7},
|
||
publisher = {University of Kaiserslautern},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
school = {University of Kaiserslautern},
|
||
timestamp = {2017-06-30},
|
||
year = {2017},
|
||
}
|
||
|
||
@PhdThesis{Phdjung17,
|
||
author = {Jung, Matthias},
|
||
title = {{S}ystem-{L}evel {M}odeling, {A}nalysis and {O}ptimization of {DRAM} {M}emories and {C}ontroller {A}rchitectures},
|
||
isbn = {978-3-95974-051-7},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
school = {University of Kaiserslautern},
|
||
timestamp = {2017-05-08},
|
||
year = {2017},
|
||
}
|
||
|
||
@Misc{junicewrapper15,
|
||
author = {Matthias Jung},
|
||
title = {{I}ce{W}rapper - {A} {S}ystem{C} {W}rapper for 3{D}-{ICE}},
|
||
howpublished = {\url{http://www.uni-kl.de/3d-dram/tools/icewrapper/}},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2015.10.29},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{junhei_16,
|
||
author = {Jung, Matthias and Heinrich, Irene and Natale, Marco and Mathew, Deepak M. and Weis, Christian and Krumke, Sven and Wehn, Norbert},
|
||
booktitle = {Proceedings of the Second International Symposium on Memory Systems},
|
||
title = {{C}on{G}en: {A}n {A}pplication {S}pecific {DRAM} {M}emory {C}ontroller {G}enerator},
|
||
doi = {10.1145/2989081.2989131},
|
||
isbn = {978-1-4503-4305-3},
|
||
location = {Alexandria, VA, USA},
|
||
pages = {257--267},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '16},
|
||
url = {http://doi.acm.org/10.1145/2989081.2989131},
|
||
acmid = {2989131},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {Address Mapping, Application Specific Memory Controller, Combinatorics, DRAM, Graph Theory, Optimization},
|
||
numpages = {11},
|
||
owner = {MJ},
|
||
timestamp = {2016-07-07},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{junhuo_20,
|
||
author = {Jung, Matthias and Huonker, Michael and Kalmar, Ralf and Wehn, Norbert},
|
||
title = {{M}oderne {S}peicherarchitekturen f{\"u}r leistungsf{\"a}hige {I}nfotainmentsysteme und autonomes {F}ahren},
|
||
doi = {10.1007/s35658-020-0269-0},
|
||
issn = {2192-8878},
|
||
number = {11},
|
||
pages = {16-21},
|
||
url = {https://doi.org/10.1007/s35658-020-0269-0},
|
||
volume = {15},
|
||
day = {01},
|
||
groups = {MJ:1},
|
||
journal = {ATZelektronik},
|
||
month = {Nov},
|
||
owner = {MJ},
|
||
timestamp = {2020-11-06},
|
||
year = {2020},
|
||
}
|
||
|
||
@InProceedings{junkra_19,
|
||
author = {Jung, Matthias and Kraft, Kira and Soliman, Taha and Sudarshan, Chirag and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {Proceedings of the International Symposium on Memory Systems},
|
||
title = {{F}ast {V}alidation of {DRAM} {P}rotocols with {T}imed {P}etri {N}ets},
|
||
doi = {10.1145/3357526.3357556},
|
||
isbn = {978-1-4503-7206-0},
|
||
location = {Washington, District of Columbia},
|
||
pages = {133--147},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '19},
|
||
url = {http://doi.acm.org/10.1145/3357526.3357556},
|
||
acmid = {3357556},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM, memory controller, petri net, validation},
|
||
numpages = {15},
|
||
owner = {MJ},
|
||
timestamp = {2019-11-14},
|
||
year = {2019},
|
||
}
|
||
|
||
@Conference{junkra_17,
|
||
author = {Jung, Matthias and Kraft, Kira and Wehn, Norbert},
|
||
booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
|
||
title = {{A} {N}ew {S}tate {M}odel for {DRAM}s {U}sing {P}etri {N}ets},
|
||
doi = {10.1109/SAMOS.2017.8344631},
|
||
pages = {221-226},
|
||
groups = {MJ:1},
|
||
keywords = {Computer architecture;Concurrent computing;Inhibitors;Parallel processing;Petri nets;Random access memory;Standards},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-29},
|
||
year = {2017},
|
||
}
|
||
|
||
@Article{junmat_17,
|
||
author = {Jung, Matthias and Mathew, Deepak and Rheinländer, Carl and Weis, Christian and Wehn, Norbert},
|
||
title = {{A} {P}latform to {A}nalyze {DDR}3 {DRAM}’s {P}ower and {R}etention {T}ime},
|
||
doi = {10.1109/MDAT.2017.2705144},
|
||
issn = {2168-2356},
|
||
number = {4},
|
||
pages = {52-59},
|
||
volume = {34},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design \& Test},
|
||
keywords = {DRAM chips;integrated circuit reliability;logic design;power consumption;DDR3;DRAM;power consumption;reliability;Current measurement;Heating systems;Power demand;Random access memory;Temperature measurement;Temperature sensors;Time measurement;Approximate DRAM;Currents;DDR3;DDR4;DRAM;Measurement Platform;Power;Retention Time},
|
||
month = {Aug},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{junmat_16a,
|
||
author = {Jung, Matthias and Mathew, Deepak and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {Proceedings of the 53rd Annual Design Automation Conference},
|
||
title = {{A}pproximate {C}omputing with {P}artially {U}nreliable {D}ynamic {R}andom {A}ccess {M}emory - {A}pproximate {DRAM}},
|
||
doi = {10.1145/2897937.2905002},
|
||
isbn = {978-1-4503-4236-0},
|
||
location = {Austin, Texas},
|
||
pages = {100:1--100:4},
|
||
publisher = {ACM},
|
||
series = {DAC '16},
|
||
acmid = {2905002},
|
||
address = {New York, NY, USA},
|
||
articleno = {100},
|
||
groups = {MJ:1},
|
||
keywords = {approximate computing, approxmiate DRAM, refresh, retention time},
|
||
numpages = {4},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-03},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{junmat_16,
|
||
author = {Jung, Matthias and Mathew, Deepak M. and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {21st Asia and South Pacific Design Automation Conference (ASP-DAC)},
|
||
title = {{E}fficient {R}eliability {M}anagement in {S}o{C}s - {A}n {A}pproximate {DRAM} {P}erspective},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.11.11},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{junmat_16b,
|
||
author = {Jung, Matthias and Mathew, Deepak M. and Zulian, \'Eder F. and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS 2016)},
|
||
title = {{A} {N}ew {B}ank {S}ensitive {DRAMP}ower {M}odel for {E}fficient {D}esign {S}pace {E}xploration},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-15},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{junmck_18,
|
||
author = {Jung, Matthias and McKee, Sally A. and Sudarshan, Chirag and Dropmann, Christoph and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {Proceedings of the International Symposium on Memory Systems},
|
||
title = {{D}riving into the {M}emory {W}all: {T}he {R}ole of {M}emory for {A}dvanced {D}river {A}ssistance {S}ystems and {A}utonomous {D}riving},
|
||
doi = {10.1145/3240302.3240322},
|
||
isbn = {978-1-4503-6475-1},
|
||
location = {Alexandria, Virginia},
|
||
pages = {377--386},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '18},
|
||
acmid = {3240322},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {ADAS, DRAM, autonomous driving},
|
||
numpages = {10},
|
||
owner = {MJ},
|
||
timestamp = {2018-06-05},
|
||
year = {2018},
|
||
}
|
||
|
||
@Article{junpia_15,
|
||
author = {Jung, Matthias and Piao, Songlin and Purusothaman, Thiyagarajan and Pan, Xiao and Kuhn, Thomas and Grimm, Christoph and Berns, Karsten and Wehn, Norbert},
|
||
title = {{V}irtual {D}evelopment on {M}ixed {A}bstraction {L}evels: an {A}gricultural {V}ehicle {C}ase {S}tudy},
|
||
groups = {MJ:1},
|
||
journal = {Synopsys Usergroup Conference (SNUG)},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{junrhe_16,
|
||
author = {Jung, Matthias and Rheinl{\"a}nder, Carl and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {International Symposium on Memory Systems (MEMSYS 2016)},
|
||
title = {{R}everse {E}ngineering of {DRAM}s: {R}ow {H}ammer with {C}rosshair},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-07-07},
|
||
year = {2016},
|
||
}
|
||
|
||
@InCollection{junsad_14,
|
||
author = {Jung, Matthias and Sadri, MohammadSadegh and Wehn, Norbert},
|
||
booktitle = {Tenth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES14)},
|
||
title = {{T}hermal {M}odelling of 3{D} {S}tacked {DRAM} with {V}irtual {P}latforms},
|
||
publisher = {Academia Press, Ghent, Belgium},
|
||
volume = {10},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2014},
|
||
}
|
||
|
||
@InCollection{junsad_13,
|
||
author = {Jung, Matthias and Sadri, MohammadSadegh and Wehn, Norbert},
|
||
booktitle = {Ninth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES13)},
|
||
title = {{V}irtual {P}latforms for {F}ast {M}emory {S}ubsystem {E}xploration {U}sing gem5 and {TLM}2.0},
|
||
pages = {153--156},
|
||
publisher = {Academia Press, Ghent, Belgium},
|
||
volume = {9},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{junsch_19,
|
||
author = {Jung, Matthias and Schnicke, Frank and Damm, Markus and Kuhn, Thomas and Wehn, Norbert},
|
||
booktitle = {IEEE Conference on Design, Automation and Test in Europe (DATE)},
|
||
title = {{S}peculative {T}emporal {D}ecoupling {U}sing \texttt{fork()}},
|
||
doi = {10.23919/DATE.2019.8714823},
|
||
pages = {1721-1726},
|
||
groups = {MJ:1},
|
||
issn = {1558-1101},
|
||
keywords = {Synchronization;Checkpointing;Kernel;Analytical models;Prototypes;Hardware;Temporal Decoupling;Fork;SystemC;Time Quantum;Virtual Prototyping},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2019-05-21},
|
||
year = {2019},
|
||
}
|
||
|
||
@InProceedings{junste_21,
|
||
author = {Jung, Matthias and Steiner, Lukas and Wehn, Norbert},
|
||
booktitle = {IEEE/VDE 24. Workshop „Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen” (MBMV 2021)},
|
||
title = {{T}he {O}pen {S}ource {DRAM} {S}imulator {DRAMS}ys4.0},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2021-04-01},
|
||
year = {2021},
|
||
}
|
||
|
||
@Conference{junweh_18,
|
||
author = {Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {Workshop on New Platforms for Future Cars: Current and Emerging Trends at IEEE Conference Design, Automation and Test in Europe (DATE)},
|
||
title = {{D}riving {A}gainst the {M}emory {W}all: {T}he {R}ole of {M}emory for {A}utonomous {D}riving},
|
||
groups = {MJ:1},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2018-02-11},
|
||
year = {2018},
|
||
}
|
||
|
||
@InProceedings{junweh_15,
|
||
author = {Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {gem5 User Workshop, International Symposium on Computer Architecture (ISCA)},
|
||
title = {{C}oupling gem5 with {S}ystem{C} {TLM} 2.0 {V}irtual {P}latforms},
|
||
address = {Portland, OR, USA.},
|
||
groups = {MJ:1},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{junwei_15a,
|
||
author = {Matthias Jung and Christian Weis and Norbert Wehn},
|
||
title = {{A} cross layer approach for efficient thermal management in 3{D} stacked {S}o{C}s},
|
||
doi = {10.1016/j.microrel.2015.12.025},
|
||
issn = {0026-2714},
|
||
note = {ICMAT 2015 Symposium},
|
||
pages = {43 - 47},
|
||
volume = {61},
|
||
abstract = {Abstract 3D stacking of silicon dies via Through Silicon Vias (TSVs) is an emerging technology to increase performance, energy efficiency and integration density of today's and future System-on-Chips (SoCs). Especially the stacking of Wide I/O \{DRAMs\} on top of a logic die is a very promising approach to tackle the memory wall and energy efficiency challenge. The potential of this type of stacking is currently under investigation by many research groups and companies in particular for mobile devices. There, for instance, the baseband processing and the application processor can be implemented on the same single logic die. On top of this die one or several Wide I/O \{DRAMs\} are stacked. An example of such a SoC is the \{WIOMING\} chip [15]. However, new challenges emerge, especially thermal management, which is already a very demanding challenge in current 2D SoCs. With 3D SoCs this problem exacerbates due to reliability issues such as the temperature sensitivity of DRAMs, i.e., the retention time of a \{DRAM\} cell largely decreases with increasing temperature. In this paper, we show a holistic cross layer reliability approach for efficient reliability management starting from measuring and modeling of \{DRAM\} retention errors, which finally leads to optimizations for specific applications. These optimizations exploit the data lifetime and the inherent error resilience of the application, which is for instance given in the probabilistic behavior of wireless communications.},
|
||
groups = {MJ:1},
|
||
journal = {Microelectronics Reliability},
|
||
keywords = {DRAM},
|
||
owner = {MJ},
|
||
timestamp = {2016-10-20},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{junwei_15,
|
||
author = {Jung, Matthias and Weis, Christian and Wehn, Norbert},
|
||
title = {{DRAMS}ys: {A} flexible {DRAM} {S}ubsystem {D}esign {S}pace {E}xploration {F}ramework},
|
||
doi = {10.2197/ipsjtsldm.8.63},
|
||
groups = {MJ:1},
|
||
journal = {IPSJ Transactions on System LSI Design Methodology (T-SLDM)},
|
||
month = {August},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-02},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{junwei_14,
|
||
author = {Jung, Matthias and Weis, Christian and Wehn, Norbert and Sadri, MohammadSadegh and Benini, Luca},
|
||
booktitle = {Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on},
|
||
title = {{O}ptimized active and power-down mode refresh control in 3{D}-{DRAM}s},
|
||
doi = {10.1109/VLSI-SoC.2014.7004159},
|
||
pages = {1-6},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;integrated circuit design;integrated circuit modelling;three-dimensional integrated circuits;3D integration;3D stacked systems;3D structure;3D-DRAMs;DRAM cells;DRAM controller model;DRAM refresh power;SystemC TLM-2.0;bank-wise refresh;energy reduction;future density optimized mobile computing platforms;lateral temperature variations;optimized active mode refresh control;per DRAM array hotspot detector;power density;power estimation;power-down mode policy;power-down mode refresh control;temperature variation aware bank-wise refresh;thermal dissipation;transaction level modeling;vertical temperature variations;virtual hardware platform;Arrays;Benchmark testing;Detectors;Energy consumption;Random access memory;Temperature sensors;Three-dimensional displays},
|
||
month = {Oct},
|
||
owner = {MJ},
|
||
timestamp = {2017-07-05},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{junzul_15,
|
||
author = {Jung, Matthias and Zulian, \'Eder and Mathew, Deepak and Herrmann, Matthias and Brugger, Christian and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {1st International Symposium on Memory Systems (MEMSYS 2015)},
|
||
title = {{O}mitting {R}efresh - {A} {C}ase {S}tudy for {C}ommodity and {W}ide {I}/{O} {DRAM}s},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{katstu_99,
|
||
author = {Katayama, Y. and Stuckey, E.J. and Morioka, S. and Wu, Z.},
|
||
booktitle = {Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on},
|
||
title = {{F}ault-tolerant refresh power reduction of {DRAM}s for quasi-nonvolatile data retention},
|
||
doi = {10.1109/DFTVS.1999.802898},
|
||
pages = {311-318},
|
||
groups = {MJ:1},
|
||
issn = {1550-5774},
|
||
keywords = {DRAM chips;Reed-Solomon codes;error correction codes;fault tolerance;DRAMs;adaptive refresh rate controller;data integrity;data pattern sensitivity;fault-tolerant refresh power reduction;memory system power usage;one-shot Reed-Solomon error correction code;part-to-part variations;perturbation effects;quasi-nonvolatile data retention;Adaptive control;DRAM chips;Error correction codes;Fault tolerance;Power system reliability;Programmable control;Random access memory;Reed-Solomon codes;Robust control;Standards development},
|
||
month = {Nov},
|
||
owner = {MJ},
|
||
timestamp = {2015.12.02},
|
||
year = {1999},
|
||
}
|
||
|
||
@InProceedings{kayabd_14,
|
||
author = {M. O. {Kayed} and M. {Abdelsalam} and R. {Guindi}},
|
||
booktitle = {2014 15th International Microprocessor Test and Verification Workshop},
|
||
title = {{A} {N}ovel {A}pproach for {SVA} {G}eneration of {DDR} {M}emory {P}rotocols {B}ased on {TDML}},
|
||
doi = {10.1109/MTV.2014.15},
|
||
pages = {61-66},
|
||
groups = {MJ:1},
|
||
issn = {1550-4093},
|
||
keywords = {DRAM chips;hardware description languages;memory protocols;SVA generation;TDML;System Verilog Assertions;Assertion Based Verification methodology;ABV methodology;hardware design specifications;general memory protocol standard;DDR memory protocols;timing diagram tool;Timing Diagram Markup Language;JEDEC LPDDR3 memory protocol standard;Standards;XML;Protocols;Hardware;Unified modeling language;Delays;Timing Diagrams;TDML;Functional Verification;SVA;DDR memories},
|
||
month = {Dec},
|
||
owner = {MJ},
|
||
timestamp = {2019-05-30},
|
||
year = {2014},
|
||
}
|
||
|
||
@Patent{kazyu_12,
|
||
author = {Kazi, Tauseef and Yu, Haobo and Cai, Lukai and Sridharan, Mahesh and Chaiyakul, Viraphol},
|
||
title = {{S}ystems and methods for improving digital system simulation speed by clock phase gating},
|
||
note = {US Patent 8,140,316},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
publisher = {Google Patents},
|
||
timestamp = {2019-08-08},
|
||
year = {2012},
|
||
}
|
||
|
||
@Misc{ker_18,
|
||
author = {Michael Kerrisk},
|
||
title = {{L}inux {P}rogrammer's {M}anual: {FORK}(2)},
|
||
howpublished = {http://man7.org/linux/man-pages/man2/fork.2.html},
|
||
groups = {MJ:1},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-13},
|
||
year = {2018},
|
||
}
|
||
|
||
@Book{kes_12,
|
||
author = {Kesel, Frank},
|
||
title = {{M}odellierung von digitalen {S}ystemen mit {S}ystem{C}: {V}on der {RTL}- zur {T}ransaction-{L}evel-{M}odellierung},
|
||
isbn = {9783486705812},
|
||
publisher = {Oldenbourg Wissenschaftsverlag},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.23},
|
||
year = {2012},
|
||
}
|
||
|
||
@InProceedings{khasal_15,
|
||
author = {K. {Khalifa} and K. {Salah}},
|
||
booktitle = {2015 10th International Conference on Design Technology of Integrated Systems in Nanoscale Era (DTIS)},
|
||
title = {{I}mplementation and verification of a generic universal memory controller based on {UVM}},
|
||
doi = {10.1109/DTIS.2015.7127364},
|
||
pages = {1-2},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;flash memories;low-power electronics;power consumption;generic universal memory controller;universal verification methodology;power consumption;FLASH;DRAM;Memory management;Monitoring;Random access memory;Time-varying systems;Time-domain analysis;Memory architecture;Protocols;Universal Memory Controller;low power Memory Controller;Flash;DRAM;UVM;eMMC;ONFI;One-NAND;UFS;HMC;WideIO;SSD;Verification Environment},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2019-05-30},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{khalee_14,
|
||
author = {Khan, Samira and Lee, Donghyuk and Kim, Yoongu and Alameldeen, Alaa R. and Wilkerson, Chris and Mutlu, Onur},
|
||
booktitle = {The 2014 ACM International Conference on Measurement and Modeling of Computer Systems},
|
||
title = {{T}he {E}fficacy of {E}rror {M}itigation {T}echniques for {DRAM} {R}etention {F}ailures: {A} {C}omparative {E}xperimental {S}tudy},
|
||
doi = {10.1145/2591971.2592000},
|
||
isbn = {978-1-4503-2789-3},
|
||
location = {Austin, Texas, USA},
|
||
pages = {519--532},
|
||
publisher = {ACM},
|
||
series = {SIGMETRICS '14},
|
||
url = {http://doi.acm.org/10.1145/2591971.2592000},
|
||
acmid = {2592000},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {dram, ecc, error correction, fault tolerance, memory scaling, retention failures, system-level detection and mitigation},
|
||
numpages = {14},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-08},
|
||
year = {2014},
|
||
}
|
||
|
||
@Article{khuzam_16,
|
||
author = {Khudia, D. S. and Zamirai, B. and Samadi, M. and Mahlke, S.},
|
||
title = {{Q}uality {C}ontrol for {A}pproximate {A}ccelerators by {E}rror {P}rediction},
|
||
number = {1},
|
||
pages = {43-50},
|
||
volume = {33},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design \& Test},
|
||
month = {February},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{kimoh_11a,
|
||
author = {H. Kim and B. Oh and Y. Son and K. Kim and S. Y. Cha and J. G. Jeong and S. J. Hong and H. Shin},
|
||
title = {{C}haracterization of the {V}ariable {R}etention {T}ime in {D}ynamic {R}andom {A}ccess {M}emory},
|
||
doi = {10.1109/TED.2011.2160066},
|
||
issn = {0018-9383},
|
||
number = {9},
|
||
pages = {2952-2958},
|
||
volume = {58},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Electron Devices},
|
||
keywords = {leakage currents;random-access storage;dynamic random access memory;leakage current fluctuation;variable retention time;Current measurement;Leakage current;Logic gates;Random access memory;Semiconductor device measurement;Temperature measurement;Time measurement;Dynamic random access memory (DRAM);gate-induced drain leakage (GIDL);leakage current;location of trap;random telegraph noise (RTN);variable retention time (VRT)},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-14},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{kimvij_03,
|
||
author = {H. S. Kim and N. Vijaykrishnan and M. Kandemir and E. Brockmeyer and F. Catthoor and M. J. Irwin},
|
||
booktitle = {Low Power Electronics and Design, 2003. ISLPED '03. Proceedings of the 2003 International Symposium on},
|
||
title = {{E}stimating influence of data layout optimizations on {SDRAM} energy consumption},
|
||
doi = {10.1109/LPE.2003.1231832},
|
||
pages = {40-43},
|
||
groups = {MJ:1},
|
||
keywords = {low-power electronics;optimisation;optimising compilers;paged storage;random-access storage;storage management;Ehrhart polynomials;Presburger arithmetic;SDRAM energy consumption;compile time estimation;data layout influence;data layout optimization;data page switching;memory access efficiency;memory latency;page granularity data locality;static page break estimation;video codes;Arithmetic;Bandwidth;Computer science;Data engineering;Delay;Energy consumption;Permission;Polynomials;Power engineering and energy;SDRAM},
|
||
month = {Aug},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {2003},
|
||
}
|
||
|
||
@InProceedings{kimoh_11,
|
||
author = {Jung-Sik Kim and Chi Sung Oh and Hocheol Lee and Donghyuk Lee and Hyong-Ryol Hwang and Sooman Hwang and Byongwook Na and Joungwook Moon and Jin-Guk Kim and Hanna Park and Jang-Woo Ryu and Kiwon Park and Sang-Kyu Kang and So-Young Kim and Hoyoung Kim and Jong-Min Bang and Hyunyoon Cho and Minsoo Jang and Cheolmin Han and Jung-Bae Lee and Kyehyun Kyung and Joo-Sun Choi and Young-Hyun Jun},
|
||
booktitle = {Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International},
|
||
title = {{A} 1.2{V} 12.8{GB}/s 2{G}b mobile {W}ide-{I}/{O} {DRAM} with 4x128 {I}/{O}s using {TSV}-based stacking},
|
||
doi = {10.1109/ISSCC.2011.5746413},
|
||
pages = {496-498},
|
||
groups = {MJ:1},
|
||
issn = {0193-6530},
|
||
keywords = {DRAM chips;low-power electronics;three-dimensional integrated circuits;TSV-based stacking;byte rate 12.8 GByte/s;low power consumption;mobile wide-I/O DRAM;portable electronic devices;single data rate;storage capacity 1 Gbit;storage capacity 2 Gbit;voltage 1.2 V;wide-I/O mobile SDRAM;Arrays;Clocks;Mobile communication;Pins;Random access memory;Registers;Timing},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2015.04.13},
|
||
year = {2011},
|
||
}
|
||
|
||
@Article{kimlee_09,
|
||
author = {Kim, Kinam and Jooyoung Lee},
|
||
title = {{A} {N}ew {I}nvestigation of {D}ata {R}etention {T}ime in {T}ruly {N}anoscaled {DRAM}s},
|
||
doi = {10.1109/LED.2009.2023248},
|
||
issn = {0741-3106},
|
||
number = {8},
|
||
pages = {846-848},
|
||
volume = {30},
|
||
groups = {MJ:1},
|
||
journal = {Electron Device Letters, IEEE},
|
||
keywords = {DRAM chips;leakage currents;nanoelectronics;data retention time;full chip retention failure curve;gate-induced drain leakage current;interface trap density;nanoscaled DRAM;scaled-down cell size;trap energy dispersion;DRAM;Data retention time;gate-induced drain leakage (GIDL) currents;recess channel array transistor (RCAT);trap-assisted tunneling (TAT)},
|
||
month = {Aug},
|
||
owner = {MJ},
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||
timestamp = {2015.10.28},
|
||
year = {2009},
|
||
}
|
||
|
||
@InProceedings{kimdal_14,
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||
author = {Yoongu Kim and R. Daly and J. H. Kim and C. Fallin and Ji Hye Lee and Donghyuk Lee and C. Wilkerson and K. Lai and O. Mutlu},
|
||
booktitle = {ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)},
|
||
title = {{F}lipping bits in memory without accessing them: {A}n experimental study of {DRAM} disturbance errors},
|
||
doi = {10.1109/ISCA.2014.6853210},
|
||
pages = {361-372},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;field programmable gate arrays;AMD systems;DRAM accesses;DRAM cells;DRAM chips;DRAM disturbance errors;DRAM modules;DRAM process technology;FPGA-based testing platform;Intel;charge leakage;intercell coupling effects;malicious program;memory address;memory bit flipping;memory isolation;reliable computing system;secure computing system;Acceleration;Artificial intelligence;DRAM chips;Organizations;Testing;Timing},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-18},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{kimhan_10,
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||
author = {Y. Kim and D. Han and O. Mutlu and M. Harchol-Balter},
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||
booktitle = {HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture},
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||
title = {{ATLAS}: {A} scalable and high-performance scheduling algorithm for multiple memory controllers},
|
||
doi = {10.1109/HPCA.2010.5416658},
|
||
pages = {1-12},
|
||
groups = {MJ:1},
|
||
issn = {1530-0897},
|
||
keywords = {Pareto distribution;digital storage;microprocessor chips;multiprocessing systems;scheduling;ATLAS memory scheduling;Pareto workload distribution;adaptive per-thread least-attained-service;chip multiprocessor;multiple memory controllers;multiprogrammed SPEC 2006 workloads;scheduling algorithm;single-server queue;Adaptive control;Algorithm design and analysis;Bandwidth;Control systems;Feeds;Programmable control;Queueing analysis;Scheduling algorithm;Throughput;Yarn},
|
||
month = {Jan},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-02},
|
||
year = {2010},
|
||
}
|
||
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||
@InProceedings{kimpap_10,
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author = {Kim, Yoongu and Papamichael, Michael and Mutlu, Onur and Harchol-Balter, Mor},
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||
booktitle = {Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture},
|
||
title = {{T}hread {C}luster {M}emory {S}cheduling: {E}xploiting {D}ifferences in {M}emory {A}ccess {B}ehavior},
|
||
doi = {10.1109/MICRO.2010.51},
|
||
isbn = {978-0-7695-4299-7},
|
||
pages = {65--76},
|
||
publisher = {IEEE Computer Society},
|
||
series = {MICRO '43},
|
||
url = {http://dx.doi.org/10.1109/MICRO.2010.51},
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||
acmid = {1935012},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
keywords = {memory scheduling, memory access behavior, fairness, system throughput, thread cluster, niceness},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-02},
|
||
year = {2010},
|
||
}
|
||
|
||
@Article{kimyan_15,
|
||
author = {Kim, Yoongu and Yang, Weikun and Mutlu, Onur},
|
||
title = {{R}amulator: {A} {F}ast and {E}xtensible {DRAM} {S}imulator},
|
||
doi = {10.1109/LCA.2015.2414456},
|
||
issn = {1556-6056},
|
||
number = {99},
|
||
pages = {1-1},
|
||
volume = {PP},
|
||
groups = {MJ:1},
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||
journal = {IEEE Computer Architecture Letters},
|
||
keywords = {Hardware design languages;Nonvolatile memory;Proposals;Random access memory;Runtime;Standards;Timing},
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||
owner = {MJ},
|
||
timestamp = {2016-05-17},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{koggenerating10,
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||
author = {Kogel, Tim},
|
||
title = {{Generating Workload Models from TLM-2.0-based Virtual Prototypes for Efficient Architecture Performance Analysis}},
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||
howpublished = {\url{http://www.nascug.org/events/13th/tlm20_workload_models.pdf}},
|
||
booktitle = {{talk NASCUG 13}},
|
||
groups = {MJ:1},
|
||
month = {Jun.},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2010, Last Access: 19.02.2015},
|
||
}
|
||
|
||
@Article{kog_16,
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||
author = {Kogel, Tim},
|
||
title = {{O}ptimizing {DDR} {M}emory {S}ubsystem {E}fficiency - {T}he {U}npredictable {M}emory {B}ottleneck},
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||
groups = {MJ:1},
|
||
journal = {\mbox{Synopsys Inc.}},
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||
month = {January},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {2016},
|
||
}
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@InProceedings{kraleu_09,
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author = {S. Kraemer and R. Leupers and D. Petras and T. Philipp},
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booktitle = {2009 International Symposium on System-on-Chip},
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||
title = {{A} checkpoint/restore framework for systemc-based virtual platforms},
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||
doi = {10.1109/SOCC.2009.5335656},
|
||
pages = {161-167},
|
||
groups = {MJ:1},
|
||
keywords = {checkpointing;graphical user interfaces;software engineering;checkpoint/restore framework;SystemC-based virtual platforms;edit-compile-debug cycle;checkpoint image;interactive GUI;checkpointing;Checkpointing;Hardware;Image restoration;Personal digital assistants;Signal restoration;Productivity;Debugging;Programming;Application software;Signal processing},
|
||
month = {Oct},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-09},
|
||
year = {2009},
|
||
}
|
||
|
||
@InProceedings{krajun_18,
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||
author = {Kraft, Kira and Jung, Matthias and Sudarshan, Chiarg and Mathew, Deepak M. and Weis, Christian and Wehn, Norbert},
|
||
booktitle = {IEEE Conference Design, Automation and Test in Europe (DATE)},
|
||
title = {{I}mproving the {E}rror {B}ehavior of {DRAM} by {E}xploiting its {Z}-{C}hannel {P}roperty},
|
||
groups = {MJ:1},
|
||
month = {March},
|
||
owner = {MJ},
|
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timestamp = {2017-11-05},
|
||
year = {2018},
|
||
}
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|
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@InProceedings{kramat_18,
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author = {Kraft, Kira and Mathew, Deepak M. and Sudarshan, Chirag and Jung, Matthias and Weis, Christian and Wehn, Norbert and Longnos, Florian},
|
||
booktitle = {ACM International Symposium on Memory Systems (MEMSYS 2018)},
|
||
title = {{E}fficient {C}oding {S}cheme for {DDR}4 {M}emory {S}ubsystems},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
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timestamp = {2018-06-05},
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||
year = {2018},
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||
}
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@InProceedings{krudon_11a,
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author = {Krueger, J. and Donofrio, D. and Shalf, J. and Mohiyuddin, M. and Williams, S. and Oliker, L. and Pfreundt, F.-J.},
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booktitle = {High Performance Computing, Networking, Storage and Analysis (SC), 2011 International Conference for},
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||
title = {{H}ardware/software co-design for energy-efficient seismic modeling},
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pages = {1-12},
|
||
groups = {MJ:1},
|
||
keywords = {field programmable gate arrays;geophysics computing;graphics processing units;hardware-software codesign;multiprocessing systems;power aware computing;seismology;wave equations;FPGA-accelerated architectural simulation platform;Green Wave design;HPC cluster;Intel Nehalem X5530 multicore processor;NVIDIA Tesla C2050 GPU;PDE;RTM stencil;energy-efficient seismic modeling;general-purpose manycore chip design;hardware-software codesign;high-order wave equation;reverse time migration;seismic imaging;Computer architecture;Graphics processing unit;Green products;Hardware;Propagation;System-on-a-chip;GPU;RTM;co-design;manycore;seismic;stencil},
|
||
month = {Nov},
|
||
owner = {MJ},
|
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timestamp = {2015.02.10},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{kuhfor_13,
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||
author = {T. Kuhn and T. Forster and T. Braun and R. Gotzhein},
|
||
booktitle = {2013 Eleventh ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2013)},
|
||
title = {{FERAL} - {F}ramework for simulator coupling on requirements and architecture level},
|
||
pages = {11-22},
|
||
groups = {MJ:1},
|
||
month = {Oct},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-13},
|
||
year = {2013},
|
||
}
|
||
|
||
@Electronic{kus_16,
|
||
author = {Ingo Kuss},
|
||
title = {{A}udi z{FAS} - {E}norme {D}atenmengen bewältigen},
|
||
url = {http://www.elektroniknet.de/elektronik-automotive/assistenzsysteme/enorme-datenmengen-bewaeltigen-131797.html},
|
||
groups = {MJ:1},
|
||
month = {07},
|
||
owner = {MJ},
|
||
timestamp = {2018-01-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{kwoseo_17,
|
||
author = {H. J. Kwon and E. Seo and C. Y. Lee and Y. H. Seo and G. H. Han and H. R. Kim and J. H. Lee and M. S. Jang and S. G. Do and S. H. Cho and J. K. Park and S. Y. Doo and J. B. Shin and S. H. Jung and H. J. Kim and I. H. Im and B. R. Cho and J. W. Lee and J. Y. Lee and K. H. Yu and H. K. Kim and C. H. Jeon and H. S. Park and S. S. Kim and S. H. Lee and J. W. Park and S. S. Lee and B. T. Lim and J. y. Park and Y. S. Park and H. J. Kwon and S. J. Bae and J. H. Choi and K. I. Park and S. J. Jang and G. Y. Jin},
|
||
booktitle = {2017 IEEE International Solid-State Circuits Conference (ISSCC)},
|
||
title = {23.4 {A}n extremely low-standby-power 3.733{G}b/s/pin 2{G}b {LPDDR}4 {SDRAM} for wearable devices},
|
||
doi = {10.1109/ISSCC.2017.7870427},
|
||
pages = {394-395},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;error correction codes;low-power electronics;DRAM periodic self-refresh;active-mode power efficiency;battery life;data retention;deep-power-down mode;dual-page-size scheme;error-correction-code engine;extremely low-standby-power LPDDR4 SDRAM;high-resolution graphic engines;intensive power gating;leakage current;limited battery capacity;memory bandwidth;power 0.15 mW;self-refresh current reduction;smart glasses;smart watches;storage capacity 2 Gbit;temperature controlled internal power generator;wearable devices},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2017-09-13},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{kwogen_20,
|
||
author = {Kwong, Andrew and Genkin, Daniel and Gruss, Daniel and Yarom, Yuval},
|
||
booktitle = {Proceedings of the 41st Annual IEEE Symposium on Security \& Privacy, May 2020},
|
||
title = {{RAMB}leed: {R}eading {B}its in {M}emory {W}ithout {A}ccessing {T}hem},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-06-18},
|
||
year = {2020},
|
||
}
|
||
|
||
@Patent{che_02,
|
||
author = {{L.L. Chen Hsu et al.}},
|
||
title = {{Dynamic DRAM Refresh Rate Adjustment Based on Cell Leakage Monitoring}},
|
||
address = {{US Patent 6,483,764}},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-15},
|
||
year = {2002},
|
||
}
|
||
|
||
@Electronic{arm_16,
|
||
author = {ARM Ldt.},
|
||
title = {{C}ycle {M}odels},
|
||
groups = {MJ:1},
|
||
howpublished = {\url{https://developer.arm.com/products/system-design/cycle-models}},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-24},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{lebfan_00,
|
||
author = {Lebeck, Alvin R. and Fan, Xiaobo and Zeng, Heng and Ellis, Carla},
|
||
booktitle = {Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems},
|
||
title = {{P}ower {A}ware {P}age {A}llocation},
|
||
doi = {10.1145/378993.379007},
|
||
isbn = {1-58113-317-0},
|
||
location = {Cambridge, Massachusetts, USA},
|
||
pages = {105--116},
|
||
publisher = {ACM},
|
||
series = {ASPLOS IX},
|
||
url = {http://doi.acm.org/10.1145/378993.379007},
|
||
acmid = {379007},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-13},
|
||
year = {2000},
|
||
}
|
||
|
||
@InProceedings{leeeom_17,
|
||
author = {C. K. Lee and Y. J. Eom and J. H. Park and J. Lee and H. R. Kim and K. Kim and Y. Choi and H. J. Chang and J. Kim and J. M. Bang and S. Shin and H. Park and S. Park and Y. R. Choi and H. Lee and K. H. Jeon and J. Y. Lee and H. J. Ahn and K. H. Kim and J. S. Kim and S. Chang and H. R. Hwang and D. Kim and Y. H. Yoon and S. H. Hyun and J. Y. Park and Y. G. Song and Y. S. Park and H. J. Kwon and S. J. Bae and T. Y. Oh and I. D. Song and Y. C. Bae and J. H. Choi and K. I. Park and S. J. Jang and G. Y. Jin},
|
||
booktitle = {2017 IEEE International Solid-State Circuits Conference (ISSCC)},
|
||
title = {23.2 {A} 5{G}b/s/pin 8{G}b {LPDDR}4{X} {SDRAM} with power-isolated {LVSTL} and split-die architecture with 2-die {ZQ} calibration scheme},
|
||
doi = {10.1109/ISSCC.2017.7870425},
|
||
pages = {390-391},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;calibration;low-power electronics;LPDDR4X SDRAM;LPDDR4X memory;PI-LVSTL;ZQ calibration scheme;enhanced power-efficiency;low-power mobile DRAM;low-power mobile applications;low-power system designs;power-isolated low-voltage-swing terminated logic;split-die architecture;Calibration;Capacitance;Equalizers;Impedance;Mobile applications;SDRAM},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2017-09-13},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{leekim_15,
|
||
author = {D. Lee and Y. Kim and G. Pekhimenko and S. Khan and V. Seshadri and K. Chang and O. Mutlu},
|
||
booktitle = {High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on},
|
||
title = {{A}daptive-latency {DRAM}: {O}ptimizing {DRAM} timing for the common-case},
|
||
doi = {10.1109/HPCA.2015.7056057},
|
||
pages = {489-501},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;field programmable gate arrays;integrated circuit reliability;integrated circuit testing;AL-DRAM;DRAM chip;DRAM standard;FPGA-based testing platform;access latency;adaptive-latency DRAM;memory-intensive workloads;minimum latency restrictions;process variation;temperature 55 C;temperature 85 C;timing parameters;DRAM chips;Reliability;Temperature dependence;Temperature measurement;Testing;Timing},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-14},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{leepar_10,
|
||
author = {M. J. Lee and K. W. Park},
|
||
title = {{A} {M}echanism for {D}ependence of {R}efresh {T}ime on {D}ata {P}attern in {DRAM}},
|
||
doi = {10.1109/LED.2009.2038243},
|
||
issn = {0741-3106},
|
||
number = {2},
|
||
pages = {168-170},
|
||
volume = {31},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Electron Device Letters},
|
||
keywords = {DRAM chips;pattern recognition;DRAM chips;cell leakage mechanism;data pattern;dynamic random access memory;refresh time;Bit-line sense amplifier (BLSA);cell leakage;data pattern;offset;refresh time (tREF);sensing noise},
|
||
month = {Feb},
|
||
owner = {MJ},
|
||
timestamp = {2016-12-14},
|
||
year = {2010},
|
||
}
|
||
|
||
@Article{ligu_16,
|
||
author = {Li, B. and Gu, P. and Wang, Y. and Yang, H.},
|
||
title = {{E}xploring the {P}recision {L}imitation for {RRAM}-{B}ased {A}nalog {A}pproximate {C}omputing},
|
||
number = {1},
|
||
pages = {51-58},
|
||
volume = {33},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design \& Test},
|
||
month = {February},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@TechReport{liwan_10,
|
||
author = {Li, Nan and Wang, Yi and Zhou, Huisheng and Liang, Lei},
|
||
title = {{Design and Implementation of an Accurate Memory Subsystem Model in SystemC}},
|
||
url = {http://www.ocpip.org/memory_model.php},
|
||
groups = {MJ:1},
|
||
month = dec,
|
||
organization = {OCP},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.17},
|
||
year = {2010},
|
||
}
|
||
|
||
@InProceedings{lijac_19,
|
||
author = {Li, Shang and Jacob, Bruce},
|
||
booktitle = {Proceedings of the International Symposium on Memory Systems},
|
||
title = {{S}tatistical {DRAM} {M}odeling},
|
||
doi = {10.1145/3357526.3357576},
|
||
isbn = {9781450372060},
|
||
location = {Washington, District of Columbia},
|
||
pages = {521–530},
|
||
publisher = {Association for Computing Machinery},
|
||
series = {MEMSYS ’19},
|
||
url = {https://doi.org/10.1145/3357526.3357576},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM modeling, architecture simulation, cycle accurate simulation},
|
||
numpages = {10},
|
||
owner = {MJ},
|
||
timestamp = {2020.03.10},
|
||
year = {2019},
|
||
}
|
||
|
||
@Article{liyan_20,
|
||
author = {S. {Li} and Z. {Yang} and D. {Reddy} and A. {Srivastava} and B. {Jacob}},
|
||
title = {{DRAM}sim3: a {C}ycle-accurate, {T}hermal-{C}apable {DRAM} {S}imulator},
|
||
doi = {10.1109/LCA.2020.2973991},
|
||
issn = {2473-2575},
|
||
pages = {1-1},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Computer Architecture Letters},
|
||
keywords = {Random access memory;Thermal conductivity;Protocols;Thermal resistance;Computational modeling;Integrated circuit modeling;Three-dimensional displays;DRAM;Cycle-accurate;Simulation;3D-modeling;Thermal Modeling},
|
||
owner = {MJ},
|
||
timestamp = {2020-03-12},
|
||
year = {2020},
|
||
}
|
||
|
||
@InProceedings{liake_14,
|
||
author = {Y. Li and B. Akesson and K. Goossens},
|
||
booktitle = {2014 26th Euromicro Conference on Real-Time Systems},
|
||
title = {{D}ynamic {C}ommand {S}cheduling for {R}eal-{T}ime {M}emory {C}ontrollers},
|
||
doi = {10.1109/ECRTS.2014.18},
|
||
pages = {3-14},
|
||
groups = {MJ:1},
|
||
issn = {1068-3070},
|
||
keywords = {Bismuth;Dynamic scheduling;Heuristic algorithms;Memory management;Real-time systems;SDRAM;Timing},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{liake_16,
|
||
author = {Y. {Li} and B. {Akesson} and K. {Lampka} and K. {Goossens}},
|
||
booktitle = {2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)},
|
||
title = {{M}odeling and {V}erification of {D}ynamic {C}ommand {S}cheduling for {R}eal-{T}ime {M}emory {C}ontrollers},
|
||
doi = {10.1109/RTAS.2016.7461341},
|
||
pages = {1-12},
|
||
groups = {MJ:1},
|
||
keywords = {automata theory;DRAM chips;multiprocessing systems;processor scheduling;real-time systems;dynamic command scheduling verification;dynamic command scheduling modeling;real-time memory controllers;multicore systems;multiple real-time applications;memory traffic;RT memory controllers;dynamic command scheduling;SDRAM timing constraints;tight bounds;worst-case response time;WCRT;worst-case bandwidth;WCBW;timed automata;TA model;model checking;worst-case transaction traces;SDRAM;Timing;Dynamic scheduling;Clocks;Adaptation models;Analytical models;Model checking},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2019-06-03},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{limlim_15,
|
||
author = {J. Lim and H. Lim and S. Kang},
|
||
title = {3-{D} {S}tacked {DRAM} {R}efresh {M}anagement {W}ith {G}uaranteed {D}ata {R}eliability},
|
||
doi = {10.1109/TCAD.2015.2413411},
|
||
issn = {0278-0070},
|
||
number = {9},
|
||
pages = {1455-1466},
|
||
volume = {34},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
|
||
keywords = {DRAM chips;low-power electronics;reliability;temperature sensors;three-dimensional integrated circuits;3-D stacked DRAM refresh management;data communication power reduction;dynamic random-access memory;guaranteed data reliability;on-chip temperature sensor-dependent adaptive refresh control;temperature-aware refresh management;thermal guard-band set-up method;Computer architecture;Microprocessors;Random access memory;Reliability;Temperature distribution;Temperature sensors;Three-dimensional displays;3-D integration;DRAM refresh;Data reliability;Terms—3D integration;data reliability},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-16},
|
||
year = {2015},
|
||
}
|
||
|
||
@Electronic{lim_17,
|
||
author = {Imperas Software Limited},
|
||
title = {{O}pen {V}irtual {P}latforms - the source of {F}ast {P}rocessor {M}odels \& {P}latforms},
|
||
url = {http://www.ovpworld.org},
|
||
organization = {Imperas Software Limited},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-04-05},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{linshe_12,
|
||
author = {Chung-Hsiang Lin and De-Yu Shen and Yi-Jung Chen and Chia-Lin Yang and Wang, M.},
|
||
booktitle = {IEEE 30th International Conference on Computer Design (ICCD)},
|
||
title = {{SECRET}: {S}elective error correction for refresh energy reduction in {DRAM}s},
|
||
doi = {10.1109/ICCD.2012.6378619},
|
||
pages = {67-74},
|
||
groups = {MJ:1},
|
||
issn = {1063-6404},
|
||
keywords = {DRAM chips;energy conservation;error correction;integrated circuit design;low-power electronics;power aware computing;DRAM power reduction;SECRET;dynamic random-access memory;error correction information;hard errors;leaky cells;low-overhead error correction mechanism;low-power DRAM design;main memory;memory cell identification;memory cells;off-line phase;process variation;refresh interval;refresh power reduction;retention errors;retention time variation;selective error correction for refresh energy reduction;single worst-case refresh period;system power consumption;target error rate;DRAM chips;Decoding;Error analysis;Error correction;Error correction codes;Memory management},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2012},
|
||
}
|
||
|
||
@InProceedings{linrei_01,
|
||
author = {Wei-Fen Lin and Reinhardt, S.K. and Burger, D.},
|
||
booktitle = {High-Performance Computer Architecture, 2001. HPCA. The Seventh International Symposium on},
|
||
title = {{R}educing {DRAM} latencies with an integrated memory hierarchy design},
|
||
doi = {10.1109/HPCA.2001.903272},
|
||
pages = {301-312},
|
||
groups = {MJ:1},
|
||
issn = {1530-0897},
|
||
keywords = {cache storage;memory architecture;performance evaluation;DRAM accesses;Rambus channels;benchmarks;cache blocks;integrated memory hierarchy;next-generation memory system;performance;performance gap;Banking;Clocks;Computer science;Degradation;Delay;Dynamic scheduling;Frequency;High performance computing;Prefetching;Random access memory},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.21},
|
||
year = {2001},
|
||
}
|
||
|
||
@Article{liujai_13,
|
||
author = {Liu, Jamie and Jaiyen, Ben and Kim, Yoongu and Wilkerson, Chris and Mutlu, Onur},
|
||
title = {{A}n {E}xperimental {S}tudy of {D}ata {R}etention {B}ehavior in {M}odern {DRAM} {D}evices: {I}mplications for {R}etention {T}ime {P}rofiling {M}echanisms},
|
||
doi = {10.1145/2508148.2485928},
|
||
issn = {0163-5964},
|
||
number = {3},
|
||
pages = {60--71},
|
||
url = {http://doi.acm.org/10.1145/2508148.2485928},
|
||
volume = {41},
|
||
acmid = {2485928},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {June 2013},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
month = jun,
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2015.07.06},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{liujai_12,
|
||
author = {Liu, Jamie and Jaiyen, Ben and Veras, Richard and Mutlu, Onur},
|
||
booktitle = {Proceedings of the 39th Annual International Symposium on Computer Architecture},
|
||
title = {{RAIDR}: {R}etention-{A}ware {I}ntelligent {DRAM} {R}efresh},
|
||
isbn = {978-1-4503-1642-2},
|
||
location = {Portland, Oregon},
|
||
pages = {1--12},
|
||
publisher = {IEEE Computer Society},
|
||
series = {ISCA '12},
|
||
url = {http://dl.acm.org/citation.cfm?id=2337159.2337161},
|
||
acmid = {2337161},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.09},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{liuhem_17,
|
||
author = {Liu, Pei and Hemani, Ahmed and Paul, Kolin and Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
title = {3{D}-{S}tacked {M}any-{C}ore {A}rchitecture for {B}iological {S}equence {A}nalysis {P}roblems},
|
||
doi = {10.1007/s10766-017-0495-0},
|
||
issn = {1573-7640},
|
||
pages = {1--41},
|
||
url = {http://dx.doi.org/10.1007/s10766-017-0495-0},
|
||
abstract = {Sequence analysis plays extremely important role in bioinformatics, and most applications of which have compute intensive kernels consuming over 70{\%} of total execution time. By exploiting the compute intensive execution stages of popular sequence analysis applications, we present and evaluate a VLSI architecture with a focus on those that target at biological sequences directly, including pairwise sequence alignment, multiple sequence alignment, database search, and short read sequence mappings. Based on coarse grained reconfigurable array we propose the use of many-core and 3D-stacked technologies to gain further improvement over memory subsystem, which gives another order of magnitude speedup from high bandwidth and low access latency. We analyze our approach in terms of its throughput and efficiency for different application mappings. Initial experimental results are evaluated from a stripped down implementation in a commodity FPGA, and then we scale the results to estimate the performance of our architecture with 9 layers of {\$}{\$}70 {\backslash}hbox {\{} mm{\}}^{\{}2{\}}{\$}{\$} 70 mm 2 stacked wafers in 45-nm process. We demonstrate numerous estimated speedups better than corresponding existed hardware accelerator platforms for at least 40 times for the entire range of applications and datasets of interest. In comparison, the alternative FPGA based accelerators deliver only improvement for single application, while GPGPUs perform not well enough on accelerating program kernel with random memory access and integer addition/comparison operations.},
|
||
groups = {MJ:1},
|
||
journal = {International Journal of Parallel Programming},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2017},
|
||
}
|
||
|
||
@Article{liuhem_16,
|
||
author = {Liu, Pei and Hemani, Ahmed and Paul, Kolin and Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
title = {{A} {C}ustomized {M}any-{C}ore {H}ardware {A}cceleration {P}latform for {S}hort {R}ead {M}apping {P}roblems {U}sing {D}istributed {M}emory {I}nterface with 3{D}--{S}tacked {A}rchitecture},
|
||
doi = {10.1007/s11265-016-1204-8},
|
||
issn = {1939-8115},
|
||
pages = {1--15},
|
||
url = {http://dx.doi.org/10.1007/s11265-016-1204-8},
|
||
abstract = {Rapidly developing Next Generation Sequencing technologies produce huge amounts of short reads that consisting randomly fragmented DNA base pair strings. Assembling of those short reads poses a challenge on the mapping of reads to a reference genome in terms of both sensitivity and execution time. In this paper, we propose a customized many-core hardware acceleration platform for short read mapping problems based on hash-index method. The processing core is highly customized to suite both 2-hit string matching and banded Smith-Waterman sequence alignment operations, while distributed memory interface with 3D--stacked architecture provides high bandwidth and low access latency for highly customized dataset partitioning and memory access scheduling. Conformal with original BFAST program, our design provides an amazingly 45,012 times speedup over software approach for single-end short reads and 21,102 times for paired-end short reads, while also beats similar single FPGA solution for 1466 times in case of single end reads. Optimized seed generation gives much better sensitivity while the performance boost is still impressive.},
|
||
groups = {MJ:1},
|
||
journal = {Journal of Signal Processing Systems},
|
||
owner = {MJ},
|
||
timestamp = {2017-01-01},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{liupat_11,
|
||
author = {Liu, Song and Pattabiraman, Karthik and Moscibroda, Thomas and Zorn, Benjamin G.},
|
||
title = {{F}likker: {S}aving {DRAM} {R}efresh-power {T}hrough {C}ritical {D}ata {P}artitioning},
|
||
doi = {10.1145/1961296.1950391},
|
||
issn = {0362-1340},
|
||
number = {3},
|
||
pages = {213--224},
|
||
url = {http://doi.acm.org/10.1145/1961296.1950391},
|
||
volume = {46},
|
||
acmid = {1950391},
|
||
address = {New York, NY, USA},
|
||
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owner = {MJ},
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publisher = {ACM},
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title = {{U}sing {R}untime {R}everse {E}ngineering to {O}ptimize {DRAM} {R}efresh},
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title = {{RRAMS}pec: {A} {D}esign {S}pace {E}xploration {F}ramework for {H}igh {D}ensity {R}esistive {RAM}},
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title = {{U}sing {R}un-{T}ime {R}everse-{E}ngineering to {O}ptimize {DRAM} {R}efresh},
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title = {{S}ystem {S}imulation with gem5 and {S}ystem{C}: {T}he {K}eystone for {F}ull {I}nteroperability},
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@Article{mur_89,
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volume = {77},
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journal = {Proceedings of the IEEE},
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keywords = {Petri nets;logic programming;stochastic processes;Petri nets;behavioural properties;concurrent system model;high-level nets;logic programming;marked graphs;performance modeling;reachability criteria;stochastic nets;structural properties;subclasses;Books;Equations;History;Information processing;Logic programming;Mathematical model;Petri nets;Power system modeling;Stochastic processes;Stochastic systems},
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owner = {MJ},
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timestamp = {2016-12-04},
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year = {1989},
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@InProceedings{mut_17,
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author = {O. {Mutlu}},
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title = {{T}he {R}ow{H}ammer problem and other issues we may face as memory becomes denser},
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pages = {1116-1121},
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groups = {MJ:1},
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issn = {1558-1101},
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keywords = {DRAM chips;failure analysis;integrated circuit reliability;RowHammer Problem;malicious attack;system security;circuit-level failure mechanism;system security vulnerability;hardware failure mechanism;DRAM disturbance errors;circuit-level cell- to-cell interference;scaled memory technology;Google Project Zero;user-level programs;virtual machine;mobile device;malicious user-level application;memory reliability;memory security;Security;Failure analysis;Reliability;DRAM chips;Error correction codes;Virtual machining},
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year = {2017},
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@InProceedings{mutmos_08,
|
||
author = {Onur Mutlu and Thomas Moscibroda},
|
||
booktitle = {35th International Symposium on Computer Architecture (ISCA)},
|
||
title = {{P}arallelism-{A}ware {B}atch-{S}cheduling: {E}nhancing both {P}erformance and {F}airness of {S}hared {DRAM} {S}ystems},
|
||
publisher = {Association for Computing Machinery, Inc.},
|
||
url = {http://research.microsoft.com/apps/pubs/default.aspx?id=79626},
|
||
groups = {MJ:1},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2008},
|
||
}
|
||
|
||
@InProceedings{myt_16,
|
||
author = {Mytkowicz, T.},
|
||
booktitle = {ACM/IEEE Design Automation Conference (DAC), (Presentation Only)},
|
||
title = {{P}rogramming {U}ncertain {T}hings},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{naicho_14,
|
||
author = {Nair, Prashant J. and Chou, Chia-Chen and Qureshi, Moinuddin K.},
|
||
title = {{R}efresh {P}ausing in {DRAM} {M}emory {S}ystems},
|
||
doi = {10.1145/2579669},
|
||
issn = {1544-3566},
|
||
number = {1},
|
||
pages = {10:1--10:26},
|
||
url = {http://doi.acm.org/10.1145/2579669},
|
||
volume = {11},
|
||
acmid = {2579669},
|
||
address = {New York, NY, USA},
|
||
articleno = {10},
|
||
groups = {MJ:1},
|
||
issue_date = {February 2014},
|
||
journal = {ACM Trans. Archit. Code Optim.},
|
||
keywords = {Memory scheduling, memory controller},
|
||
month = feb,
|
||
numpages = {26},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2015.07.13},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{naikim_13,
|
||
author = {Nair, Prashant J. and Kim, Dae-Hyun and Qureshi, Moinuddin K.},
|
||
booktitle = {Proceedings of the 40th Annual International Symposium on Computer Architecture},
|
||
title = {{A}rch{S}hield: {A}rchitectural {F}ramework for {A}ssisting {DRAM} {S}caling by {T}olerating {H}igh {E}rror {R}ates},
|
||
doi = {10.1145/2485922.2485929},
|
||
isbn = {978-1-4503-2079-5},
|
||
location = {Tel-Aviv, Israel},
|
||
pages = {72--83},
|
||
publisher = {ACM},
|
||
series = {ISCA '13},
|
||
url = {http://doi.acm.org/10.1145/2485922.2485929},
|
||
acmid = {2485929},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {dynamic random access memory, error correction, hard faults},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2015.12.02},
|
||
year = {2013},
|
||
}
|
||
|
||
@Article{nairob_15,
|
||
author = {Nair, Prashant J. and Roberts, David A. and Qureshi, Moinuddin K.},
|
||
title = {{F}ault{S}im: {A} {F}ast, {C}onfigurable {M}emory-{R}eliability {S}imulator for {C}onventional and 3{D}-{S}tacked {S}ystems},
|
||
doi = {10.1145/2831234},
|
||
issn = {1544-3566},
|
||
number = {4},
|
||
pages = {44:1--44:24},
|
||
url = {http://doi.acm.org/10.1145/2831234},
|
||
volume = {12},
|
||
acmid = {2831234},
|
||
address = {New York, NY, USA},
|
||
articleno = {44},
|
||
groups = {MJ:1},
|
||
issue_date = {January 2016},
|
||
journal = {ACM Trans. Archit. Code Optim.},
|
||
keywords = {Error correcting codes, monte carlo simulation, reliability, stacked memory, through silicon vias},
|
||
month = dec,
|
||
numpages = {24},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2016-11-24},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{najwei_15,
|
||
author = {Naji, Omar and Weis, Christian and Jung, Matthias and Wehn, Norbert and Hansson, Andreas},
|
||
booktitle = {Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
|
||
title = {{A} {H}igh-{L}evel {DRAM} {T}iming, {P}ower and {A}rea {E}xploration {T}ool},
|
||
groups = {MJ:1},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2015},
|
||
}
|
||
|
||
@Electronic{nar_17,
|
||
author = {Narasimhan, Raj},
|
||
title = {{F}ulfilling {Q}uality {R}equirements for {M}emory in {A}utomotive {A}pplications},
|
||
organization = {Micron Technology, Inc.},
|
||
groups = {MJ:1},
|
||
howpublished = {http://www.arena-international.com/Journals/2017/04/04/y/l/g/1.-Raj-Narasimhan---Micron.pdf},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-03},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{natjun_20,
|
||
author = {Natale, Marco V. and Jung, Matthias and Kraft, Kira and Lauer, Frederik and Feldmann, Johannes and Sudarshan, Chirag and Weis, Christian and Krumke, Sven O. and Wehn, Norbert},
|
||
booktitle = {International Symposium on Memory Systems (MEMSYS 2020)},
|
||
title = {{E}fficient {G}eneration of {A}pplication {S}pecific {M}emory {C}ontrollers},
|
||
publisher = {ACM/IEEE},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2020-09-19},
|
||
year = {2020},
|
||
}
|
||
|
||
@Misc{neljus_16,
|
||
author = {Nelson, Patrick},
|
||
title = {{J}ust one autonomous car will use 4,000 {GB} of data/day},
|
||
howpublished = {https://www.networkworld.com/article/3147892/internet/one-autonomous-car-will-use-4000-gb-of-dataday.html},
|
||
groups = {MJ:1},
|
||
month = {December},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-04},
|
||
year = {2016},
|
||
}
|
||
|
||
@Book{nemwol_99,
|
||
author = {George Nemhauser and Laurence Wolsey},
|
||
title = {{I}nteger and {C}ombinatorial {O}ptimization},
|
||
publisher = {John Wiley \& Sons, Inc.},
|
||
series = {Series in discrete mathematics and optimization},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-23},
|
||
year = {1999},
|
||
}
|
||
|
||
@Article{ocelg_17,
|
||
author = {O'Connor, Rory V. and Elger, Peter and Clarke, Paul M.},
|
||
title = {{C}ontinuous software engineering — {A} microservices architecture perspective},
|
||
doi = {10.1002/smr.1866},
|
||
issn = {2047-7481},
|
||
note = {e1866 JSME-16-0193.R2},
|
||
number = {11},
|
||
pages = {e1866--n/a},
|
||
url = {http://dx.doi.org/10.1002/smr.1866},
|
||
volume = {29},
|
||
groups = {MJ:1},
|
||
journal = {Journal of Software: Evolution and Process},
|
||
keywords = {agile, continuous software engineering, microservices, situational factors, software development process},
|
||
owner = {MJ},
|
||
timestamp = {2020-02-09},
|
||
year = {2017},
|
||
}
|
||
|
||
@Book{olimor_16,
|
||
author = {Oliveira, Pablo and Morgenstern, Andreas and Jung, Matthias and Kuhn, Thomas and Wehn, Norbert},
|
||
title = {{S}oftware {A}rchitectures for {E}mbedded {S}oftware {S}ystems},
|
||
publisher = {Distance and Independent Studies Center (DISC) University of Kaiserslautern},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-06-30},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{onu_07,
|
||
author = {Onur Mutlu, Thomas Moscibroda},
|
||
booktitle = {40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)},
|
||
title = {{S}tall-{T}ime {F}air {M}emory {A}ccess {S}cheduling for {C}hip {M}ultiprocessors},
|
||
publisher = {IEEE},
|
||
url = {https://www.microsoft.com/en-us/research/publication/stall-time-fair-memory-access-scheduling-for-chip-multiprocessors/},
|
||
abstract = {DRAM memory is a major resource shared among cores in a chip multiprocessor (CMP) system. Memory requests from different threads can interfere with each other. Existing memory access scheduling techniques try to optimize the overall data throughput obtained from the DRAM and thus do not take into account inter-thread interference.
|
||
Therefore, different threads running together on the same chip can experience extremely different memory system performance: one thread can experience a severe slowdown or starvation while another is unfairly prioritized by the memory scheduler. This paper proposes a new memory access scheduler, called the Stall-Time Fair Memory scheduler (STFM), that provides quality of service to different threads sharing the DRAM memory system. The goal of the proposed scheduler is to “equalize” the DRAM-related slowdown experienced by each thread due to interference from other threads, without hurting overall system performance. As such, STFM takes into account inherent memory characteristics of each thread and does not unfairly penalize threads that use the DRAM system without interfering with other threads.
|
||
We show that STFM significantly reduces the unfairness in the DRAM system while also improving system throughput (i.e., weighted speedup of threads) on a wide variety of workloads and systems. For example, averaged over 32 different workloads running on an 8-core CMP, the ratio between the highest DRAM-related slowdown and the lowest DRAM-related slowdown reduces from 5.26X to 1.4X, while the average system throughput improves by 7.6%. We qualitatively and quantitatively compare STFM to one new and three previouslyproposed memory access scheduling algorithms, including network fair queueing. Our results show that STFM provides the best fairness, system throughput, and scalability.},
|
||
groups = {MJ:1},
|
||
month = {December},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-02},
|
||
year = {2007},
|
||
}
|
||
|
||
@InProceedings{oco_16,
|
||
author = {O’Connor, Ian},
|
||
booktitle = {1st Intl. Workshop on Emerging Memory Solutions, DATE Conference 2016, Dresden, Germany},
|
||
title = {{W}ill current memories be replaced by new emerging {NV} memories? {W}hen and which ones? {A}nd for which applications?},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-08-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{parlim_16,
|
||
author = {Kyungbae Park and Chulseung Lim and Donghyuk Yun and Sanghyeon Baeg},
|
||
title = {{E}xperiments and root cause analysis for active-precharge hammering fault in {DDR}3 {SDRAM} under 3x nm technology},
|
||
doi = {http://dx.doi.org/10.1016/j.microrel.2015.12.027},
|
||
issn = {0026-2714},
|
||
pages = {39 - 46},
|
||
url = {http://www.sciencedirect.com/science/article/pii/S0026271415302742},
|
||
volume = {57},
|
||
abstract = {Abstract This paper investigates the failure mechanism manifested in \{DDR3\} \{SDRAMs\} under 3 × nm technology. \{DRAM\} cells should retain the stored value if they are refreshed within the cell retention time of 64 ms at minimum. However the charge in a \{DRAM\} cell leaked faster, and the values of the stressed cells could not be retained with valid yet stressful hammered accesses to a row. An experiment of accelerated discharging by hammered accesses was duplicated by a \{SPICE\} simulation with a \{TCAD\} device model of a \{DRAM\} cell. Experiments with commercial \{DDR3\} discrete components from three major memory manufacturers were performed to confirm the validity of the \{SPICE\} simulation. The contributions of each in triggering and accelerating the failure mechanisms are investigated depending on the three test parameters—tRP, data pattern, and temperature—based on the experimental results. In the experiments, all commercial \{DDR3\} components failed much earlier than the specified limit of allowed accesses. In the worst condition, the failure in a normal cell of a component occurred at 200 K, which is 15.23% of the permitted cell retention time.},
|
||
groups = {MJ:1},
|
||
journal = {Microelectronics Reliability},
|
||
keywords = {Active-precharge hammering on a row fault},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-25},
|
||
year = {2016},
|
||
}
|
||
|
||
@InCollection{patben_05,
|
||
author = {Patel, K. and Benini, L. and Macii, Enrico and Poncino, Massimo},
|
||
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation},
|
||
title = {{E}nergy-{E}fficient {V}alue-{B}ased {S}elective {R}efresh for {E}mbedded {DRAM}s},
|
||
doi = {10.1007/11556930_48},
|
||
editor = {Paliouras, Vassilis and Vounckx, Johan and Verkest, Diederik},
|
||
isbn = {978-3-540-29013-1},
|
||
language = {English},
|
||
pages = {466-476},
|
||
publisher = {Springer Berlin Heidelberg},
|
||
series = {Lecture Notes in Computer Science},
|
||
url = {http://dx.doi.org/10.1007/11556930_48},
|
||
volume = {3728},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2005},
|
||
}
|
||
|
||
@InBook{patpol_12,
|
||
author = {Paterson, Kenneth G. and Polychroniadou, Antigoni and Sibborn, Dale L.},
|
||
booktitle = {Advances in Cryptology -- ASIACRYPT 2012: 18th International Conference on the Theory and Application of Cryptology and Information Security, Beijing, China, December 2-6, 2012. Proceedings},
|
||
title = {{A} {C}oding-{T}heoretic {A}pproach to {R}ecovering {N}oisy {RSA} {K}eys},
|
||
doi = {10.1007/978-3-642-34961-4_24},
|
||
isbn = {978-3-642-34961-4},
|
||
pages = {386--403},
|
||
publisher = {Springer Berlin Heidelberg},
|
||
url = {https://doi.org/10.1007/978-3-642-34961-4_24},
|
||
abstract = {Inspired by cold boot attacks, Heninger and Shacham (Crypto 2009) initiated the study of the problem of how to recover an RSA private key from a noisy version of that key. They gave an algorithm for the case where some bits of the private key are known with certainty. Their ideas were extended by Henecka, May and Meurer (Crypto 2010) to produce an algorithm that works when all the key bits are subject to error. In this paper, we bring a coding-theoretic viewpoint to bear on the problem of noisy RSA key recovery. This viewpoint allows us to cast the previous work as part of a more general framework. In turn, this enables us to explain why the previous algorithms do not solve the motivating cold boot problem, and to design a new algorithm that does (and more). In addition, we are able to use concepts and tools from coding theory -- channel capacity, list decoding algorithms, and random coding techniques -- to derive bounds on the performance of the previous and our new algorithm.},
|
||
address = {Berlin, Heidelberg},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-09-11},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{pat_04,
|
||
author = {Patterson, David A.},
|
||
title = {{L}atency {L}ags {B}andwith},
|
||
doi = {10.1145/1022594.1022596},
|
||
issn = {0001-0782},
|
||
number = {10},
|
||
pages = {71--75},
|
||
url = {http://doi.acm.org/10.1145/1022594.1022596},
|
||
volume = {47},
|
||
acmid = {1022596},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {October 2004},
|
||
journal = {Commun. ACM},
|
||
month = oct,
|
||
numpages = {5},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2018-05-03},
|
||
year = {2004},
|
||
}
|
||
|
||
@Misc{pawhybrid11,
|
||
author = {J. T. Pawlowski},
|
||
title = {{H}ybrid {M}emory {C}ube},
|
||
howpublished = {HotChips 23},
|
||
file = {pawhybrid11.pdf:pawhybrid11.pdf:PDF},
|
||
groups = {MJ:1},
|
||
month = {August},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.11},
|
||
year = {2011},
|
||
}
|
||
|
||
@Book{pet_81,
|
||
author = {Peterson, James Lyle},
|
||
title = {{P}etri {N}et {T}heory and the {M}odeling of {S}ystems},
|
||
isbn = {0136619835},
|
||
publisher = {Prentice Hall PTR},
|
||
address = {Upper Saddle River, NJ, USA},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-27},
|
||
year = {1981},
|
||
}
|
||
|
||
@Electronic{petwha_16,
|
||
author = {Petitet, A. and Whaley, R. C. and Dongarra, J. and Cleary, A.},
|
||
title = {{HPL} - {A} {P}ortable {I}mplementation of the {H}igh-{P}erformance {L}inpack {B}enchmark for {D}istributed-{M}emory {C}omputers},
|
||
url = {http://www.netlib.org/benchmark/hpl/},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@PhdThesis{pet_62,
|
||
author = {Carl Adam Petri},
|
||
title = {{K}ommunikation mit {A}utomaten},
|
||
language = {ger},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
school = {Universität Hamburg},
|
||
timestamp = {2016-12-04},
|
||
year = {1962},
|
||
}
|
||
|
||
@InProceedings{porxie_12,
|
||
author = {M. {Poremba} and Y. {Xie}},
|
||
booktitle = {2012 IEEE Computer Society Annual Symposium on VLSI},
|
||
title = {{NVM}ain: {A}n {A}rchitectural-{L}evel {M}ain {M}emory {S}imulator for {E}merging {N}on-volatile {M}emories},
|
||
doi = {10.1109/ISVLSI.2012.82},
|
||
pages = {392-397},
|
||
groups = {MJ:1},
|
||
issn = {2159-3469},
|
||
keywords = {circuit reliability;DRAM chips;memory architecture;NVMain;architectural-level main memory simulator;nonvolatile memories;DRAM-based main memory design;computer systems;NVM technologies;computer architecture;architectural-level simulator;main memory design;design space explorations;Nonvolatile memory;Random access memory;Delay;Integrated circuit modeling;Computational modeling;Organizations;emerging memory technology;memory architecture},
|
||
month = {Aug},
|
||
owner = {MJ},
|
||
timestamp = {2020-03-12},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{porzha_15,
|
||
author = {M. {Poremba} and T. {Zhang} and Y. {Xie}},
|
||
title = {{NVM}ain 2.0: {A} {U}ser-{F}riendly {M}emory {S}imulator to {M}odel ({N}on-){V}olatile {M}emory {S}ystems},
|
||
doi = {10.1109/LCA.2015.2402435},
|
||
issn = {2473-2575},
|
||
number = {2},
|
||
pages = {140-143},
|
||
volume = {14},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Computer Architecture Letters},
|
||
keywords = {cache storage;DRAM chips;memory architecture;phase change memories;user interfaces;NVMain 2.0;user-friendly memory simulator;nonvolatile memory system;flexible memory simulator;commodity DRAM;memory technology;die-stacked DRAM cache;STT-RAM;PCRAM;ReRAM;multilevel cells;DRAM memory systems;flexible user interface;Nonvolatile memory;Memory management;Computational modeling;Phase change random access memory;Computer architecture;Memory architecture, random access memory, nonvolatile memory, phase change memory, SDRAM},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2020-03-12},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{qurkim_15,
|
||
author = {Qureshi, Moinuddin K and Kim, Dae-Hyun and Khan, Samira and Nair, Prashant J and Mutlu, Onur},
|
||
title = {{AVATAR}: {A} {V}ariable-{R}etention-{T}ime ({VRT}) {A}ware {R}efresh for {DRAM} {S}ystems},
|
||
number = {4Gb},
|
||
pages = {20},
|
||
volume = {2},
|
||
groups = {MJ:1},
|
||
journal = {Memory},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{rahjay_15,
|
||
author = {Raha, Arnab and Jayakumar, Hrishikesh and Sutar, Soubhagya and Raghunathan, Vijay},
|
||
booktitle = {Proceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems},
|
||
title = {{Q}uality-aware {D}ata {A}llocation in {A}pproximate {DRAM}},
|
||
isbn = {978-1-4673-8320-2},
|
||
location = {Amsterdam, The Netherlands},
|
||
pages = {89--98},
|
||
publisher = {IEEE Press},
|
||
series = {CASES '15},
|
||
url = {http://dl.acm.org/citation.cfm?id=2830689.2830702},
|
||
acmid = {2830702},
|
||
address = {Piscataway, NJ, USA},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM power management, approximate computing, intrinsic application resilience, low power design},
|
||
numpages = {10},
|
||
owner = {MJ},
|
||
timestamp = {2015.10.26},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{rahsut_17,
|
||
author = {Arnab Raha and S. Sutar and H. Jayakumar and V. Raghunathan},
|
||
title = {{Q}uality {C}onfigurable {A}pproximate {DRAM}},
|
||
doi = {10.1109/TC.2016.2640296},
|
||
issn = {0018-9340},
|
||
number = {7},
|
||
pages = {1172-1187},
|
||
volume = {66},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {DRAM chips;fault tolerant computing;power aware computing;power consumption;resource allocation;storage management;Altera Stratix IV GX FPGA;Terasic TR4-230 development board;approximate computing;data allocation;error-resilient applications;inherent error tolerance;power consumption;power performance;quality configurable approximate DRAM system;substantial energy savings;Capacitors;Energy consumption;Integrated circuits;Power demand;Random access memory;Resilience;Resource management;DRAM;Low power design;approximate computing;approximate memory;approximate storage},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2017-09-11},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{rahhic_14,
|
||
author = {Rahmati, Amir and Hicks, Matthew and Holcomb, Daniel and Fu, Kevin},
|
||
booktitle = {Workshop on Approximate Computing Across the System Stack (WACAS)},
|
||
title = {{R}efreshing thoughts on {DRAM}: {P}ower saving vs. data integrity},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.12.02},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{rahhic_15,
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author = {Amir Rahmati and M. Hicks and D. E. Holcomb and K. Fu},
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||
booktitle = {2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA)},
|
||
title = {{P}robable cause: {T}he deanonymizing effects of approximate {DRAM}},
|
||
doi = {10.1145/2749469.2750419},
|
||
pages = {604-615},
|
||
groups = {MJ:1},
|
||
issn = {1063-6897},
|
||
keywords = {DRAM chips;security of data;DRAM chip;analog properties;approximate DRAM;approximate computing;approximate memory platform;approximate output;commodity system;computation accuracy;digital components;distance metric;end-to-end deanonymizing effects;error pattern;guard bands;image manipulation program;mathematical model;memory cell decay times;opportunistic relaxation;power consumption;probable cause threat model;system identifying fingerprint;two-orders-of-magnitude difference;Approximation algorithms;Computational modeling;Fingerprint recognition;Hardware;Random access memory;Tin;Writing},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2017-09-11},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{ram_06a,
|
||
author = {Ramanathan, R.M.},
|
||
title = {{I}ntel({R}) {M}ulti-{C}ore {P}rocessors {M}aking the {M}ove to {Q}uad-{C}ore and {B}eyond},
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||
groups = {MJ:1},
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||
journal = {Intel Corporation},
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||
owner = {MJ},
|
||
timestamp = {2016-06-05},
|
||
year = {2006},
|
||
}
|
||
|
||
@Electronic{ram_09,
|
||
author = {Rambus},
|
||
title = {{C}hallenges and {S}olutions for {F}uture {M}ain {M}emory},
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||
url = {\url{https://www.rambus.com/challenges-and-solutions-for-future-main-memory/}},
|
||
groups = {MJ:1},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2016-08-10},
|
||
year = {2009},
|
||
}
|
||
|
||
@InProceedings{redwal_17,
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author = {B. K. Reddy and M. J. Walker and D. Balsamo and S. Diestelhorst and B. M. Al-Hashimi and G. V. Merrett},
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||
booktitle = {2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)},
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||
title = {{E}mpirical {CPU} power modelling and estimation in the gem5 simulator},
|
||
doi = {10.1109/PATMOS.2017.8106988},
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||
pages = {1-8},
|
||
groups = {MJ:1},
|
||
keywords = {cache storage;microprocessor chips;multiprocessing systems;power aware computing;DVFS level;PMC;design space exploration;dynamic voltage and frequency scaling level;empirical CPU power modelling;full-system architectural simulator;gem5 simulated activity statistics;hardware PMC;integrated model;performance monitoring counters;power management approaches;power simulators;simulated quadcore ARM Cortex-A15;Data models;Hardware;Microarchitecture;Power demand;Power measurement;Timing;Tools},
|
||
month = {Sept},
|
||
owner = {MJ},
|
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timestamp = {2018-06-19},
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||
year = {2017},
|
||
}
|
||
|
||
@Conference{reikuc_13,
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author = {Dominik Reinhardt and Markus Kucera},
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booktitle = {Proceedings of the 3rd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,},
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title = {{D}omain {C}ontrolled {A}rchitecture - {A} {N}ew {A}pproach for {L}arge {S}cale {S}oftware {I}ntegrated {A}utomotive {S}ystems},
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doi = {10.5220/0004340702210226},
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isbn = {978-989-8565-43-3},
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organization = {INSTICC},
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pages = {221-226},
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publisher = {SciTePress},
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groups = {MJ:1},
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||
owner = {MJ},
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timestamp = {2018-04-25},
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year = {2013},
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||
}
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@InProceedings{reikuc_13a,
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author = {Reinhardt, Dominik and Kucera, Markus},
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booktitle = {Proceedings of the PECCS2013 - International Conference on Pervasive and Embedded Computing and Communication Systems},
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title = {{D}omain {C}ontrolled {A}rchitecture - {A} {N}ew {A}pproach for {L}arge {S}cale {S}oftware {I}ntegrated {A}utomotive {S}ystems},
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location = {Barcelona, Spain},
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groups = {MJ:1},
|
||
owner = {MJ},
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timestamp = {2020-02-09},
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||
year = {2013},
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}
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@InProceedings{rixdal_00,
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author = {Rixner, Scott and Dally, William J. and Kapasi, Ujval J. and Mattson, Peter and Owens, John D.},
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booktitle = {Proceedings of the 27th Annual International Symposium on Computer Architecture},
|
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title = {{M}emory {A}ccess {S}cheduling},
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||
doi = {10.1145/339647.339668},
|
||
isbn = {1-58113-232-8},
|
||
location = {Vancouver, British Columbia, Canada},
|
||
pages = {128--138},
|
||
publisher = {ACM},
|
||
series = {ISCA '00},
|
||
url = {http://doi.acm.org/10.1145/339647.339668},
|
||
acmid = {339668},
|
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address = {New York, NY, USA},
|
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groups = {MJ:1},
|
||
numpages = {11},
|
||
owner = {MJ},
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timestamp = {2015.01.20},
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year = {2000},
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}
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|
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@Article{roc_96,
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author = {Rockicki, Tomas},
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title = {{I}ndexing memory banks to maximize page mode hit percentage and minimize memory latency},
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groups = {MJ:1},
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journal = {Hewlett-Packard Laboratories Technical Report, HPL-96-95},
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owner = {MJ},
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timestamp = {2016-04-11},
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year = {1996},
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}
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@Article{rodhem_11,
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author = {Rodrigues, A. F. and Hemmert, K. S. and Barrett, B. W. and Kersey, C. and Oldfield, R. and Weston, M. and Risen, R. and Cook, J. and Rosenfeld, P. and CooperBalls, E. and Jacob, B.},
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title = {{T}he {S}tructural {S}imulation {T}oolkit},
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doi = {10.1145/1964218.1964225},
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issn = {0163-5999},
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number = {4},
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pages = {37--42},
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url = {http://doi.acm.org/10.1145/1964218.1964225},
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volume = {38},
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acmid = {1964225},
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address = {New York, NY, USA},
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groups = {MJ:1},
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||
issue_date = {March 2011},
|
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journal = {SIGMETRICS Perform. Eval. Rev.},
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keywords = {SST, architecture, performance analysis, simulation},
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month = mar,
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numpages = {6},
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owner = {MJ},
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||
publisher = {ACM},
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timestamp = {2017-06-13},
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year = {2011},
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}
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|
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@Article{roscoo_11,
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author = {Rosenfeld, Paul and Cooper-Balis, Elliot and Jacob, Bruce},
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title = {{DRAMS}im2: {A} {C}ycle {A}ccurate {M}emory {S}ystem {S}imulator},
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doi = {10.1109/L-CA.2011.4},
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issn = {1556-6056},
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number = {1},
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pages = {16-19},
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volume = {10},
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groups = {MJ:1},
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journal = {Computer Architecture Letters},
|
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keywords = {DRAM chips;memory architecture;memory cards;DDR2/3 memory system model;DRAMSim2 simulation;DRAMSim2 timing;Verilog model;cycle accurate memory system simulator;trace-based simulation;visualization tool;Computational modeling;Driver circuits;Hardware design languages;Load modeling;Object oriented modeling;Random access memory;Timing;DRAM;Primary memory;Simulation},
|
||
month = {Jan},
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owner = {MJ},
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timestamp = {2015.02.17},
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year = {2011},
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}
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||
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||
@Misc{rospython14,
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author = {van Rossum, Guido and Kuchling, A. M. and L. Drake Jr., Fred},
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title = {{P}ython {R}eference {M}anual},
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howpublished = {\url{https://www.python.org}},
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groups = {MJ:1},
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month = {October},
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owner = {MJ},
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timestamp = {2015.02.23},
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year = {2014, Last Access: 23.02.2015},
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}
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@Misc{rus_99,
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author = {John Rushby},
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title = {{P}artitioning in {A}vionics {A}rchitectures: {R}equirements, {M}echanisms, and {A}ssurance},
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groups = {MJ:1},
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owner = {MJ},
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timestamp = {2018-05-03},
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year = {1999},
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}
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@InProceedings{rusret_03,
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author = {C. {Rust} and A. {Rettberg} and K. {Gossens}},
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booktitle = {SMC'03 Conference Proceedings. 2003 IEEE International Conference on Systems, Man and Cybernetics. Conference Theme - System Security and Assurance (Cat. No.03CH37483)},
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title = {{F}rom high-level {P}etri nets to {S}ystem{C}},
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doi = {10.1109/ICSMC.2003.1244548},
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pages = {1032-1038 vol.2},
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volume = {2},
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groups = {MJ:1},
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issn = {1062-922X},
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keywords = {Petri nets;distributed programming;C language;embedded systems;program compilers;high level Petri nets;standard SystemC language;Petri net based design;distributed embedded real-time systems;Petri net components;partitions;single transition execution;conflicting transitions;transition delay realization;code generation;Petri nets;Real time systems;Embedded system;Hardware design languages;Vehicles;Performance analysis;Delay;Design methodology;Process design;Microcontrollers},
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month = {Oct},
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||
owner = {MJ},
|
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timestamp = {2019-06-04},
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||
year = {2003},
|
||
}
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||
|
||
@PhdThesis{Phdsadri14,
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author = {Mohammadsadegh Sadri},
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title = {{T}emperature {V}ariation {A}ware {E}nergy {O}ptimization in {H}eterogeneous {MPS}o{C}s},
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url = {http://amsdottorato.unibo.it/6406/},
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groups = {MJ:1},
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keywords = {Multi-scale Thermal Analysis, RT and Gate Level, Temperature Variation, Hardware Acceleration, Heterogeneous Architecture},
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month = {Maggio},
|
||
owner = {MJ},
|
||
school = {alma},
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timestamp = {2016-11-16},
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year = {2014},
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}
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@InProceedings{sadjun_14,
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author = {Sadri, MohammadSadegh and Jung, Matthias and Weis, Christian and Wehn, Norbert and Benini, Luca},
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booktitle = {Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014},
|
||
title = {{E}nergy {O}ptimization in 3{D} {MPS}o{C}s with {W}ide-{I}/{O} {DRAM} {U}sing {T}emperature {V}ariation {A}ware {B}ank-{W}ise {R}efresh},
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doi = {10.7873/DATE2014.294},
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pages = {1-4},
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file = {sadjun_14.pdf:sadjun_14.pdf:PDF},
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groups = {MJ:1},
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keywords = {AGWehn},
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month = {March},
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owner = {MJ},
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timestamp = {2017-07-05},
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year = {2014},
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}
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@InProceedings{sahsat_16,
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author = {D. {Sahoo} and M. {Satpathy}},
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booktitle = {2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)},
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||
title = {{MS}im{DRAM}: {F}ormal {M}odel {D}riven {D}evelopment of a {DRAM} {S}imulator},
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doi = {10.1109/VLSID.2016.88},
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pages = {597-598},
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groups = {MJ:1},
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issn = {2380-6923},
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keywords = {DRAM chips;finite state machines;MSimDRAM;formal model driven development;DRAM simulator;DRAM controller requirements;DRAM-C requirements;architectural design;interacting state machines;rigorous verification;truncated simulator;agent-interaction;Random access memory;Timing;Control systems;Databases;Model checking;Radiation detectors;Jacobian matrices;Memory Controller;Hardware simulation;Formal Modeling},
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month = {Jan},
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owner = {MJ},
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timestamp = {2019-06-04},
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year = {2016},
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}
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@InProceedings{samdie_11,
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author = {Sampson, Adrian and Dietl, Werner and Fortuna, Emily and Gnanapragasam, Danushen and Ceze, Luis and Grossman, Dan},
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booktitle = {Proceedings of the 32Nd ACM SIGPLAN Conference on Programming Language Design and Implementation},
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title = {{E}ner{J}: {A}pproximate {D}ata {T}ypes for {S}afe and {G}eneral {L}ow-power {C}omputation},
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doi = {10.1145/1993498.1993518},
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isbn = {978-1-4503-0663-8},
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location = {San Jose, California, USA},
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pages = {164--174},
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||
publisher = {ACM},
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||
series = {PLDI '11},
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||
url = {http://doi.acm.org/10.1145/1993498.1993518},
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acmid = {1993518},
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address = {New York, NY, USA},
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groups = {MJ:1},
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keywords = {accuracy-aware computing, critical data, energy, power-aware computing, soft errors},
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numpages = {11},
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||
owner = {MJ},
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timestamp = {2015.10.28},
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||
year = {2011},
|
||
}
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||
|
||
@Misc{samm471b2874eh109,
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||
author = {Samsung},
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title = {{M}471{B}2874{EH}1-{CF}8 {DDR}3 1{GB} 533{MH}z},
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groups = {MJ:1},
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owner = {MJ},
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timestamp = {2015.10.29},
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year = {2009},
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}
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@InProceedings{sansch_13,
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author = {Sanders, Peter and Schulz, Christian},
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booktitle = {Proceedings of the 12th International Symposium on Experimental Algorithms (SEA'13)},
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title = {{Think Locally, Act Globally: Highly Balanced Graph Partitioning}},
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pages = {164--175},
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publisher = {Springer},
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series = {LNCS},
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volume = {7933},
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groups = {MJ:1},
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owner = {MJ},
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timestamp = {2016-04-13},
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year = {2013},
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}
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@InProceedings{sanviv_13,
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author = {Santos, C. and Vivet, P. and Dutoit, D. and Garrault, P. and Peltier, N. and Reis, R.},
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booktitle = {3D Systems Integration Conference (3DIC), 2013 IEEE International},
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title = {{S}ystem-level thermal modeling for 3{D} circuits: {C}haracterization with a 65nm memory-on-logic circuit},
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doi = {10.1109/3DIC.2013.6702379},
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groups = {MJ:1},
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keywords = {integrated circuit modelling;integrated memory circuits;logic circuits;thermal analysis;three-dimensional integrated circuits;transient response;3D integrated circuits;TSV;formal reduction;integrated thermal sensors;material homogenization;memory-on-logic circuit;power dissipation hot spots;size 65 nm;steady-state analysis;system level thermal modeling;thermal analysis;thermal transient response;through silicon via;transient analysis;vertically integrated circuits;Heating;Integrated circuit modeling;Materials;Temperature measurement;Temperature sensors;Three-dimensional displays;3DIC;CTM;characterization;material homogenization;temperature;thermal modeling},
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month = {Oct},
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owner = {MJ},
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timestamp = {2015.04.13},
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year = {2013},
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}
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@InProceedings{sarsri_16,
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booktitle = {ACM/IEEE Design Automation Conference (DAC)},
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title = {{C}ross-{L}ayer {A}pproximations for {N}euromorphic {C}omputing: {F}rom {D}evices to {C}ircuits and {S}ystems},
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groups = {MJ:1},
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owner = {MJ},
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timestamp = {2016-04-05},
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year = {2016},
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}
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@Article{schhei_13,
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author = {Schmoll, Florian and Heinig, Andreas and Marwedel, Peter and Engel, Michael},
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title = {{I}mproving the {F}ault {R}esilience of an {H}.264 {D}ecoder {U}sing {S}tatic {A}nalysis {M}ethods},
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doi = {10.1145/2536747.2536753},
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issn = {1539-9087},
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number = {1s},
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pages = {31:1--31:27},
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url = {http://doi.acm.org/10.1145/2536747.2536753},
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volume = {13},
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acmid = {2536753},
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address = {New York, NY, USA},
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articleno = {31},
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issue_date = {November 2013},
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journal = {ACM Trans. Embed. Comput. Syst.},
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keywords = {Flexible error handling, annotations, application knowledge, delayed error handling, embedded systems, error classification, static analysis, transient faults, type qualifier},
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month = dec,
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numpages = {27},
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owner = {MJ},
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publisher = {ACM},
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timestamp = {2015.07.08},
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year = {2013},
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}
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@Article{schtra_13,
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author = {Schneider, Daniel and Trapp, Mario},
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title = {{C}onditional {S}afety {C}ertification of {O}pen {A}daptive {S}ystems},
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doi = {10.1145/2491465.2491467},
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issn = {1556-4665},
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number = {2},
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pages = {8:1--8:20},
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url = {http://doi.acm.org/10.1145/2491465.2491467},
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volume = {8},
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acmid = {2491467},
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issue_date = {July 2013},
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journal = {ACM Trans. Auton. Adapt. Syst.},
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keywords = {Adaptive systems, conditional certification, open systems, safety},
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month = jul,
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numpages = {20},
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owner = {MJ},
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publisher = {ACM},
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timestamp = {2019-01-02},
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year = {2013},
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}
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@InProceedings{schpin_09,
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author = {Bianca Schroeder and Eduardo Pinheiro and Wolf-Dietrich Weber},
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booktitle = {SIGMETRICS},
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title = {{DRAM} {E}rrors in the {W}ild: {A} {L}arge-{S}cale {F}ield {S}tudy},
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groups = {MJ:1},
|
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owner = {MJ},
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timestamp = {2018-05-03},
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year = {2009},
|
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}
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|
||
@Misc{sea_15,
|
||
author = {Mark Seaborn},
|
||
title = {{H}ow physical addresses map to rows and banks in {DRAM}},
|
||
howpublished = {\url{http://lackingrhoticity.blogspot.de/2015/05/how-physical-addresses-map-to-rows-and-banks.html}},
|
||
groups = {MJ:1},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-20},
|
||
year = {2015},
|
||
}
|
||
|
||
@Misc{seadul_15,
|
||
author = {Seaborn, Mark and Dullien, Thomas},
|
||
title = {{E}xploiting the {DRAM} rowhammer bug to gain kernel privileges},
|
||
howpublished = {\url{http://googleprojectzero.blogspot.de/2015/03/exploiting-dram-rowhammer-bug-to-gain.html}},
|
||
groups = {MJ:1},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2016-03-23},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{sesmul_15,
|
||
author = {Seshadri, Vivek and Mullins, Thomas and Boroumand, Amirali and Mutlu, Onur and Gibbons, Phillip B. and Kozuch, Michael A. and Mowry, Todd C.},
|
||
booktitle = {Proceedings of the 48th International Symposium on Microarchitecture},
|
||
title = {{G}ather-scatter {DRAM}: {I}n-{DRAM} {A}ddress {T}ranslation to {I}mprove the {S}patial {L}ocality of {N}on-unit {S}trided {A}ccesses},
|
||
doi = {10.1145/2830772.2830820},
|
||
isbn = {978-1-4503-4034-2},
|
||
location = {Waikiki, Hawaii},
|
||
pages = {267--280},
|
||
publisher = {ACM},
|
||
series = {MICRO-48},
|
||
url = {http://doi.acm.org/10.1145/2830772.2830820},
|
||
acmid = {2830820},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM, SIMD, caches, energy, in-memory databases, memory bandwidth, performance, strided accesses},
|
||
numpages = {14},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{shahaf_16,
|
||
author = {Shafique, M. and Hafiz, R. and Rehman, S. and El-Harouni, W. and Henkel, J.},
|
||
booktitle = {ACM/IEEE Design Automation Conference (DAC)},
|
||
title = {{C}ross-{L}ayer {A}pproximate {C}omputing: {F}rom {L}ogic to {A}rchitectures},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Book{sha_14,
|
||
author = {Shamieh, Cathleen},
|
||
title = {{C}ontinuous {E}ngineering for {D}ummies},
|
||
isbn = {3319112821, 9783319112824},
|
||
publisher = {John Wiley \& Sons, Inc.},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2020-02-09},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{shadav_05,
|
||
author = {Shao, Jun and Davis, Brian T.},
|
||
booktitle = {Proceedings of the 2005 Workshop on Software and Compilers for Embedded Systems},
|
||
title = {{T}he {B}it-reversal {SDRAM} {A}ddress {M}apping},
|
||
doi = {10.1145/1140389.1140396},
|
||
isbn = {1-59593-207-0},
|
||
location = {Dallas, Texas, USA},
|
||
pages = {62--71},
|
||
publisher = {ACM},
|
||
series = {SCOPES '05},
|
||
url = {http://doi.acm.org/10.1145/1140389.1140396},
|
||
acmid = {1140396},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {SDRAM, address mapping, memory controller},
|
||
numpages = {10},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-11},
|
||
year = {2005},
|
||
}
|
||
|
||
@Misc{shanvidia18,
|
||
author = {Shapiro, Danny},
|
||
title = {{NVIDIA} {DRIVE} {X}avier, {W}orld's {M}ost {P}owerful {S}o{C}, {B}rings {D}ramatic {N}ew {AI} {C}apabilities},
|
||
url = {https://blogs.nvidia.com/blog/2018/01/07/drive-xavier-processor/},
|
||
groups = {MJ:1},
|
||
month = {January},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-03},
|
||
year = {2018},
|
||
}
|
||
|
||
@Article{shitsa_12,
|
||
author = {Shieh, M.Z. and Tsai, S.C. and Yang, M-C.},
|
||
title = {{O}n the {I}napproximability of {M}aximum {I}ntersection {P}roblems},
|
||
number = {19},
|
||
pages = {723--727},
|
||
volume = {112},
|
||
groups = {MJ:1},
|
||
journal = {Information Processing Letters},
|
||
owner = {MJ},
|
||
timestamp = {2019-02-25},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{shicho_16,
|
||
author = {W. Shin and J. Choi and J. Jang and J. Suh and Y. Moon and Y. Kwon and L. S. Kim},
|
||
title = {{DRAM}-{L}atency {O}ptimization {I}nspired by {R}elationship between {R}ow-{A}ccess {T}ime and {R}efresh {T}iming},
|
||
doi = {10.1109/TC.2015.2512863},
|
||
issn = {0018-9340},
|
||
number = {10},
|
||
pages = {3027-3040},
|
||
volume = {65},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computers},
|
||
keywords = {DRAM chips;circuit simulation;electric charge;timing;DRAM cell capacitors;DRAM latency optimization;DRAM row-access latency;DRAM structure;DRAM vendors;NUAT-1;NUAT-2;circuit-level simulations;computing systems;electric charge variation;nonuniform access time;refresh timing;row-access time;system-level simulations;Capacitors;DRAM;Decoding;Memory management;Random access memory;Transistors;DRAM;DRAM-latency;memory controller;non-uniform access time (NUAT);refresh},
|
||
month = {Oct},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{shiyan_14,
|
||
author = {Shin, Wongyu and Yang, Jeongmin and Choi, Jungwhan and Kim, Lee-Sup},
|
||
booktitle = {2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)},
|
||
title = {{NUAT}: {A} non-uniform access time memory controller},
|
||
organization = {IEEE},
|
||
pages = {464--475},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{sonsam_16,
|
||
author = {Y. Song and K. Samadi and B. Lin},
|
||
booktitle = {2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC)},
|
||
title = {{S}ingle-tier virtual queuing: {A}n efficacious memory controller architecture for {MPS}o{C}s with multiple realtime cores},
|
||
doi = {10.1145/2897937.2898093},
|
||
pages = {1-6},
|
||
groups = {MJ:1},
|
||
keywords = {memory architecture;microprocessor chips;multiprocessing systems;performance evaluation;processor scheduling;queueing theory;system-on-chip;CPU;QoS;STVQ memory controller;efficacious memory controller architecture;heterogeneous MPSoC;memory interference;multiple realtime cores;scheduling policies;single-tier transaction queues;single-tier virtual queuing;system performance;two-tier queuing system;Bandwidth;Delays;Graphics processing units;Memory management;Quality of service;Random access memory;Scheduling},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-02},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{srivin_10,
|
||
author = {Sridhar, A. and Vincenzi, A. and Ruggiero, M. and Brunschwiler, Thomas and Atienza, D.},
|
||
booktitle = {Proc. of ICCAD 2010},
|
||
title = {3{D}-{ICE}: {F}ast compact transient thermal modeling for 3{D} {IC}s with inter-tier liquid cooling},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.20},
|
||
year = {2010},
|
||
}
|
||
|
||
@Article{srideb_15,
|
||
author = {Sridharan, Vilas and DeBardeleben, Nathan and Blanchard, Sean and Ferreira, Kurt B. and Stearley, Jon and Shalf, John and Gurumurthi, Sudhanva},
|
||
title = {{M}emory {E}rrors in {M}odern {S}ystems: {T}he {G}ood, {T}he {B}ad, and {T}he {U}gly},
|
||
doi = {10.1145/2786763.2694348},
|
||
issn = {0163-5964},
|
||
number = {1},
|
||
pages = {297--310},
|
||
url = {http://doi.acm.org/10.1145/2786763.2694348},
|
||
volume = {43},
|
||
acmid = {2694348},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {March 2015},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
keywords = {field studies, large-scale systems, reliability},
|
||
month = mar,
|
||
numpages = {14},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2018-05-03},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{srilib_12,
|
||
author = {V. Sridharan and D. Liberty},
|
||
booktitle = {High Performance Computing, Networking, Storage and Analysis (SC), 2012 International Conference for},
|
||
title = {{A} study of {DRAM} failures in the field},
|
||
doi = {10.1109/SC.2012.13},
|
||
pages = {1-11},
|
||
groups = {MJ:1},
|
||
issn = {2167-4329},
|
||
keywords = {DRAM chips;error correction codes;performance evaluation;system recovery;DRAM array;DRAM devices;DRAM errors;DRAM failures;DRAM subsystems;ECC;board level circuitry;dynamic random access memory;error-correcting codes;hardware scrubber;high-performance computing cluster;memory storage;node failure rate;shared internal circuitry;Circuit faults;Error analysis;Error correction codes;Hardware;Random access memory;Reliability;Transient analysis;DRAM;hard error;memory;reliability;single-event upset;soft error},
|
||
month = {Nov},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-03},
|
||
year = {2012},
|
||
}
|
||
|
||
@InProceedings{srikan_04,
|
||
author = {Srinivasan, Sudarshan M and Kandula, Srikanth and Andrews, Christopher R and Zhou, Yuanyuan and others},
|
||
booktitle = {USENIX Annual Technical Conference, General Track},
|
||
title = {{F}lashback: {A} lightweight extension for rollback and deterministic replay for software debugging},
|
||
organization = {Boston, MA, USA},
|
||
pages = {29--44},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-08},
|
||
year = {2004},
|
||
}
|
||
|
||
@Article{stasud_20,
|
||
author = {Stathis, Dimitrios and Sudarshan, Chirag and Yang, Yu and Jung, Matthias and Weis, Christian and Hemani, Ahmed and Lansner, Anders and Wehn, Norbert},
|
||
title = {e{B}rain{II}: a 3 k{W} {R}ealtime {C}ustom 3{D} {DRAM} {I}ntegrated {ASIC} {I}mplementation of a {B}iologically {P}lausible {M}odel of a {H}uman {S}cale {C}ortex},
|
||
doi = {10.1007/s11265-020-01562-x},
|
||
issn = {1939-8115},
|
||
url = {https://doi.org/10.1007/s11265-020-01562-x},
|
||
abstract = {The Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological brains. The biologically plausible spiking brain models, e.g., cortex, basal ganglia, and amygdala, have a greater potential to achieve biological brain like cognitive capabilities. Bayesian Confidence Propagation Neural Network (BCPNN) is a biologically plausible spiking model of the cortex. A human-scale model of BCPNN in real-time requires 162 TFlop/s, 50 TBs of synaptic weight storage to be accessed with a bandwidth of 200 TBs. The spiking bandwidth is relatively modest at 250 GBs/s. A hand-optimized implementation of rodent scale BCPNN has been done on Tesla K80 GPUs require 3 kWs, we extrapolate from that a human scale network will require 3 MWs. These power numbers rule out such implementations for field deployment as cognition engines in embedded systems.},
|
||
day = {07},
|
||
groups = {MJ:1},
|
||
journal = {Journal of Signal Processing Systems},
|
||
month = {Jul},
|
||
owner = {MJ},
|
||
timestamp = {2020-09-19},
|
||
year = {2020},
|
||
}
|
||
|
||
@InProceedings{stabri_11,
|
||
author = {S. Stattelmann and O. Bringmann and W. Rosenstiel},
|
||
booktitle = {2011 Design, Automation Test in Europe},
|
||
title = {{F}ast and accurate resource conflict simulation for performance analysis of multi-core systems},
|
||
doi = {10.1109/DATE.2011.5763044},
|
||
pages = {1-6},
|
||
groups = {MJ:1},
|
||
issn = {1558-1101},
|
||
keywords = {digital simulation;multiprocessing systems;optimisation;parallel programming;performance evaluation;program compilers;resource conflict simulation;performance analysis;multicore systems;SystemC based simulation;parallel software components;source code;low level timing properties;compiler optimizations;SystemC TLM 2.0 standard;Synchronization;Binary codes;Analytical models;Kernel;Predictive models;System analysis and design;Timing;Modeling;Software performance},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-13},
|
||
year = {2011},
|
||
}
|
||
|
||
@InProceedings{stamen_17,
|
||
author = {Giulia Stazi and F. Menichelli and A. Mastrandrea and M. Olivieri},
|
||
booktitle = {2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)},
|
||
title = {{I}ntroducing approximate memory support in {L}inux {K}ernel},
|
||
doi = {10.1109/PRIME.2017.7974116},
|
||
pages = {97-100},
|
||
groups = {MJ:1},
|
||
keywords = {Linux;operating system kernels;paged storage;Linux operating system kernel;OS level;allocation request management;approximate memory;approximate memory banks;approximate memory management;approximate physical memories;controlled probability;exact physical memories;fallback allocation policies;memory cells;memory fault probability;page pool management;read/write faults;Approximate computing;Hardware;Kernel;Linux;Memory management;Random access memory;Resource management},
|
||
month = {June},
|
||
owner = {MJ},
|
||
timestamp = {2017-09-11},
|
||
year = {2017},
|
||
}
|
||
|
||
@Article{stehwa_15,
|
||
author = {Stefanovici, Ioan and Hwang, Andy and Schroeder, Bianca},
|
||
title = {{DRAM}’s {D}amning {D}efects - and {H}ow {T}hey {C}ripple {C}omputers},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Spectrum},
|
||
month = {November},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-03},
|
||
year = {2015},
|
||
}
|
||
|
||
@Article{stejun_22,
|
||
author = {Steiner, Lukas and Jung, Matthias and Prado, Felipe and Bykov, Kyrill and Wehn, Norbert},
|
||
date = {2022},
|
||
journaltitle = {Springer International Journal of Parallel Programming (IJPP)},
|
||
title = {{DRAMS}ys4.0: {A}n {O}pen-{S}ource {S}imulation {F}ramework for {I}n-{D}epth {DRAM} {A}nalyses},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2022-03-31},
|
||
year = {2022},
|
||
}
|
||
|
||
@InProceedings{stejun_20,
|
||
author = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kyrill and Wehn, Norbert},
|
||
booktitle = {International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS)},
|
||
title = {{DRAMS}ys4.0: {A} {F}ast and {C}ycle-{A}ccurate {S}ystem{C}/{TLM}-{B}ased {DRAM} {S}imulator},
|
||
publisher = {Springer},
|
||
groups = {MJ:1},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2020-07-14},
|
||
year = {2020},
|
||
}
|
||
|
||
@InProceedings{stejun_21,
|
||
author = {Steiner, Lukas and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {IEEE/VDE Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen MBMV},
|
||
title = {{E}xploration of {DDR}5 with the {O}pen {S}ource {S}imulator {DRAMS}ys},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2021-02-28},
|
||
year = {2021},
|
||
}
|
||
|
||
@InProceedings{stekra_21,
|
||
author = {Steiner, Lukas and Kraft, Kira and Uecker, Denis and Jung, Matthias and Huonker, Michael and Wehn, Norbert},
|
||
booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021)},
|
||
title = {{A}n {LPDDR}4 {S}afety {M}odel for {A}utomotive {A}pplications},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2021-10-07},
|
||
year = {2021},
|
||
}
|
||
|
||
@Misc{crazy_17,
|
||
author = {Jack Stewart},
|
||
title = {{Self-Driving Cars use Crazy Amounts of Power, and it's Becoming a Problem}},
|
||
howpublished = {https://www.wired.com/story/self-driving-cars-power-consumption-nvidia-chip/},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2018-07-27},
|
||
year = {2018},
|
||
}
|
||
|
||
@InProceedings{stukas_10,
|
||
author = {Stuecheli, J. and Kaseridis, D. and Hunter, H.C. and John, L.K.},
|
||
booktitle = {Microarchitecture (MICRO), 2010 43rd Annual IEEE/ACM International Symposium on},
|
||
title = {{E}lastic {R}efresh: {T}echniques to {M}itigate {R}efresh {P}enalties in {H}igh {D}ensity {M}emory},
|
||
doi = {10.1109/MICRO.2010.22},
|
||
pages = {375-384},
|
||
groups = {MJ:1},
|
||
issn = {1072-4451},
|
||
keywords = {DRAM chips;multiprocessing systems;DRAM device;Elastic Refresh;GEMS;JEDEC DDRx SDRAM specification;SIMICS tool-set;dynamically reconfigurable predictive mechanism;execution stream;high density memory;refresh penalty mitigation;single chip many-core processor},
|
||
month = {Dec},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.13},
|
||
year = {2010},
|
||
}
|
||
|
||
@InProceedings{subses_13,
|
||
author = {Subramanian, Lavanya and Seshadri, Vivek and Kim, Yoongu and Jaiyen, Ben and Mutlu, Onur},
|
||
booktitle = {Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)},
|
||
title = {{MISE}: {P}roviding {P}erformance {P}redictability and {I}mproving {F}airness in {S}hared {M}ain {M}emory {S}ystems},
|
||
doi = {10.1109/HPCA.2013.6522356},
|
||
isbn = {978-1-4673-5585-8},
|
||
pages = {639--650},
|
||
publisher = {IEEE Computer Society},
|
||
series = {HPCA '13},
|
||
url = {http://dx.doi.org/10.1109/HPCA.2013.6522356},
|
||
acmid = {2495485},
|
||
address = {Washington, DC, USA},
|
||
groups = {MJ:1},
|
||
numpages = {12},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-02},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{sudlap_19,
|
||
author = {Sudarshan, Chirag and Lappas, Jan and Ghaffar, Muhammad Mohsin and Rybalkin, Vladimir and Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
|
||
title = {{NNDRAM}: {A} {D}eep {I}n-{DRAM} {C}omputing {A}rchitecture for {N}eural {N}etwork {P}rocessing},
|
||
groups = {MJ:1},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2019-04-26},
|
||
year = {2019},
|
||
}
|
||
|
||
@InProceedings{sudlap_19a,
|
||
author = {Sudarshan, Chirag and Lappas, Jan and Weis, Christian and Mathew, Deepak M. and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
|
||
title = {{A} {L}ean, {L}ow {P}ower, {L}ow {L}atency {DRAM} {M}emory {C}ontroller for {T}ransprecision {C}omputing},
|
||
editor = {Pnevmatikatos, Dionisios N. and Pelcat, Maxime and Jung, Matthias},
|
||
isbn = {978-3-030-27562-4},
|
||
pages = {429--441},
|
||
publisher = {Springer International Publishing},
|
||
abstract = {Energy consumption is one of the major challenges for the advanced System on Chips (SoC). This is addressed by adopting heterogeneous and approximate computing techniques. One of the recent evolution in this context is transprecision computing paradigm. The idea of the transprecision computing is to consume adequate amount of energy for each operation by performing dynamic precision reduction. The impact of the memory subsystem plays a crucial role in such systems. Hence, the energy efficiency of a transprecision system can be further optimized by tailoring the memory subsystem to the transprecision computing. In this work, we present a lean, low power, low latency memory controller that is appropriate for transprecision methodology. The memory controller consumes an average power of 129.33Â mW at a frequency of 500Â MHz and has a total area of 4.71Â mm2 for UMC 65Â nm process.},
|
||
address = {Cham},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-08-12},
|
||
year = {2019},
|
||
}
|
||
|
||
@Article{sudsol_22,
|
||
author = {Sudarshan, Chirag and Soliman, Taha and Lappas, Jan and Weis, Christian and Sadi, Mohammad H. and Jung, Matthias and Guntoro, Andre and Wehn, Norbert},
|
||
date = {2022},
|
||
journaltitle = {IEEE Journal on Emerging and Selected Topics in Circuits and Systems},
|
||
title = {{A} {W}eighted {C}urrent {S}ummation based {M}ixed {S}ignal {DRAM}-{PIM} {A}rchitecture for {D}eep {N}eural {N}etwork {I}nference},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2022-03-31},
|
||
year = {2022},
|
||
}
|
||
|
||
@InProceedings{sudsol_21,
|
||
author = {Sudarshan, Chirag and Soliman, Taha and de la Parra, C. and Weis, Christian and Ecco, Leonardo and Jung, Matthias and Wehn, Norbert and Guntoro, Andre},
|
||
booktitle = {26th Asia and South Pacific Design Automation Conference (ASP-DAC 2021)},
|
||
title = {{A} {N}ovel {DRAM}-{B}ased {P}rocess-in-{M}emory {A}rchitecture and its {I}mplementation for {CNN}s},
|
||
groups = {MJ:1},
|
||
month = {Januar},
|
||
owner = {MJ},
|
||
timestamp = {2020-09-19},
|
||
year = {2021},
|
||
}
|
||
|
||
@Article{sudste_21,
|
||
author = {Sudarshan, Chirag and Steiner, Lukas and Jung, Matthias and Lappas, Jan and Weis, Christian and Wehn, Norbert},
|
||
title = {{A} {N}ovel {DRAM} {A}rchitecture for {I}mproved {B}andwidth {U}tilization and {L}atency {R}eduction {U}sing {D}ual-{P}age {O}peration},
|
||
doi = {10.1109/TCSII.2021.3068007},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
|
||
owner = {MJ},
|
||
timestamp = {2021-02-28},
|
||
year = {2021},
|
||
}
|
||
|
||
@Electronic{tak_14,
|
||
author = {Takahash, Daisuke},
|
||
title = {{FFTE}: {A} {F}ast {F}ourier {T}ransform {P}ackage},
|
||
url = {http://www.ffte.jp/},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-05-17},
|
||
year = {2014},
|
||
}
|
||
|
||
@Article{tan_18,
|
||
author = {Tang, Kar Yee},
|
||
title = {{T}he {N}ew {D}eep {L}earning {M}emory {A}rchitectures {Y}ou {S}hould {K}now {A}bout},
|
||
groups = {MJ:1},
|
||
journal = {Whitepaper eSilicon},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-24},
|
||
year = {2018},
|
||
}
|
||
|
||
@Article{tavkas_14,
|
||
author = {Tavva, Venkata Kalyan and Kasha, Ravi and Mutyam, Madhu},
|
||
title = {{EFGR}: {A}n {E}nhanced {F}ine {G}ranularity {R}efresh {F}eature for {H}igh-{P}erformance {DDR}4 {DRAM} {D}evices},
|
||
doi = {10.1145/2656340},
|
||
issn = {1544-3566},
|
||
number = {3},
|
||
pages = {31:1--31:26},
|
||
url = {http://doi.acm.org/10.1145/2656340},
|
||
volume = {11},
|
||
acmid = {2656340},
|
||
address = {New York, NY, USA},
|
||
articleno = {31},
|
||
groups = {MJ:1},
|
||
issue_date = {October 2014},
|
||
journal = {ACM Trans. Archit. Code Optim.},
|
||
keywords = {DDR4, DRAM architecture, Fine-Granularity Refresh, activation energy, partial rank refresh, precharge, refresh, selective precharge},
|
||
month = oct,
|
||
numpages = {26},
|
||
owner = {MJ},
|
||
publisher = {ACM},
|
||
timestamp = {2015.07.13},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{thocha_12,
|
||
author = {G. Thomas and K. Chandrasekar and B. Åkesson and B. Juurlink and K. Goossens},
|
||
booktitle = {2012 15th Euromicro Conference on Digital System Design},
|
||
title = {{A} {P}redictor-{B}ased {P}ower-{S}aving {P}olicy for {DRAM} {M}emories},
|
||
doi = {10.1109/DSD.2012.11},
|
||
pages = {882-889},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;power aware computing;battery-driven handheld devices;computer systems;energy consumption;energy savings;history-based predictor;marginal performance penalty;off-chip DRAM memory;power saving modes;power-down mode;power-hungry components;power-up latency;predictor-based power-saving policy;self-refresh mode;Clocks;Energy consumption;History;Memory management;Prediction algorithms;Random access memory;Servers;DRAM-Memory;Power-Down;Predictor;Predictor-based Power Saving Policy;Self-Refresh},
|
||
month = {Sept},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-22},
|
||
year = {2012},
|
||
}
|
||
|
||
@Misc{tizmem_17,
|
||
author = {Tiziani, Federico},
|
||
title = {{M}emory and {S}torage for {L}5 {A}utonomy from {A}utomotive {JEDEC} {F}orum},
|
||
url = {https://www.micron.com/about/blogs/2017/november/memory-and-storage-for-l5-autonomy-from-automotive-jedec-forum},
|
||
groups = {MJ:1},
|
||
month = {November},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-03},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{todmue_12,
|
||
author = {Todorov, Vladimir and Mueller-Gritschneder, Daniel and Reinig, Helmut and Schlichtmann, Ulf},
|
||
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe},
|
||
title = {{A}utomated {C}onstruction of a {C}ycle-approximate {T}ransaction {L}evel {M}odel of a {M}emory {C}ontroller},
|
||
isbn = {978-3-9810801-8-6},
|
||
location = {Dresden, Germany},
|
||
pages = {1066--1071},
|
||
publisher = {EDA Consortium},
|
||
series = {DATE '12},
|
||
url = {http://dl.acm.org/citation.cfm?id=2492708.2492972},
|
||
acmid = {2492972},
|
||
address = {San Jose, CA, USA},
|
||
groups = {MJ:1},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2019-09-11},
|
||
year = {2012},
|
||
}
|
||
|
||
@InBook{trasch_13,
|
||
author = {Trapp, Mario and Schneider, Daniel and Liggesmeyer, Peter},
|
||
booktitle = {Perspectives on the Future of Software Engineering: Essays in Honor of Dieter Rombach},
|
||
title = {{A} {S}afety {R}oadmap to {C}yber-{P}hysical {S}ystems},
|
||
doi = {10.1007/978-3-642-37395-4_6},
|
||
editor = {M{\"u}nch, J{\"u}rgen and Schmid, Klaus},
|
||
isbn = {978-3-642-37395-4},
|
||
pages = {81--94},
|
||
publisher = {Springer Berlin Heidelberg},
|
||
url = {https://doi.org/10.1007/978-3-642-37395-4_6},
|
||
abstract = {In recent years, the term cyber-physical systems has emerged to characterize a new generation of embedded systems. In cyber-physical systems, embedded systems will be open in the sense that they will dynamically interconnect with other systems and will be able to dynamically adapt to changing runtime contexts. Such open adaptive systems provide a huge potential for society and for the economy. On the other hand, however, openness and adaptivity make it hard or even impossible for developers to predict a system's dynamic structure and behavior. This impedes the assurance of important system quality properties, especially safety and reliability. Safety assurance of cyber-physical systems will therefore be both one of the most urgent and one of the most challenging research questions of the next decade. This chapter analyzes the state of the art in order to identify open gaps and suggests a runtime safety assurance framework for cyber-physical systems to structure ongoing and future research activities.},
|
||
address = {Berlin, Heidelberg},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-02},
|
||
year = {2013},
|
||
}
|
||
|
||
@Misc{valren_17,
|
||
author = {Valdes-Dapena, Peter},
|
||
title = {{R}enault, {N}issan and {M}itsubishi team up on self-driving and electric cars},
|
||
howpublished = {http://money.cnn.com/2017/09/15/technology/renault-nissan-mitsubishi-alliance-electric-self-driving-cars/index.html},
|
||
groups = {MJ:1},
|
||
month = {September},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-01},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{vaszul_21,
|
||
author = {Vasan, Gokul and Zulian, Éder F. and Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021)},
|
||
title = {{O}nline {W}orking {S}et {C}hange {D}etection with {C}onstant {C}omplexity},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2021-10-07},
|
||
year = {2021},
|
||
}
|
||
|
||
@Article{verwyn_10,
|
||
author = {Verbeek, H. M. W. and Wynn, M. T. and van der Aalst, W. M. P. and ter Hofstede, A. H. M.},
|
||
title = {{R}eduction {R}ules for {R}eset/{I}nhibitor {N}ets},
|
||
doi = {10.1016/j.jcss.2009.06.003},
|
||
issn = {0022-0000},
|
||
number = {2},
|
||
pages = {125--143},
|
||
url = {http://dx.doi.org/10.1016/j.jcss.2009.06.003},
|
||
volume = {76},
|
||
acmid = {1660380},
|
||
address = {Orlando, FL, USA},
|
||
groups = {MJ:1},
|
||
issue_date = {March, 2010},
|
||
journal = {J. Comput. Syst. Sci.},
|
||
keywords = {Boundedness, Inhibitor arcs, Liveness, Petri nets, Reduction rules, Reset arcs},
|
||
month = mar,
|
||
numpages = {19},
|
||
owner = {MJ},
|
||
publisher = {Academic Press, Inc.},
|
||
timestamp = {2016-12-05},
|
||
year = {2010},
|
||
}
|
||
|
||
@TechReport{vin_02,
|
||
author = {Vinterbo, S.A.},
|
||
institution = {Decision Systems Group, Harvard Medical School},
|
||
title = {{M}aximum $k$-{I}ntersection, {E}dge {L}abeled {M}ultigraph {M}ax {C}apacity $k$-{P}ath, and {M}ax {F}actor $k$-gcd are all {NP}-hard},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-02-25},
|
||
year = {2002},
|
||
}
|
||
|
||
@InBook{wacwin_16,
|
||
author = {Wachenfeld, Walther and Winner, Hermann},
|
||
booktitle = {Autonomous Driving: Technical, Legal and Social Aspects},
|
||
title = {{T}he {R}elease of {A}utonomous {V}ehicles},
|
||
doi = {10.1007/978-3-662-48847-8_21},
|
||
editor = {Maurer, Markus and Gerdes, J. Christian and Lenz, Barbara and Winner, Hermann},
|
||
isbn = {978-3-662-48847-8},
|
||
pages = {425--449},
|
||
publisher = {Springer Berlin Heidelberg},
|
||
url = {https://doi.org/10.1007/978-3-662-48847-8_21},
|
||
abstract = {In the future, the functions of autonomous driving could fundamentally change all road traffic; to do so, it would have to be implemented on a large scale, in series production.},
|
||
address = {Berlin, Heidelberg},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2020-06-09},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{wandon_14,
|
||
author = {Jue Wang and Xiangyu Dong and Yuan Xie},
|
||
booktitle = {32nd IEEE International Conference on Computer Design (ICCD)},
|
||
title = {{P}roactive{DRAM}: {A} {DRAM}-initiated retention management scheme},
|
||
doi = {10.1109/ICCD.2014.6974657},
|
||
pages = {22-27},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;scheduling;DRAM scaling;ProactiveDRAM;command scheduling;energy overhead;multirate DRAM refresh scheme;smart retention-aware refresh;weak cell refresh management;Amplitude modulation;Capacitors;DRAM chips;Radiation detectors;Standards;Timing},
|
||
month = {Oct},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2014},
|
||
}
|
||
|
||
@Article{wanhu_16,
|
||
author = {S. Wang and H. C. Hu and H. Zheng and P. Gupta},
|
||
title = {{MEMRES}: {A} {F}ast {M}emory {S}ystem {R}eliability {S}imulator},
|
||
doi = {10.1109/TR.2016.2608357},
|
||
issn = {0018-9529},
|
||
number = {99},
|
||
pages = {1-15},
|
||
volume = {PP},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Reliability},
|
||
keywords = {Analytical models;Circuit faults;Error correction codes;Memory management;Monte Carlo methods;Reliability engineering;Memory fault;magnetic random access memory (MRAM);memory mirroring;memory page retirement;memory reliability;reliability management;retention error;simulator;sparing;spin-transfer torque random access memory (STT-RAM);write error},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-24},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{weileu_15,
|
||
author = {J. H. Weinstock and R. Leupers and G. Ascheid},
|
||
booktitle = {2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
|
||
title = {{P}arallel {S}ystem{C} simulation for {ESL} design using flexible time decoupling},
|
||
doi = {10.1109/SAMOS.2015.7363702},
|
||
pages = {378-383},
|
||
groups = {MJ:1},
|
||
keywords = {discrete event simulation;embedded systems;parallel architectures;ESL design;flexible time decoupling;next generation embedded systems;parallel SystemC simulators;cross-thread communication;Timing;Instruction sets;Time-domain analysis;Time-varying systems;Embedded systems;Kernel},
|
||
month = {July},
|
||
owner = {MJ},
|
||
timestamp = {2018-09-11},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{weijun_15,
|
||
author = {Weis, Christian and Jung, Matthias and Ehses, Peter and Santos, Cristiano and Vivet, Pascal and Goossens, Sven and Koedam, Martijn and Wehn, Norbert},
|
||
booktitle = {Proceedings of the IEEE Conference on Design, Automation \& Test in Europe (DATE)},
|
||
title = {{R}etention {T}ime {M}easurements and {M}odelling of {B}it {E}rror {R}ates of {WIDE} {I}/{O} {DRAM} in {MPS}o{C}s},
|
||
organization = {European Design and Automation Association},
|
||
groups = {MJ:1},
|
||
keywords = {AGWehn},
|
||
owner = {MJ},
|
||
timestamp = {2016-02-17},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{weijun_15a,
|
||
author = {Weis, Christian and Jung, Matthias and Santos, Christiano and Vivet, Pascal and Naji, Omar and Hansson, Andreas and Wehn, Norbert},
|
||
booktitle = {IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
|
||
title = {{T}hermal {A}spects and {H}igh-level {E}xplorations of 3{D} stacked {DRAM}s},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.08.11},
|
||
year = {2015},
|
||
}
|
||
|
||
@Book{weijun_16,
|
||
author = {Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
title = {3{D} {S}tacked {DRAM} {M}emories ({B}ook chapter in the {H}andbook of 3{D} {I}ntegration)},
|
||
publisher = {Wiley-VCH},
|
||
volume = {4},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-01-25},
|
||
year = {2019},
|
||
}
|
||
|
||
@InProceedings{weijun_15b,
|
||
author = {Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {1st International ESWEEK Workshop on Resiliency in Embedded Electronic Systems, Amsterdam, The Netherlands.},
|
||
title = {{R}eliability and {T}hermal {C}hallenges in 3{D} {I}ntegrated {E}mbedded {S}ystems},
|
||
groups = {MJ:1},
|
||
month = {October},
|
||
owner = {MJ},
|
||
timestamp = {2015.12.18},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{weijun_18,
|
||
author = {Weis, Christian and Jung, Matthias and Zulian, Éder F. and Sudarshan, Chirag and Mathew, Deepak and Wehn, Norbert},
|
||
booktitle = {IEEE International Symposium on Circuits and Systems (ISCAS)},
|
||
title = {{T}he {R}ole of {M}emories in {T}ransprecision {C}omputing},
|
||
groups = {MJ:1},
|
||
month = {May},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-25},
|
||
year = {2018},
|
||
}
|
||
|
||
@Article{weiloi_13,
|
||
author = {Weis, Christian and Loi, Igor and Benini, Luca and Wehn, Norbert},
|
||
title = {{E}xploration and {O}ptimization of 3-{D} {I}ntegrated {DRAM} {S}ubsystems},
|
||
doi = {10.1109/TCAD.2012.2235125},
|
||
issn = {0278-0070},
|
||
number = {4},
|
||
pages = {597-610},
|
||
volume = {32},
|
||
file = {weiloi_13.pdf:weiloi_13.pdf:PDF},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
|
||
keywords = {DRAM chips;next generation networks;system-on-chip;three-dimensional integrated circuits;controller architecture;3D DRAM model;design space exploration;3D DRAM subsystem;power estimation engine;3D stacked DRAM;SDR/DDR 3D DRAM channel controller;synthesizable model;flexible interface;fine grained access;3D DRAM cube;SDR/DDR 3D DRAM controller;next generation 3D integrated SoC;energy efficient DRAM subsystem;3D DRAM architecture design space;dies;3D integration;TSV technology;through silicon via technology;tablets;smartphones;mobile device;systems on chip;optimization criterion;energy efficiency;3D integrated DRAM subsystems;Random access memory;Computer architecture;Integrated circuit modeling;Through-silicon vias;Bandwidth;Organizations;3-D integration;channel;controller;DRAM},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.09},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{weiloi_12,
|
||
author = {Weis, C. and Loi, I. and Benini, L. and Wehn, N.},
|
||
booktitle = {{proc. DATE 2012}},
|
||
title = {{An energy efficient DRAM subsystem for 3D integrated SoCs}},
|
||
groups = {MJ:1},
|
||
keywords = {LPDDR2; SDR-DDR 3D-DRAM channel controller; TSV technology; WIDE-IO interface; attached 3D-stacked DRAM cube; energy consumption; energy efficient DRAM subsystem; fine-grained access; logic layers stacking; memory cooptimization; memory interface; mobile terminal; multiple memory stacking; next-generation 3D integrated SoC; optimization design; power estimation engine; power saving; smartphone; storage capacity 256 Mbit to 4 Gbit; tablet; through silicon via technology; DRAM chips; energy conservation; integrated circuit design; network synthesis; optimisation; system-on-chip; three-dimensional integrated circuits},
|
||
month = {march},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.10},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{wulmck_95,
|
||
author = {Wulf, Wm. A. and McKee, Sally A.},
|
||
title = {{Hitting the memory wall: implications of the obvious}},
|
||
doi = {10.1145/216585.216588},
|
||
url = {http://doi.acm.org/10.1145/216585.216588},
|
||
acmid = {216588},
|
||
groups = {MJ:1},
|
||
issue_date = {March 1995},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
month = mar,
|
||
numpages = {5},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.10},
|
||
year = {1995},
|
||
}
|
||
|
||
@Article{xav_12,
|
||
author = {Xavier, Eduardo C.},
|
||
title = {{A} note on a {M}aximum k-{S}ubset {I}ntersection {P}roblem},
|
||
number = {12},
|
||
pages = {471-472},
|
||
volume = {112},
|
||
groups = {MJ:1},
|
||
journal = {Information Processing Letters},
|
||
owner = {MJ},
|
||
timestamp = {2019-02-25},
|
||
year = {2012},
|
||
}
|
||
|
||
@Article{yanwei_16,
|
||
author = {C. M. Yang and C. K. Wei and Y. J. Chang and T. C. Wu and H. P. Chen and C. S. Lai},
|
||
title = {{S}uppression of {R}ow {H}ammer {E}ffect by {D}oping {P}rofile {M}odification in {S}addle-{F}in {A}rray {D}evices for {S}ub-30-nm {DRAM} {T}echnology},
|
||
doi = {10.1109/TDMR.2016.2607174},
|
||
issn = {1530-4388},
|
||
number = {4},
|
||
pages = {685-687},
|
||
volume = {16},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Transactions on Device and Materials Reliability},
|
||
keywords = {DRAM chips;doping profiles;integrated circuit reliability;isolation technology;phosphorus;DRAM technology;access device;array device;buried word lines;channel leaking;doping profile modification;dosage modification;dynamic random-access memory;electric field;energy adjustment;fabrication process optimization;gate-induced electron;isolation spacing;localized shielding effect;phosphorus implantation;reliability issue;row hammer effect suppression;saddle-fin array device;Doping profiles;Junctions;Logic gates;Materials reliability;Random access memory;Resistance;Transistors;DRAM;Row hammer;implantation},
|
||
month = {Dec},
|
||
owner = {MJ},
|
||
timestamp = {2018-05-03},
|
||
year = {2016},
|
||
}
|
||
|
||
@Article{yazthw_16,
|
||
author = {Yazdanbakhsh, A. and Thwaites,B. and Esmaeilzadeh, H. and Pekhimenko, G. and Mutlu, O. and Mowry, T. C.},
|
||
title = {{M}itigating the {M}emory {B}ottleneck {W}ith {A}pproximate {L}oad {V}alue {P}rediction},
|
||
number = {1},
|
||
pages = {32-42},
|
||
volume = {33},
|
||
groups = {MJ:1},
|
||
journal = {IEEE Design \& Test},
|
||
month = {February},
|
||
owner = {MJ},
|
||
timestamp = {2016-04-05},
|
||
year = {2016},
|
||
}
|
||
|
||
@Misc{yuaaam_09,
|
||
author = {Yuan, George L. and Aamodt, Tor M.},
|
||
title = {{A} {H}ybrid {A}nalytical {DRAM} {P}erformance {M}odel},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2019-09-11},
|
||
year = {2009},
|
||
}
|
||
|
||
@InProceedings{yunyao_13,
|
||
author = {H. Yun and G. Yao and R. Pellizzoni and M. Caccamo and L. Sha},
|
||
booktitle = {2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)},
|
||
title = {{M}em{G}uard: {M}emory bandwidth reservation system for efficient performance isolation in multi-core platforms},
|
||
doi = {10.1109/RTAS.2013.6531079},
|
||
pages = {55-64},
|
||
groups = {MJ:1},
|
||
issn = {1080-1812},
|
||
keywords = {multiprocessing systems;storage management;MemGuard;SPEC2006 benchmark;best effort memory bandwidth;guaranteed memory bandwidth;memory bandwidth reservation system;memory performance isolation;multicore platform;temporal isolation;Bandwidth;Benchmark testing;Multicore processing;Random access memory;Real-time systems;Regulators;Throughput},
|
||
month = {April},
|
||
owner = {MJ},
|
||
timestamp = {2018-04-29},
|
||
year = {2013},
|
||
}
|
||
|
||
@InProceedings{zhapor_14,
|
||
author = {Zhang, Tao and Poremba, Matthew and Xu, Cong and Sun, Guangyu and Xie, Yuan},
|
||
booktitle = {High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on},
|
||
title = {{CREAM}: a {C}oncurrent-{R}efresh-{A}ware {DRAM} {M}emory {A}rchitecture},
|
||
organization = {IEEE},
|
||
pages = {368--379},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2015.07.10},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{zhaxu_14,
|
||
author = {Zhang, Tao and Xu, Cong and Chen, Ke and Sun, Guangyu and Xie, Yuan},
|
||
booktitle = {Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI},
|
||
title = {3{D}-{SWIFT}: {A} {H}igh-performance 3{D}-stacked {W}ide {IO} {DRAM}},
|
||
doi = {10.1145/2591513.2591529},
|
||
isbn = {978-1-4503-2816-6},
|
||
location = {Houston, Texas, USA},
|
||
pages = {51--56},
|
||
publisher = {ACM},
|
||
series = {GLSVLSI '14},
|
||
acmid = {2591529},
|
||
address = {New York, NY, USA},
|
||
file = {zhaxu_14.pdf:zhaxu_14.pdf:PDF},
|
||
groups = {MJ:1},
|
||
keywords = {3D ICS, DRAM, memory parallelism, sub-bank, wide IO},
|
||
numpages = {6},
|
||
owner = {MJ},
|
||
timestamp = {2015.02.11},
|
||
year = {2014},
|
||
}
|
||
|
||
@InProceedings{zhazha_16a,
|
||
author = {Zhang, Xianwei and Zhang, Youtao and Childers, Bruce and Yang, Jun},
|
||
booktitle = {Proceedings of the Second International Symposium on Memory Systems},
|
||
title = {{AWARD}: {A}pproximation-a{WA}re {R}estore in {F}urther {S}caling {DRAM}},
|
||
doi = {10.1145/2989081.2989127},
|
||
isbn = {978-1-4503-4305-3},
|
||
location = {Alexandria, VA, USA},
|
||
pages = {322--324},
|
||
publisher = {ACM},
|
||
series = {MEMSYS '16},
|
||
url = {http://doi.acm.org/10.1145/2989081.2989127},
|
||
acmid = {2989127},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
keywords = {Approximate Computing, DRAM Scaling, Slow Restore},
|
||
numpages = {3},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{zhazha_16b,
|
||
author = {X. Zhang and Y. Zhang and B. R. Childers and J. Yang},
|
||
booktitle = {2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)},
|
||
title = {{R}estore truncation for performance improvement in future {DRAM} systems},
|
||
doi = {10.1109/HPCA.2016.7446093},
|
||
pages = {543-554},
|
||
groups = {MJ:1},
|
||
keywords = {DRAM chips;performance evaluation;power aware computing;DRAM chips;DRAM module performance;DRAM scaling;DRAM systems;RT schemes;bit cell structure;cell data restoration;energy consumption;performance improvement;process variations;read write access;restore strategy;restore timing;restore truncation;Capacitors;DRAM chips;Hardware;Sensors;Timing;Transistors},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2016},
|
||
}
|
||
|
||
@InProceedings{zhazha_15,
|
||
author = {X. Zhang and Y. Zhang and B. R. Childers and J. Yang},
|
||
booktitle = {2015 Design, Automation Test in Europe Conference Exhibition (DATE)},
|
||
title = {{E}xploiting {DRAM} restore time variations in deep sub-micron scaling},
|
||
pages = {477-482},
|
||
groups = {MJ:1},
|
||
issn = {1530-1591},
|
||
keywords = {DRAM chips;microprocessor chips;multiprocessing systems;performance evaluation;4-core multiprocessor system;DRAM restore time variations;ECC;cell restore time;deep submicron scaling;memory chunks;performance degradation;relaxed timing constraints;row sparing;tWR;timing constraints;variation-aware memory controller;write recovery time;Capacitors;Degradation;Error correction codes;Integrated circuit modeling;Random access memory;Standards;Timing},
|
||
month = {March},
|
||
owner = {MJ},
|
||
timestamp = {2016-11-17},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{zhazhu_00,
|
||
author = {Zhang, Zhao and Zhu, Zhichun and Zhang, Xiaodong},
|
||
booktitle = {Proceedings of the 33rd Annual ACM/IEEE International Symposium on Microarchitecture},
|
||
title = {{A} {P}ermutation-based {P}age {I}nterleaving {S}cheme to {R}educe {R}ow-buffer {C}onflicts and {E}xploit {D}ata {L}ocality},
|
||
doi = {10.1145/360128.360134},
|
||
isbn = {1-58113-196-8},
|
||
location = {Monterey, California, USA},
|
||
pages = {32--41},
|
||
publisher = {ACM},
|
||
series = {MICRO 33},
|
||
url = {http://doi.acm.org/10.1145/360128.360134},
|
||
acmid = {360134},
|
||
address = {New York, NY, USA},
|
||
groups = {MJ:1},
|
||
numpages = {10},
|
||
owner = {MJ},
|
||
timestamp = {2015.01.21},
|
||
year = {2000},
|
||
}
|
||
|
||
@Book{zhoven_99,
|
||
author = {Zhou, MengChu and Venkatesh, Kurapati},
|
||
title = {{M}odeling, simulation, and control of flexible manufacturing systems: a {P}etri net approach},
|
||
publisher = {World Scientific},
|
||
volume = {6},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2017-02-27},
|
||
year = {1999},
|
||
}
|
||
|
||
@Article{zhuwan_15,
|
||
author = {Zhu, DanFeng and Wang, Rui and Wei, YanJiang and Qian, DePei},
|
||
title = {{R}educing {DRAM} refreshing in an error correction manner},
|
||
doi = {10.1007/s11432-015-5352-4},
|
||
issn = {1674-733X},
|
||
language = {English},
|
||
pages = {1-14},
|
||
url = {http://dx.doi.org/10.1007/s11432-015-5352-4},
|
||
groups = {MJ:1},
|
||
journal = {Science China Information Sciences},
|
||
keywords = {DRAM refreshing; error correction; DRAM-ECP; counting bloom filter; retention time},
|
||
owner = {MJ},
|
||
publisher = {Science China Press},
|
||
timestamp = {2015.07.10},
|
||
year = {2015},
|
||
}
|
||
|
||
@InProceedings{zulhau_20,
|
||
author = {Zulian, Éder F. and Haugou, Germain and Weis, Christian and Jung, Matthias and Wehn, Norbert},
|
||
booktitle = {International Conference on High-Performance and Embedded Architectures and Compilers 2020 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO)},
|
||
title = {{S}ystem {S}imulation with {PULP} {V}irtual {P}latform and {S}ystem{C}},
|
||
groups = {MJ:1},
|
||
month = {January},
|
||
owner = {MJ},
|
||
timestamp = {2020-09-19},
|
||
year = {2020},
|
||
}
|
||
|
||
@Book{petri_03,
|
||
title = {{P}etri {N}et {T}echnology for {C}ommunication-{B}ased {S}ystems - {A}dvances in {P}etri {N}ets},
|
||
editor = {Hartmut Ehrig and Wolfgang Reisig and Grzegorz Rozenberg and Herbert Weber},
|
||
isbn = {3-540-20538-1},
|
||
publisher = {Springer},
|
||
series = {Lecture Notes in Computer Science},
|
||
volume = {2472},
|
||
bibsource = {dblp computer science bibliography, http://dblp.org},
|
||
biburl = {http://dblp2.uni-trier.de/rec/bib/conf/dfg/2003},
|
||
groups = {MJ:1},
|
||
owner = {MJ},
|
||
timestamp = {2023-03-28},
|
||
year = {2003},
|
||
}
|
||
|
||
@Article{patkim_17,
|
||
author = {Patel, Minesh and Kim, Jeremie S. and Mutlu, Onur},
|
||
title = {The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions},
|
||
doi = {10.1145/3140659.3080242},
|
||
issn = {0163-5964},
|
||
number = {2},
|
||
pages = {255–268},
|
||
url = {https://doi.org/10.1145/3140659.3080242},
|
||
volume = {45},
|
||
abstract = {Modern DRAM-based systems suffer from significant energy and latency penalties due to conservative DRAM refresh standards. Volatile DRAM cells can retain information across a wide distribution of times ranging from milliseconds to many minutes, but each cell is currently refreshed every 64ms to account for the extreme tail end of the retention time distribution, leading to a high refresh overhead. Due to poor DRAM technology scaling, this problem is expected to get worse in future device generations. Hence, the current approach of refreshing all cells with the worst-case refresh rate must be replaced with a more intelligent design.Many prior works propose reducing the refresh overhead by extending the default refresh interval to a higher value, which we refer to as the target refresh interval, across parts or all of a DRAM chip. These proposals handle the small set of failing cells that cannot retain data throughout the entire extended refresh interval via retention failure mitigation mechanisms (e.g., error correcting codes or bit-repair mechanisms). This set of failing cells is discovered via retention failure profiling, which is currently a brute-force process that writes a set of known data to DRAM, disables refresh and waits for the duration of the target refresh interval, and then checks for retention failures across the DRAM chip. We show that this brute-force approach is too slow and is detrimental to system execution, especially with frequent online profiling.This paper presents reach profiling, a new methodology for retention failure profiling based on the key observation that an overwhelming majority of failing DRAM cells at a target refresh interval fail more reliably at both longer refresh intervals and higher temperatures. Using 368 state-of-the-art LPDDR4 DRAM chips from three major vendors, we conduct a thorough experimental characterization of the complex set of tradeoffs inherent in the profiling process. We identify three key metrics to guide design choices for retention failure profiling and mitigation mechanisms: coverage, false positive rate, and runtime. We propose reach profiling, a new retention failure profiling mechanism whose key idea is to profile failing cells at a longer refresh interval and/or higher temperature relative to the target conditions in order to maximize failure coverage while minimizing the false positive rate and profiling runtime. We thoroughly explore the tradeoffs associated with reach profiling and show that there is significant room for improvement in DRAM retention failure profiling beyond the brute-force approach. We show with experimental data that on average, by profiling at 250ms above the target refresh interval, our first implementation of reach profiling (called REAPER) can attain greater than 99% coverage of failing DRAM cells with less than a 50% false positive rate while running 2.5x faster than the brute-force approach. In addition, our end-to-end evaluations show that REAPER enables significant system performance improvement and DRAM power reduction, outperforming the brute-force approach and enabling high-performance operation at longer refresh intervals that were previously unreasonable to employ due to the high associated profiling overhead.},
|
||
address = {New York, NY, USA},
|
||
issue_date = {May 2017},
|
||
journal = {SIGARCH Comput. Archit. News},
|
||
keywords = {testing, reliability, memory, retention failures, refresh, DRAM},
|
||
month = {jun},
|
||
numpages = {14},
|
||
owner = {MJ},
|
||
publisher = {Association for Computing Machinery},
|
||
year = {2017},
|
||
}
|
||
|
||
@InProceedings{venher_06,
|
||
author = {Venkatesan, R.K. and Herr, S. and Rotenberg, E.},
|
||
booktitle = {The Twelfth International Symposium on High-Performance Computer Architecture, 2006.},
|
||
title = {Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM},
|
||
doi = {10.1109/HPCA.2006.1598122},
|
||
pages = {155-165},
|
||
year = {2006},
|
||
}
|
||
|
||
@InProceedings{uecjun_22,
|
||
author = {Uecker, Denis and Jung, Matthias},
|
||
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
|
||
title = {Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC},
|
||
editor = {Orailoglu, Alex and Reichenbach, Marc and Jung, Matthias},
|
||
isbn = {978-3-031-15074-6},
|
||
pages = {74--89},
|
||
publisher = {Springer International Publishing},
|
||
abstract = {The development of safe hardware is a major concern in automotive applications. The parts 5 and 11 of the ISO 26262 define procedures and methods for the development of hardware to achieve a specific automotive safety integrity level. In this paper, we present a novel methodology that combines the hardware metrics analysis of ISO 26262 with SystemC-based virtual prototyping. To show the applicability of our methodology, we modeled the LPDDR4 memory system of a current state-of-the-art ADAS system and estimated the ASIL level of this system. The new methodology is implemented in SystemC and is provided as open-source.},
|
||
address = {Cham},
|
||
owner = {MJ},
|
||
year = {2022},
|
||
}
|
||
|
||
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|
||
|
||
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|
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