177 lines
4.5 KiB
TeX
177 lines
4.5 KiB
TeX
\section{Appendix}
|
|
\label{sec:appendix}
|
|
|
|
\subsection{Simulation Address Mappings}
|
|
\label{sec:address_mappings}
|
|
|
|
\begin{table}[!hbt]
|
|
\caption{Memory configuration used in comparison simulations against gem5.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|c|}
|
|
\hline
|
|
DRAM & \parbox{2.2cm}{\centering Ranks\\per Channel} & \parbox{2cm}{\centering Banks\\per Rank} & Rows & Columns & \parbox{2cm}{\centering Devices\\per Rank} & Width\\
|
|
\hline
|
|
\hline
|
|
DDR3 & 2 & 8 & 65536 & 1024 & 8 & 8\\
|
|
\hline
|
|
DDR4 & 2 & 16 & 65536 & 1024 & 8 & 8\\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\end{table}
|
|
|
|
\begin{table}[!hbt]
|
|
\caption{Address mappings used in comparison simulations against gem5.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|c|}
|
|
\hline
|
|
DRAM & Byte & Column & Bankgroup & Bank & Rank & Row\\
|
|
\hline
|
|
\hline
|
|
DDR3 & 0-2 & 3-12 & - & 13-15 & 16 & 17-32 \\
|
|
\hline
|
|
DDR4 & 0-2 & 3-12 & 13-14 & 15-16 & 17 & 18-33 \\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\end{table}
|
|
|
|
\begin{table}[!hbt]
|
|
\caption{Memory configuration used in comparison simulations against Ramulator.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|c|}
|
|
\hline
|
|
DRAM & \parbox{2.2cm}{\centering Ranks\\per Channel} & \parbox{2cm}{\centering Banks\\per Rank} & Rows & Columns & \parbox{2cm}{\centering Devices\\per Rank} & Width\\
|
|
\hline
|
|
\hline
|
|
DDR3 & 1 & 8 & 32768 & 1024 & 8 & 8\\
|
|
\hline
|
|
DDR4 & 1 & 16 & 32768 & 1024 & 8 & 8\\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\end{table}
|
|
|
|
\begin{table}[!hbt]
|
|
\caption{Address mappings used in comparison simulations against Ramulator.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|c|}
|
|
\hline
|
|
DRAM & Byte & Column & Bankgroup & Bank & Rank & Row\\
|
|
\hline
|
|
\hline
|
|
DDR3 & 0-2 & 3-12 & - & 13-15 & - & 16-30 \\
|
|
\hline
|
|
DDR4 & 0-2 & 3-12 & 13-14 & 15-16 & - & 17-31 \\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\end{table}
|
|
|
|
\subsection{Simulation Results}
|
|
\label{sec:appendix_sim_results}
|
|
|
|
\begin{table}[!ht]
|
|
\caption{Last-level cache (L2) statistics.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|}
|
|
\hline
|
|
\multirow{2}*{Benchmark} & \multicolumn{3}{|c|}{\parbox{2.3cm}{Miss Rate [\%]\\(DDR3-1600)}} & \multicolumn{3}{|c|}{\parbox{2.3cm}{Miss Rate [\%]\\(DDR4-2400)}} \\
|
|
\cline{2-7}
|
|
& FS & SE & DS & FS & SE & DS \\
|
|
\hline
|
|
\hline
|
|
|
|
COPY & 96.8 & 100.0 & 76.9 & 96.7 & 100.0 & 76.3 \\
|
|
\hline
|
|
DAXPY & 96.7 & 100.0 & 74.8 & 96.7 & 100.0 & 74.9 \\
|
|
\hline
|
|
INIT & 94.9 & 100.0 & 70.3 & 94.8 & 99.8 & 70.3 \\
|
|
\hline
|
|
SDAXPY & 96.7 & 100.0 & 080.9 & 96.6 & 100.0 & 80.7 \\
|
|
\hline
|
|
STRIAD & 97.1 & 100.0 & 083.1 & 96.6 & 100.0 & 83.0 \\
|
|
\hline
|
|
SUM & 94.8 & 100.0 & 89.4 & 94.8 & 99.9 & 89.5 \\
|
|
\hline
|
|
TRIAD & 96.6 & 100.0 & 80.9 & 96.6 & 100.0 & 80.6 \\
|
|
\hline
|
|
UPDATE & 94.9 & 100.0 & 71.6 & 94.8 & 99.9 & 71.6 \\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\label{tab:benchmark_gem5_cache_ddr4}
|
|
\end{table}
|
|
|
|
\begin{table}[!ht]
|
|
\caption{Results for memory access latency and data bus utilization with DDR3-1600.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|}
|
|
\hline
|
|
\multirow{2}*{Benchmark} & \multicolumn{3}{|c|}{Simulation Time [s]} & \multicolumn{3}{|c|}{Avg. Latency [ns]} \\
|
|
\cline{2-7}
|
|
& FS & SE & DS & FS & SE & DS\\
|
|
\hline
|
|
\hline
|
|
|
|
COPY & 0.186 & 0.149 & 0.206 & 47.4 & 35.2 & 55.8 \\
|
|
\hline
|
|
DAXPY & 0.183 & 0.153 & 0.271 & 39.1 & 34.8 & 49.4 \\
|
|
\hline
|
|
INIT & 0.139 & 0.117 & 0.169 & 39.0 & 42.2 & 48.1 \\
|
|
\hline
|
|
SDAXPY & 0.226 & 0.181 & 0.255 & 43.2 & 29.3 & 50.6 \\
|
|
\hline
|
|
STRIAD & 0.251 & 0.228 & 0.266 & 36.6 & 37.6 & 50.4 \\
|
|
\hline
|
|
SUM & 0.134 & 0.107 & 0.204 & 29.0 & 28.4 & 44.2 \\
|
|
\hline
|
|
TRIAD & 0.220 & 0.183 & 0.251 & 40.6 & 32.5 & 51.2 \\
|
|
\hline
|
|
UPDATE & 0.146 & 0.121 & 0.248 & 39.8 & 40.3 & 49.9 \\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\label{tab:benchmark_access_ddr3}
|
|
\end{table}
|
|
|
|
\begin{table}[!ht]
|
|
\caption{Results for memory access latency and data bus utilization with DDR4-2400.}
|
|
\begin{center}
|
|
\begin{tabular}{|c|c|c|c|c|c|c|}
|
|
\hline
|
|
\multirow{2}*{Benchmark} & \multicolumn{3}{|c|}{Simulation Time [s]} & \multicolumn{3}{|c|}{Avg. Latency [ns]} \\
|
|
\cline{2-7}
|
|
& FS & SE & DS & FS & SE & DS\\
|
|
\hline
|
|
\hline
|
|
|
|
COPY & 0.172 & 0.144 & 0.208 & 32.5 & 29.8 & 43.4 \\
|
|
\hline
|
|
DAXPY & 0.175 & 0.148 & 0.273 & 31.4 & 29.5 & 38.8 \\
|
|
\hline
|
|
INIT & 0.137 & 0.112 & 0.172 & 36.0 & 34.8 & 39.5 \\
|
|
\hline
|
|
SDAXPY & 0.212 & 0.177 & 0.259 & 32.7 & 26.4 & 40.4 \\
|
|
\hline
|
|
STRIAD & 0.210 & 0.212 & 0.268 & 34.5 & 29.1 & 40.1 \\
|
|
\hline
|
|
SUM & 0.130 & 0.107 & 0.205 & 24.1 & 27.0 & 37.1 \\
|
|
\hline
|
|
TRIAD & 0.212 & 0.175 & 0.254 & 34.5 & 26.7 & 40.4 \\
|
|
\hline
|
|
UPDATE & 0.141 & 0.118 & 0.247 & 33.0 & 34.2 & 40.5 \\
|
|
\hline
|
|
|
|
\end{tabular}
|
|
\end{center}
|
|
\label{tab:benchmark_gem5_access_ddr4}
|
|
\end{table}
|
|
|