DRAMSys

doc.bib

@@ -72,4 +72,52 @@
   doi       = {10.1109/SAMOS.2017.8344612},
 }
 
+@InProceedings{Steiner2020,
+  author    = {Steiner, Lukas and Jung, Matthias and Prado, Felipe S. and Bykov, Kirill and Wehn, Norbert},
+  booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation},
+  title     = {DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator},
+  year      = {2020},
+  address   = {Cham},
+  editor    = {Orailoglu, Alex and Jung, Matthias and Reichenbach, Marc},
+  pages     = {110--126},
+  publisher = {Springer International Publishing},
+  abstract  = {The simulation of DRAMs (Dynamic Random Access Memories) on system level requires highly accurate models due to their complex timing and power behavior. However, conventional cycle-accurate DRAM models often become the bottleneck for the overall simulation speed. A promising alternative are DRAM simulation models based on Transaction Level Modeling, which can be fast and accurate at the same time. In this paper we present DRAMSys4.0, which is, to the best of our knowledge, the fastest cycle-accurate open-source DRAM simulator and has a large range of functionalities. DRAMSys4.0 includes a novel simulator architecture that enables a fast adaptation to new DRAM standards using a Domain Specific Language. We present optimization techniques to achieve a high simulation speed while maintaining full temporal accuracy. Finally, we provide a detailed survey and comparison of the most prominent cycle-accurate open-source DRAM simulators with regard to their supported features, analysis capabilities and simulation speed.},
+  isbn      = {978-3-030-60939-9},
+}
+
+@Book{Jung2017,
+  author    = {Jung, M.},
+  publisher = {Technische Universit{\"a}t Kaiserslautern},
+  title     = {System-level Modeling, Analysis and Optimization of DRAM Memories and Controller Architectures},
+  year      = {2017},
+  isbn      = {9783959740517},
+  series    = {Forschungsberichte Mikroelektronik},
+}
+
+@Article{Binkert2011,
+  author     = {Binkert, Nathan and Beckmann, Bradford and Black, Gabriel and Reinhardt, Steven K. and Saidi, Ali and Basu, Arkaprava and Hestness, Joel and Hower, Derek R. and Krishna, Tushar and Sardashti, Somayeh and Sen, Rathijit and Sewell, Korey and Shoaib, Muhammad and Vaish, Nilay and Hill, Mark D. and Wood, David A.},
+  journal    = {SIGARCH Comput. Archit. News},
+  title      = {The Gem5 Simulator},
+  year       = {2011},
+  issn       = {0163-5964},
+  month      = {aug},
+  number     = {2},
+  volume     = {39},
+  abstract   = {The gem5 simulation infrastructure is the merger of the best aspects of the M5 [4] and GEMS [9] simulators. M5 provides a highly configurable simulation framework, multiple ISAs, and diverse CPU models. GEMS complements these features with a detailed and exible memory system, including support for multiple cache coherence protocols and interconnect models. Currently, gem5 supports most commercial ISAs (ARM, ALPHA, MIPS, Power, SPARC, and x86), including booting Linux on three of them (ARM, ALPHA, and x86).The project is the result of the combined efforts of many academic and industrial institutions, including AMD, ARM, HP, MIPS, Princeton, MIT, and the Universities of Michigan, Texas, and Wisconsin. Over the past ten years, M5 and GEMS have been used in hundreds of publications and have been downloaded tens of thousands of times. The high level of collaboration on the gem5 project, combined with the previous success of the component parts and a liberal BSD-like license, make gem5 a valuable full-system simulation tool.},
+  address    = {New York, NY, USA},
+  doi        = {10.1145/2024716.2024718},
+  issue_date = {May 2011},
+  numpages   = {7},
+  publisher  = {Association for Computing Machinery},
+  url        = {https://doi.org/10.1145/2024716.2024718},
+}
+
+@InProceedings{Jung2017a,
+  author    = {Jung, Matthias and Kraft, Kira and Wehn, Norbert},
+  booktitle = {2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},
+  title     = {A new state model for DRAMs using Petri Nets},
+  year      = {2017},
+  doi       = {10.1109/SAMOS.2017.8344631},
+}
+
 @Comment{jabref-meta: databaseType:bibtex;}