387 lines
12 KiB
C++
387 lines
12 KiB
C++
/*
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* Copyright (c) 2019, Technische Universität Kaiserslautern
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Lukas Steiner
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*/
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#include <algorithm>
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#include "BankMachine.h"
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#include "../configuration/Configuration.h"
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using namespace sc_core;
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using namespace tlm;
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BankMachine::BankMachine(const Configuration& config, const SchedulerIF& scheduler, const CheckerIF& checker, Bank bank)
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: scheduler(scheduler), checker(checker), memSpec(*config.memSpec), bank(bank),
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bankgroup(BankGroup(bank.ID() / memSpec.banksPerGroup)), rank(Rank(bank.ID() / memSpec.banksPerRank)),
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refreshManagement(config.refreshManagement)
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{}
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CommandTuple::Type BankMachine::getNextCommand()
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{
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return {nextCommand, currentPayload, std::max(timeToSchedule, sc_time_stamp())};
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}
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void BankMachine::updateState(Command command)
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{
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switch (command)
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{
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case Command::ACT:
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state = State::Activated;
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openRow = DramExtension::getRow(*currentPayload);
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keepTrans = true;
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refreshManagementCounter++;
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break;
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case Command::PREPB: case Command::PRESB: case Command::PREAB:
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state = State::Precharged;
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keepTrans = false;
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break;
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case Command::RD: case Command::WR:
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currentPayload = nullptr;
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keepTrans = false;
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break;
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case Command::RDA: case Command::WRA:
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state = State::Precharged;
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currentPayload = nullptr;
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keepTrans = false;
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break;
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case Command::PDEA: case Command::PDEP: case Command::SREFEN:
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assert(!keepTrans);
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sleeping = true;
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break;
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case Command::REFPB: case Command::REFP2B: case Command::REFSB: case Command::REFAB:
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sleeping = false;
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blocked = false;
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if (refreshManagement)
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{
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if (refreshManagementCounter > memSpec.getRAACDR())
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refreshManagementCounter -= memSpec.getRAACDR();
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else
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refreshManagementCounter = 0;
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}
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break;
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case Command::RFMPB: case Command::RFMP2B: case Command::RFMSB: case Command::RFMAB:
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assert(!keepTrans);
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sleeping = false;
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blocked = false;
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if (refreshManagement)
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{
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if (refreshManagementCounter > memSpec.getRAAIMT())
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refreshManagementCounter -= memSpec.getRAAIMT();
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else
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refreshManagementCounter = 0;
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}
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break;
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case Command::PDXA: case Command::PDXP:
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assert(!keepTrans);
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sleeping = false;
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break;
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default:
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break;
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}
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}
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uint64_t BankMachine::getRefreshManagementCounter() const
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{
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return refreshManagementCounter;
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}
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void BankMachine::block()
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{
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blocked = true;
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timeToSchedule = sc_max_time();
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nextCommand = Command::NOP;
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}
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Rank BankMachine::getRank() const
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{
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return rank;
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}
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BankGroup BankMachine::getBankGroup() const
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{
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return bankgroup;
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}
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Bank BankMachine::getBank() const
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{
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return bank;
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}
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Row BankMachine::getOpenRow() const
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{
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return openRow;
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}
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bool BankMachine::isIdle() const
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{
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return (currentPayload == nullptr);
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}
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bool BankMachine::isActivated() const
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{
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return state == State::Activated;
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}
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bool BankMachine::isPrecharged() const
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{
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return state == State::Precharged;
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}
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BankMachineOpen::BankMachineOpen(const Configuration& config, const SchedulerIF& scheduler, const CheckerIF& checker,
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Bank bank)
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: BankMachine(config, scheduler, checker, bank) {}
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sc_time BankMachineOpen::start()
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{
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timeToSchedule = sc_max_time();
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nextCommand = Command::NOP;
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if (!(sleeping || blocked))
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{
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tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
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if (newPayload == nullptr)
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{
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return timeToSchedule;
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}
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else
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{
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assert(!keepTrans || currentPayload != nullptr);
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if (keepTrans)
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{
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if (DramExtension::getRow(*newPayload) == openRow)
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currentPayload = newPayload;
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}
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else
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{
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currentPayload = newPayload;
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}
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if (state == State::Precharged) // bank precharged
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nextCommand = Command::ACT;
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else if (state == State::Activated)
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{
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if (DramExtension::getRow(*currentPayload) == openRow) // row hit
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{
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assert(currentPayload->is_read() || currentPayload->is_write());
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if (currentPayload->is_read())
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nextCommand = Command::RD;
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else
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nextCommand = Command::WR;
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}
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else // row miss
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nextCommand = Command::PREPB;
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}
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timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
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return timeToSchedule;
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}
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}
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else
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return timeToSchedule;
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}
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BankMachineClosed::BankMachineClosed(const Configuration& config, const SchedulerIF& scheduler,
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const CheckerIF& checker, Bank bank)
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: BankMachine(config, scheduler, checker, bank) {}
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sc_time BankMachineClosed::start()
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{
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timeToSchedule = sc_max_time();
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nextCommand = Command::NOP;
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if (!(sleeping || blocked))
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{
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tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
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if (newPayload == nullptr)
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{
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return timeToSchedule;
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}
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else
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{
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assert(!keepTrans || currentPayload != nullptr);
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if (keepTrans)
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{
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if (DramExtension::getRow(*newPayload) == openRow)
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currentPayload = newPayload;
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}
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else
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{
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currentPayload = newPayload;
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}
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if (state == State::Precharged) // bank precharged
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nextCommand = Command::ACT;
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else if (state == State::Activated)
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{
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assert(currentPayload->is_read() || currentPayload->is_write());
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if (currentPayload->is_read())
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nextCommand = Command::RDA;
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else
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nextCommand = Command::WRA;
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}
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timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
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return timeToSchedule;
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}
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}
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else
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return timeToSchedule;
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}
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BankMachineOpenAdaptive::BankMachineOpenAdaptive(const Configuration& config, const SchedulerIF& scheduler,
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const CheckerIF& checker, Bank bank)
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: BankMachine(config, scheduler, checker, bank) {}
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sc_time BankMachineOpenAdaptive::start()
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{
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timeToSchedule = sc_max_time();
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nextCommand = Command::NOP;
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if (!(sleeping || blocked))
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{
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tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
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if (newPayload == nullptr)
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{
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return timeToSchedule;
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}
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else
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{
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assert(!keepTrans || currentPayload != nullptr);
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if (keepTrans)
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{
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if (DramExtension::getRow(*newPayload) == openRow)
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currentPayload = newPayload;
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}
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else
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{
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currentPayload = newPayload;
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}
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if (state == State::Precharged) // bank precharged
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nextCommand = Command::ACT;
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else if (state == State::Activated)
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{
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if (DramExtension::getRow(*currentPayload) == openRow) // row hit
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{
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if (scheduler.hasFurtherRequest(bank, currentPayload->get_command())
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&& !scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command()))
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{
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assert(currentPayload->is_read() || currentPayload->is_write());
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if (currentPayload->is_read())
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nextCommand = Command::RDA;
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else
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nextCommand = Command::WRA;
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}
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else
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{
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assert(currentPayload->is_read() || currentPayload->is_write());
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if (currentPayload->is_read())
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nextCommand = Command::RD;
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else
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nextCommand = Command::WR;
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}
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}
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else // row miss
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nextCommand = Command::PREPB;
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}
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timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
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return timeToSchedule;
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}
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}
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else
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return timeToSchedule;
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}
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BankMachineClosedAdaptive::BankMachineClosedAdaptive(const Configuration& config, const SchedulerIF& scheduler,
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const CheckerIF& checker, Bank bank)
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: BankMachine(config, scheduler, checker, bank) {}
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sc_time BankMachineClosedAdaptive::start()
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{
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timeToSchedule = sc_max_time();
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nextCommand = Command::NOP;
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if (!(sleeping || blocked))
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{
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tlm_generic_payload* newPayload = scheduler.getNextRequest(*this);
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if (newPayload == nullptr)
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{
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return timeToSchedule;
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}
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else
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{
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assert(!keepTrans || currentPayload != nullptr);
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if (keepTrans)
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{
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if (DramExtension::getRow(*newPayload) == openRow)
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currentPayload = newPayload;
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}
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else
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{
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currentPayload = newPayload;
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}
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if (state == State::Precharged) // bank precharged
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nextCommand = Command::ACT;
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else if (state == State::Activated)
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{
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if (DramExtension::getRow(*currentPayload) == openRow) // row hit
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{
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if (scheduler.hasFurtherRowHit(bank, openRow, currentPayload->get_command()))
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{
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assert(currentPayload->is_read() || currentPayload->is_write());
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if (currentPayload->is_read())
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nextCommand = Command::RD;
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else
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nextCommand = Command::WR;
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}
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else
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{
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assert(currentPayload->is_read() || currentPayload->is_write());
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if (currentPayload->is_read())
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nextCommand = Command::RDA;
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else
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nextCommand = Command::WRA;
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}
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}
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else // row miss, can happen when RD/WR mode is switched
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nextCommand = Command::PREPB;
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}
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timeToSchedule = checker.timeToSatisfyConstraints(nextCommand, *currentPayload);
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return timeToSchedule;
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}
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}
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else
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return timeToSchedule;
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}
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