839 lines
26 KiB
Markdown
839 lines
26 KiB
Markdown
de.uni-kl.ems.dram.vp.system
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============================
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**DRAMSys** [1] is a flexible DRAM subsystem design space exploration
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framework that consists of models reflecting the DRAM functionality, power
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consumption, temperature behaviour and retention time errors.
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## Basic Setup
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Open a terminal window, go to your home directory, create a directory for your
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projects and change to it.
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``` bash
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$ cd
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$ mkdir projects
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$ cd projects
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```
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Clone the repository.
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``` bash
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$ git clone --recursive https://<user>@git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system.git
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```
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The *--recursive* flag tells git to initialize all submodules within the
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repository. **DRAMPower** [2], **tinyxml** and **icewrapper** are examples
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third party repositories that were embedded within the source tree as
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submodules.
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It is possible to work with a **fork** of the official codebase. In that case,
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after pushing changes into your fork you should create a **pull request** in
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order to get your changes merged into to the official codebase.
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``` bash
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$ git clone --recursive https://<user>@git.rhrk.uni-kl.de/<user>/dram.vp.system.git
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```
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After cloning go to the project directory.
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``` bash
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$ cd dram.vp.system
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```
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When working with a fork, the official repository must be added as a remote for
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your fork.
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``` bash
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$ git remote add upstream https://<user>@git.rhrk.uni-kl.de/EIT-Wehn/dram.vp.system.git
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$ git remote -v
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```
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Also, after a pull request being accepted and merged into the official
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repository you should get your fork updated.
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``` bash
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$ git fetch upstream
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$ git checkout master
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$ git merge upstream/master
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$ git push origin HEAD
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```
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### Dependencies
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Make sure you have properly installed in your system the required libraries.
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They are:
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- SystemC 2.3.1 and TLM 2.0
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The sources can be downloaded from http://accellera.org/downloads/standards/systemc.
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For installation instructions see the installation notes file contained in
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the release package.
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- qwt-6.1.3
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```bash
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$ svn checkout svn://svn.code.sf.net/p/qwt/code/branches/qwt-6.1
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$ cd qwt-6.1
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$ qmake qwt.pro
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$ make
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$ sudo make install
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```
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For further information refer to http://qwt.sourceforge.net/
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- python3.5
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In Debian like distros:
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```bash
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$ sudo apt-get install python3.5
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$ sudo apt-get install python3.5-dev
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```
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- libboost_filesystem and libboost_system
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In Debian like distros:
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```bash
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$ sudo apt-get install libboost-all-dev
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```
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- Others
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Some basic libraries may be already installed in your system. If not you can
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install the following packages or equivalent ones for your distro. In Debian
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like distros:
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```bash
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$ sudo apt-get install libc6
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$ sudo apt-get install libstdc++6
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$ sudo apt-get install sqlite3
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$ sudo apt-get install libsqlite3-dev
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$ sudo apt-get install libqt5gui5
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$ sudo apt-get install libqt5sql5
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$ sudo apt-get install libqt5widgets5
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$ sudo apt-get install libqt5core5a
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```
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To grant flexibility to the user the paths where to find some essential
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libraries and headers can be specified with environment variables. You can add
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such variables to you ~/.bashrc file or equivalent.
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```bash
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# SystemC home and target architecture
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export SYSTEMC_HOME=<path>
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export SYSTEMC_TARGET_ARCH=<[linux, linux64, macosx, macosx64, ...]>
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# DRAMSys libraries and headers
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export PYTHON_HOME=<path>
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export PYTHON_HEADERS=<path>
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export LIBQWT_HOME=<path>
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export LIBQWT_HEADERS=<path>
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export LIBBOOST_HOME=<path>
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export LIBBOOST_HEADERS=<path>
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```
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Users interested in thermal simulation can also add some extra environment
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variables:
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```bash
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# Necessary for thermal simulation
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export LIBTHREED_ICE_HOME=<path>
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export LIBSUPERLU_HOME=<path>
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```
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### Buiding with QTCreator
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Execute the *QTCreator*.
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``` bash
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$ qtcreator &
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```
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Use the menu bar and open the DRAMSys project.
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**File -> Open Project -> dram.vp.system/DRAMSys/dram.vp.system.pro**
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When you open the project for the first time a configuration window pops-up.
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Then click in **Configure Project** and after that **Build** the project.
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To speedup the building process one can use the additional **make** option
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**-j[jobs]**. The command line below returns a good number to be passed to
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make as the number of jobs that can run simultaneously to improve the building
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time.
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``` bash
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$ cat /proc/cpuinfo | grep processor | wc -l
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```
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In the left bar go to **Projects -> Build & Run -> Build Steps -> Make**.
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Click in **Details** then **Make arguments** and add **-j** followed by the
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number you got.
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### Building without QTCreator
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In case you prefer a command line interface to the QTCreator GUI you can also
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use **qmake** to generate a Makefile and then compile the project.
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``` bash
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$ mkdir build
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$ cd build
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$ qmake ../DRAMSys/dram.vp.system.pro
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$ make
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```
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The compilation generates executable binary files **dramSys** and
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**traceAnalyzer** that can be found inside sub-directories.
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From the build directory use the commands below to execute DRAMSys.
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``` bash
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$ cd simulator
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$ ./dramSys
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```
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From the build directory use the commands below to execute the traceAnalyzer.
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``` bash
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$ cd analyzer
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$ ./traceAnalyzer
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```
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Note for GNU/Linux users:
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If your keyboard shortcuts (e.g., Ctrl+O, Ctrl+T) from the traceAnalyzer menu
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appear as "ghost" and pressing any of the key combinations has no effect then
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you may need to set an extra environment variable:
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``` bash
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$ export QT_QPA_PLATFORMTHEME=qgnomeplatform
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$ ./traceAnalyzer
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```
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### Building on OSX
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- Install SystemC in /opt (as usual with ./configure --prefix=/opt/systemc; make; make install;).
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- Install the required python over macports:
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``` bash
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sudo port install python34
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```
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- Install the QtCreator via macports:
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``` bash
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sudo port install qt5-creator qt5
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```
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- Install the QWT manually to /opt/qwt, then do:
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``` bash
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cd /Library/Frameworks
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sudo ln -s /opt/qwt-6.1.2/lib/qwt.framework/ .
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```
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- The boost library must be installed manually, since the macports version is not compatible with DRAMSys:
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In your “user-config.jam”, put this:
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``` bash
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using clang : 11
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: "/usr/bin/clang++"
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: <cxxflags>"-std=c++11 -stdlib=libc++" <linkflags>"-stdlib=libc++""
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;
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```
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Then compile and install it:
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``` bash
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./b2 toolset=clang-11
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sudo ./b2 install
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```
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DRAMSys and Analyzer only runs if the following is configured in the project settings:
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```
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DYLD_LIBRARY_PATH=/opt/boost/lib
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LIBQWT_HEADERS=/opt/local/include
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LIBQWT_HOME=/opt/local/lib
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PYTHON_HEADERS=/opt/local/include
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PYTHON_HOME=/opt/local/lib
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SYSTEMC_TARGET_ARCH=macosx64
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```
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For the trace analyzer the file /opt/local/Library/Frameworks/Python.framework/Versions/3.4/include/python3.4m/pyport.h has to be changed like this: https://trac.macports.org/attachment/ticket/44288/issue10910-workaround.txt
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### DRAMSys Thermal Simulation
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The thermal simulation is performed by a **3D-ICE** [8] server accessed
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through the network. Therefore users interested in thermal simulation during
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their DRAMSys simulations need to make sure they have a 3D-ICE server up and
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running before starting. For more information about 3D-ICE visit the official
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website http://esl.epfl.ch/3D-ICE.
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#### Installing the lastest 3D-ICE version
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Download the lastest version. Make sure you got version 2.2.6 or greater:
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``` bash
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$ wget http://esl.epfl.ch/files/content/sites/esl/files/3dice/releases/3d-ice-latest.zip
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$ tar -xvzf 3d-ice-latest.zip
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```
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Install SuperLU dependencies:
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``` bash
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$ sudo apt-get install build-essential git bison flex libblas-dev
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```
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Download and install SuperLU:
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``` bash
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$ wget http://crd.lbl.gov/~xiaoye/SuperLU/superlu_4.3.tar.gz
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$ tar xvfz superlu_4.3.tar.gz
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$ cd SuperLU_4.3/
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$ cp MAKE_INC/make.linux make.inc
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```
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Make sure the SuperLUroot variable in ./make.inc is properly set (in my case $(HOME)/repos/).
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``` bash
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SuperLUroot = $(HOME)/repos/SuperLU_4.3
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```
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Compile the library:
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``` bash
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$ make superlulib
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```
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Download and install bison-2.4.1:
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``` bash
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$ wget http://ftp.gnu.org/gnu/bison/bison-2.4.1.tar.gz
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$ tar xvzf bison-2.4.1.tar.gz
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$ cd bison-2.4.1
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$ ./configure --program-suffix=-2.4.1
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$ make
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$ sudo make install
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```
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Go to the 3d-ice directory:
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``` bash
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$ cd 3d-ice-2.2.6
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```
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Open the file makefile.def and set some variables. Set the correct path to the
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SuperLU library you just compiled (in my case $(HOME)/repos/):
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``` bash
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SLU_MAIN = $(HOME)/repos/SuperLU_$(SLU_VERSION)
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```
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Set the YACC variable to bison-2.4.1:
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``` bash
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YACC = bison-2.4.1
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```
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Set the systemC architecture and main folder variables:
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``` bash
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SYSTEMC_ARCH = [linux,linux64]
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SYSTEMC_MAIN = $(HOME)/repos/systemc-$(SYSTEMC_VERSION)
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```
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Compile 3D-ICE with SystemC/TLM2.0 support:
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``` bash
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$ make clean
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$ make SYSTEMC_WRAPPER=y
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```
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#### Running DRAMSys
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Before starting make sure you have a **clean repository** without any previous
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automatic generated Makefiles. One way to ensure this is by running the
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command below inside your DRAMSys repository, but keep in mind that
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**untracked files and directories will be removed** from the repository.
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``` bash
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$ git clean -fdx
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```
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This feature can be enabled via an environment variable.
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``` bash
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$ export THERMALSIM=true
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$ qtcreator &
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```
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or
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``` bash
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$ mkdir build
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$ cd build
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$ export THERMALSIM=true
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$ qmake ../DRAMSys/dram.vp.system.pro
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$ make
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```
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Before starting DRAMSys it is necessary to run the 3D-ICE server passing to it
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two arguments: a suitable configuration file and an Internet socket port
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number. And then wait until the server is ready to receive requests.
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``` bash
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$ 3D-ICE-Server <stack file> <port>
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Preparing stk data ... done !
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Preparing thermal data ... done !
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Creating socket ... done !
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Waiting for client ... done !
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```
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The IP address and the port number related to the server shall be informed in
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DRAMSys' configuration to subsequent use by DRAMSys to access the thermal
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simulation server.
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#### Usage Example
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The DRAMSys' main configuration file is presented below.
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``` xml
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<simulation>
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<!-- General Simulator Configuration (used for all simulation setups) -->
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<simconfig>
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<Debug value="1" />
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<DatabaseRecording value="1" />
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<PowerAnalysis value="1" />
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<NumberOfTimeWindows value="1000" />
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<NumberOfTracePlayers value="1"/>
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<NumberOfMemChannels value="4"/>
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<ControllerCoreDisableRefresh value="0"/>
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<ThermalSimulation value="1"/>
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<SimulationProgressBar value="1"/>
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</simconfig>
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<!-- Temperature Simulator Configuration (used for all simulation setups) -->
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<thermalsimconfig>
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<TemperatureScale value="Celsius" />
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<StaticTemperatureDefaultValue value="23" />
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<ThermalSimPeriod value="100" />
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<ThermalSimUnit value="us" />
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<PowerInfoFile value="../../DRAMSys/simulator/resources/configs/thermalsim/powerInfo.xml"/>
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<IceServerIp value="127.0.0.1" />
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<IceServerPort value="11880" />
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<SimPeriodAdjustFactor value="10" />
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<NPowStableCyclesToIncreasePeriod value="5" />
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<GenerateTemperatureMap value="1" />
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<GeneratePowerMap value="1" />
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</thermalsimconfig>
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<memspecs>
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<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/WideIO.xml"></memspec>
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</memspecs>
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<addressmappings>
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<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
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</addressmappings>
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<memconfigs>
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<memconfig src="../../DRAMSys/simulator/resources/configs/memconfigs/fr_fcfs.xml"/>
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</memconfigs>
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<tracesetups>
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<tracesetup id="fifo">
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<device clkMhz="1000">../../../tests/error/test_error.stl</device>
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</tracesetup>
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</tracesetups>
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</simulation>
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```
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Enable the error model in fr_fcfs.xml.
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``` xml
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<memconfig>
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<BankwiseLogic value="0"/>
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<OpenPagePolicy value="1" />
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<MaxNrOfTransactions value="8" />
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<Scheduler value="FR_FCFS" />
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<Capsize value="5" />
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<PowerDownMode value="NoPowerDown"/>
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<PowerDownTimeout value="100" />
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<!-- Error Model: -->
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<ErrorChipSeed value="42" />
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<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
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<!-- Modes: NoStorage, Store (store data without errormodel), ErrorModel (store data with errormodel) -->
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<StoreMode value="ErrorModel" />
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</memconfig>
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```
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Generate the input trace file for DRAMSys.
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``` bash
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$ cd DRAMSys/tests/error/
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$ ./generateErrorTest.pl > test_error.stl
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```
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Start the 3D-ICE server providing the stack file and the port number.
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``` bash
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$ cd DRAMSys/simulator/resources/configs/thermalsim
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$ 3D-ICE-Server stack.stk 11880
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```
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In another terminal or terminal tab start DRAMSys. Here the program's output
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is redirected to a file.
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``` bash
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$ cd build/simulator/
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$ ./dramSys > output
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```
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### DRAMSys Configuration
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The **dramSys** executable supports one argument which is a XML file that
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contains configurable aspects of the desired simulation. If no argument is
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passed through the command line a default configuration file will be loaded.
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The XML code below shows a typic configuration:
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``` xml
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<simulation>
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<!-- General Simulator Configuration (used for all simulation setups) -->
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<simconfig>
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<Debug value="1"/>
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<DatabaseRecording value="1"/>
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<PowerAnalysis value="1"/>
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<NumberOfTimeWindows value="1000" />
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<NumberOfTracePlayers value="5"/>
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<NumberOfMemChannels value="1"/>
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<ControllerCoreDisableRefresh value="0"/>
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<ThermalSimulation value="0"/>
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<SimulationProgressBar value="1"/>
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</simconfig>
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<!-- Temperature Simulator Configuration (used for all simulation setups) -->
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<thermalsimconfig>
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<TemperatureScale value="Celsius" />
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<StaticTemperatureDefaultValue value="89" />
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<ThermalSimPeriod value="100" />
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<ThermalSimUnit value="ms" />
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<PowerInfoFile value="../../DRAMSys/simulator/resources/configs/thermalsim/power_thresholds.xml"/>
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<IceServerIp value="127.0.0.1" />
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<IceServerPort value="11880" />
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<SimPeriodAdjustFactor value="10" />
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<NPowStableCyclesToIncreasePeriod value="5" />
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<GenerateTemperatureMap value="1" />
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<GeneratePowerMap value="1" />
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</thermalsimconfig>
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<!-- Memory Specifications -->
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<memspecs>
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<memspec src="../../DRAMSys/simulator/resources/configs/memspecs/WideIO.xml"></memspec>
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</memspecs>
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<!-- Address Mappings -->
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<addressmappings>
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<addressmapping src="../../DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml"></addressmapping>
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</addressmappings>
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<!-- Memory Configurations -->
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<memconfigs>
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<memconfig src="../../DRAMSys/simulator/resources/configs/memconfigs/fifo.xml"/>
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</memconfigs>
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<!-- Trace Setups -->
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<tracesetups>
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<!-- Multiple trace setups are allowed for the same simulation setup -->
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<tracesetup id="fifo">
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<!--
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Specify here a trace file for each of the trace players. Trace
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players without a file will not generate transactions.
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It is also possible to choose "cklMhz" and the "bl" for every
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player.
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-->
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<device clkMhz="200">voco2.stl</device>
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<device clkMhz="200">voco2.stl</device>
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<device clkMhz="200">voco2.stl</device>
|
|
</tracesetup>
|
|
</tracesetups>
|
|
|
|
</simulation>
|
|
```
|
|
|
|
Some configuration fields reference other XML files which contain more
|
|
specialized chunks of the configuration like memory specification, address
|
|
mapping and memory configurations.
|
|
|
|
The XML configuration files are parsed by the program and the configuration
|
|
details extracted are assigned to the correspondent attributes of the internal
|
|
configuration structure.
|
|
|
|
#### Simulation Setups
|
|
|
|
Every possible combination of memory specification, address mapping and memory
|
|
configuration corresponds to a **simulation setup**.
|
|
|
|
DRAMSys executes all the **trace setups** listed in the configuration file for
|
|
each of the simulation setups.
|
|
|
|
A single **trace setup** is composed of an id string and one or more
|
|
**devices**.
|
|
|
|
The **device** configuration consists of two configuration fields - clkMhz
|
|
(operation frequency for this device) and bl (burst length) - and a
|
|
**trace file**.
|
|
|
|
A **trace file** is a pre-recorded file containing memory transactions. Each
|
|
memory transaction has a timestamp that tells the simulator when it shall
|
|
happen, a transaction type (e.g. read, write) and a memory address.
|
|
|
|
A **trace player** is **equivalent** to a bus master **device** (i.e. a device
|
|
that locks a bus and generates memory transactions). By adding device elements
|
|
into the trace setup section one can specify the operation frequency, the
|
|
burst length and the trace file to be used by trace players.
|
|
|
|
Trace players without a corresponding device configuration do not generate
|
|
transactions.
|
|
|
|
**DRAMSys** executes all the simulation setups within the configuration file
|
|
providing **flexibility** for **exhaustive explorations.**
|
|
|
|
#### Configuration File Sections
|
|
|
|
The main configuration file is divided into self-contained sections, each of
|
|
these sections is a set of logically related configuration aspects for the
|
|
simulation.
|
|
|
|
Below are listed the configuration sections and configuration fields.
|
|
|
|
- **Simulator Configuration**
|
|
- *Debug* (boolean)
|
|
- "1": enables debug output on console
|
|
- "0": disables debug output
|
|
- *DatabaseRecording* (boolean)
|
|
- "1": enables trace file recording for the trace analyser tool
|
|
- "0": disables trace file recording
|
|
- *PowerAnalysis* (boolean)
|
|
- "1": enables live power analysis with the DRAMPower tool
|
|
- "0": disables power analysis
|
|
- *NumberOfTimeWindows* (int)
|
|
- number of time windows used to evaluate average bandwidth and average power consumption
|
|
- *NumberOfTracePlayers* (unsigned int)
|
|
- Number of trace players
|
|
- *NumberOfMemChannels* (unsigned int)
|
|
- Number of memory channels
|
|
- *ControllerCoreDisableRefresh* (boolean)
|
|
- "1": disables refreshes
|
|
- "0": normal operation (refreshes enabled)
|
|
- *ThermalSimulation* (boolean)
|
|
- "1": enables thermal simulation
|
|
- "0": static temperature during simulation
|
|
- *SimulationProgressBar* (boolean)
|
|
- "1": enables the simulation progress bar
|
|
- "0": disables the simulation progress bar
|
|
|
|
- **Temperature Simulator Configuration**
|
|
- *TemperatureScale* (string)
|
|
- "Celsius"
|
|
- "Fahrenheit"
|
|
- "Kelvin"
|
|
- *StaticTemperatureDefaultValue* (int)
|
|
- Temperature value for simulations with static temperature
|
|
- *ThermalSimPeriod* (double)
|
|
- Period of the thermal simulation
|
|
- *ThermalSimUnit* (string)
|
|
- "s": seconds
|
|
- "ms": millisecond
|
|
- "us": microseconds
|
|
- "ns": nanoseconds
|
|
- "ps": picoseconds
|
|
- "fs": femtoseconds
|
|
- *PowerInfoFile* (string)
|
|
- File containing power related information: devices identifiers, initial power values and power thresholds.
|
|
- *IceServerIp* (string)
|
|
- 3D-Ice server IP address
|
|
- *IceServerPort* (unsigned int)
|
|
- 3D-Ice server port
|
|
- *SimPeriodAdjustFactor* (unsigned int)
|
|
- When substantial changes in power occur (i.e., changes that exceed the thresholds), then the simulation period will be divided by this number causing the thermal simulation to be executed more often.
|
|
- *NPowStableCyclesToIncreasePeriod* (unsigned int)
|
|
- Wait this number of thermal simulation cycles with power stability (i.e., changes that do not exceed the thresholds) to start increasing the simulation period back to its configured value.
|
|
- *GenerateTemperatureMap* (boolean)
|
|
- "1": generate temperature map files during thermal simulation
|
|
- "0": do not generate temperature map files during thermal simulation
|
|
- *GeneratePowerMap* (boolean)
|
|
- "1": generate power map files during thermal simulation
|
|
- "0": do not generate power map files during thermal simulation
|
|
|
|
- **Memory Specification**
|
|
|
|
A file with memory specifications. This information comes from datasheet and
|
|
usually does not change.
|
|
|
|
- **Address Mapping**
|
|
|
|
XML files describe the address mapping to be used in the simulation.
|
|
|
|
The file [am_wideio.xml](DRAMSys/simulator/resources/configs/amconfigs/am_wideio.xml) is
|
|
a good example.
|
|
|
|
``` xml
|
|
<!-- Row Bank Column -->
|
|
|
|
<addressmapping>
|
|
<channel from="27" to="28" />
|
|
<row from="14" to="26" />
|
|
<bank from="11" to="13" />
|
|
<column from="4" to="10" />
|
|
<bytes from="0" to="3" />
|
|
</addressmapping>
|
|
```
|
|
|
|
|
|
|
|
``` xml
|
|
<!-- Bank Row Column -->
|
|
|
|
<addressmapping>
|
|
<channel from="27" to="28" />
|
|
<bank from="24" to="26" />
|
|
<row from="11" to="23" />
|
|
<column from="4" to="10" />
|
|
<bytes from="0" to="3" />
|
|
</addressmapping>
|
|
```
|
|
|
|
|
|
|
|
- **Memory Configuration**
|
|
|
|
The content of [fifo.xml](DRAMSys/simulator/resources/configs/memconfigs/fifo.xml) is
|
|
presented below as an example.
|
|
|
|
``` xml
|
|
<memconfig>
|
|
<BankwiseLogic value="0"/>
|
|
<OpenPagePolicy value="1"/>
|
|
<MaxNrOfTransactions value="8"/>
|
|
<Scheduler value="FIFO_STRICT"/>
|
|
<Capsize value="5"/>
|
|
<PowerDownMode value="NoPowerDown"/>
|
|
<PowerDownTimeout value="100"/>
|
|
<!-- Error Modelling -->
|
|
<ErrorChipSeed value="42"/>
|
|
<ErrorCSVFile value="../../DRAMSys/simulator/src/error/error.csv" />
|
|
<StoreMode value="NoStorage"/>
|
|
</memconfig>
|
|
```
|
|
|
|
- *BankwiseLogic* (boolean)
|
|
- "1": perform bankwise-refresh [3] and bankwise-powerdown [4]
|
|
- "0": do not perform bankwise operations
|
|
- *OpenPagePolicy* (boolean)
|
|
- "1": use open page precharge policy
|
|
- "0": do not use open page precharge policy
|
|
- *MaxNrOfTransactions* (unsigned int)
|
|
- Maximum number of transactions.
|
|
- *Scheduler* (string)
|
|
- "FIFO": first in, first out
|
|
- "FIFO_STRICT": out-of-order treatment of queue elements not allowed
|
|
- "FR_FCFS": first-come, first-served
|
|
- *Capsize* (unsigned int)
|
|
- Capacitor cell size.
|
|
- *PowerDownMode* (enum EPowerDownMode)
|
|
- "NoPowerDown": no power down mode (active idle)
|
|
- "Staggered": staggered power down policy [5]
|
|
- "TimeoutPDN": precharge idle
|
|
- "TimeoutSREF": self refresh
|
|
- *Buswidth* (unsigned int)
|
|
- Bus width in bits.
|
|
- *ReadWriteGrouping* (boolean)
|
|
- "1": enable read writing grouping
|
|
- "0": disable read writing grouping
|
|
- *ReorderBuffer* (boolean)
|
|
- "1": use reordering buffer
|
|
- "0": do not use reordering buffer
|
|
- *ErrorChipSeed* (unsigned int)
|
|
- Seed to initialize the random error generator.
|
|
- *ErrorCSVFile* (string)
|
|
- CSV file with error injection information.
|
|
- *StoreMode* (enum StorageMode)
|
|
- "NoStorage": no storage
|
|
- "Store": store data without error model
|
|
- "ErrorModel": store data with error model [6]
|
|
|
|
- **Trace Setups**
|
|
- *id* (string)
|
|
- Trace setup id. Two kinds of output files are generated by DRAMSys:
|
|
SQLite databases containing transactions related to each memory channel
|
|
(.tdb) and a text file (.txt) with the program output. The base name for
|
|
these files comes from this field.
|
|
- *clkMhz* (unsigned int)
|
|
- Speed of the trace player
|
|
- *bl* (unsigned int)
|
|
- Burst length
|
|
- *trace file*
|
|
- A pre-recorded file containing memory transactions to be executed by a
|
|
trace player.
|
|
|
|
Some attributes are self-explanatory while others require some previous
|
|
knowhow of memory technologies.
|
|
|
|
Resources of the simulator are available inside of the **resources** directory
|
|
and its sub-directories.
|
|
|
|
``` bash
|
|
$ cd DRAMSys/simulator/resources
|
|
```
|
|
|
|
A description of the content each directory follows.
|
|
|
|
- **resources**
|
|
- **configs**: XML files used for configure specific details of the simulation.
|
|
- am_configs: address mapping configuration
|
|
- memconfigs: memory configuration
|
|
- memspecs: configuration related to the memory technology
|
|
- **scripts**: useful tools like address scrambler, trace analyser, database
|
|
creator, etc.
|
|
- **simulations**: global configuration
|
|
- **traces**: trace files for simulations. They contain accesses to memory
|
|
in certain known scenarios.
|
|
|
|
#### References
|
|
|
|
[1] TLM Modelling of 3D Stacked Wide I/O DRAM Subsystems, A Virtual Platform for Memory Controller Design Space Exploration
|
|
M. Jung, C. Weis, N. Wehn, K. Chandrasekar. International Conference on High-Performance and Embedded Architectures and Compilers 2013 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2013, Berlin.
|
|
|
|
[2] DRAMPower: Open-source DRAM Power & Energy Estimation Tool
|
|
Karthik Chandrasekar, Christian Weis, Yonghui Li, Sven Goossens, Matthias Jung, Omar Naji, Benny Akesson, Norbert Wehn, and Kees Goossens
|
|
URL: http://www.drampower.info
|
|
|
|
[3] Energy Optimization in 3D MPSoCs with Wide-I/O DRAM
|
|
M. Sadri, M. Jung, C. Weis, N. Wehn, L. Benini. Conference Design, Automation and Test in Europe (DATE), March, 2014, Dresden, Germany.
|
|
|
|
[4] DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework
|
|
M. Jung, C. Weis, N. Wehn. Accepted for publication, IPSJ Transactions on System LSI Design Methodology (T-SLDM), October, 2015.
|
|
|
|
[5] Optimized Active and Power-Down Mode Refresh Control in 3D-DRAMs
|
|
M. Jung, M. Sadri, C. Weis, N. Wehn, L. Benini., VLSI-SoC, October, 2014, Playa del Carmen, Mexico.
|
|
|
|
[6] Retention Time Measurements and Modelling of Bit Error Rates of WIDE-I/O DRAM in MPSoCs
|
|
C. Weis, M. Jung, P. Ehses, C. Santos, P. Vivet, S. Goossens, M. Koedam, N. Wehn. Accepted for publication, IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France
|
|
|
|
[7] http://www.uni-kl.de/3d-dram/publications/
|
|
|
|
[8] A Sridhar, A Vincenzi, D Atienza, T Brunschwiler, 3D-ICE: a compact
|
|
thermal model for early-stage design of liquid-cooled ICs, IEEE Transactions
|
|
on Computers (TC 2013, accepted for publication).
|
|
|
|
[9] A Sridhar, A Vincenzi, M Ruggiero, T Brunschwiler, D Atienza, 3D-ICE: Fast
|
|
compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling,
|
|
Proceedings of the 2010 International Conference on Computer-Aided Design
|
|
(ICCAD 2010), San Jose, CA, USA, November 7-11 2010.
|
|
|
|
[10] A Sridhar, A Vincenzi, M Ruggiero, T Brunschwiler, D Atienza, Compact
|
|
transient thermal model for 3D ICs with liquid cooling via enhanced heat
|
|
transfer cavity geometries, Proceedings of the 16th International Workshop on
|
|
Thermal Investigations of ICs and Systems (THERMINIC'10), Barcelona, Spain,
|
|
6-8 October, 2010.
|
|
|
|
[11] http://esl.epfl.ch/3D-ICE
|
|
|