Derek Christ 6861576550 Implement tCCDR for HBM2 and fix bug with SID

2025-02-21 14:18:30 +01:00

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expected

Have a one cycle END_RESP delay in the standard initiator

2025-01-24 14:43:06 +01:00

traces

Add regression test files.

2023-01-30 15:45:10 +01:00

hbm2-example.json

Implement tCCDR for HBM2 and fix bug with SID

2025-02-21 14:18:30 +01:00

hbm2.txt

Add regression test for DDR5

2023-08-15 10:58:10 +02:00