229 lines
6.3 KiB
JSON
229 lines
6.3 KiB
JSON
{
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"simulation": {
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"addressmapping": {
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"BANKGROUP_BIT": [
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13,
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14,
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15
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],
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"BANK_BIT": [
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16
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],
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"BYTE_BIT": [
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0,
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1
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],
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"CHANNEL_BIT": [
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33
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],
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"COLUMN_BIT": [
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2,
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10,
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11,
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12
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],
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"ROW_BIT": [
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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26,
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27,
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28,
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29,
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30,
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31,
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32
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]
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},
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"mcconfig": {
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"Arbiter": "Simple",
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"CmdMux": "Oldest",
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"MaxActiveTransactions": 128,
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"PagePolicy": "Open",
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"PowerDownPolicy": "NoPowerDown",
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"RefreshManagement": false,
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"RefreshMaxPostponed": 0,
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"RefreshMaxPulledin": 0,
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"RefreshPolicy": "AllBank",
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"RequestBufferSize": 8,
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"RespQueue": "Fifo",
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"Scheduler": "FrFcfs",
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"SchedulerBuffer": "Bankwise"
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},
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"memspec": {
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"memarchitecturespec": {
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"RAADEC": 16,
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"RAAIMT": 32,
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"RAAMMT": 96,
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"burstLength": 16,
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"cmdMode": 1,
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"dataRate": 2,
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"nbrOfBankGroups": 8,
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"nbrOfBanks": 16,
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"nbrOfChannels": 2,
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"nbrOfColumns": 2048,
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"nbrOfDIMMRanks": 1,
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"nbrOfDevices": 8,
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"nbrOfLogicalRanks": 1,
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"nbrOfPhysicalRanks": 1,
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"nbrOfRanks": 1,
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"nbrOfRows": 65536,
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"RefMode": 1,
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"width": 4,
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"maxBurstLength": 16
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},
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"memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
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"memoryType": "DDR5",
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"memtimingspec": {
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"ACTPDEN": 2,
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"CCD_L_WR2_slr": 16,
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"CCD_L_WR_slr": 32,
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"CCD_L_slr": 8,
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"CCD_M_WR_slr": 32,
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"CCD_M_slr": 8,
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"CCD_S_WR_slr": 8,
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"CCD_S_slr": 8,
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"CCD_WR_dlr": 0,
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"CCD_WR_dpr": 0,
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"CCD_dlr": 0,
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"CPDED": 8,
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"FAW_dlr": 0,
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"FAW_slr": 32,
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"PD": 12,
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"PPD": 2,
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"PRPDEN": 2,
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"RAS": 52,
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"RCD": 22,
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"RDDQS": 0,
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"REFI1": 6240,
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"REFI2": 3120,
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"REFISB": 1560,
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"REFPDEN": 2,
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"REFSBRD_dlr": 0,
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"REFSBRD_slr": 48,
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"RFC1_dlr": 0,
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"RFC1_dpr": 0,
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"RFC1_slr": 312,
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"RFC2_dlr": 0,
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"RFC2_dpr": 0,
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"RFC2_slr": 208,
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"RFCsb_dlr": 0,
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"RFCsb_slr": 184,
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"RL": 22,
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"RP": 22,
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"RPRE": 1,
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"RPST": 0,
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"RRD_L_slr": 8,
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"RRD_S_slr": 8,
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"RRD_dlr": 0,
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"RTP": 12,
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"RTRS": 2,
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"WL": 20,
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"WPRE": 2,
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"WPST": 0,
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"WR": 48,
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"WTR_L": 16,
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"WTR_M": 16,
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"WTR_S": 4,
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"XP": 12,
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"tCK": 625e-12
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},
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"mempowerspec": {
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"vdd": 0.0,
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"idd0": 0.0,
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"idd2n": 0.0,
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"idd3n": 0.0,
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"idd4r": 0.0,
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"idd4w": 0.0,
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"idd5c": 0.0,
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"idd6n": 0.0,
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"idd2p": 0.0,
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"idd3p": 0.0,
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"vpp": 0.0,
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"ipp0": 0.0,
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"ipp2n": 0.0,
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"ipp3n": 0.0,
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"ipp4r": 0.0,
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"ipp4w": 0.0,
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"ipp5c": 0.0,
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"ipp6n": 0.0,
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"ipp2p": 0.0,
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"ipp3p": 0.0,
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"idd5b": 0.0,
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"idd5f": 0.0,
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"ipp5b": 0.0,
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"ipp5f": 0.0,
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"vddq": 0.0,
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"iBeta_vdd": 0.0,
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"iBeta_vpp": 0.0
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},
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"bankwisespec": {
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"factRho": 1.0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12
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},
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"dataratespec": {
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"ca_bus_rate": 2,
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"dq_bus_rate": 2,
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"dqs_bus_rate": 2
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}
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},
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"simconfig": {
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"AddressOffset": 0,
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"CheckTLM2Protocol": false,
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"DatabaseRecording": true,
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"Debug": false,
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"EnableWindowing": false,
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"PowerAnalysis": false,
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"SimulationName": "ddr5",
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"SimulationProgressBar": true,
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"StoreMode": "NoStorage",
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"UseMalloc": false,
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"WindowSize": 1000
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},
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"simulationid": "ddr5-example",
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"tracesetup": [
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{
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"type": "player",
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"clkMhz": 1600,
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"dataLength": 64,
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"name": "traces/trace_test3.stl"
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}
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]
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}
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}
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