{
    "simulation": {
        "addressmapping": {
            "BANKGROUP_BIT": [
                13,
                14,
                15
            ],
            "BANK_BIT": [
                16
            ],
            "BYTE_BIT": [
                0,
                1
            ],
            "CHANNEL_BIT": [
                33
            ],
            "COLUMN_BIT": [
                2,
                3,
                4,
                5,
                6,
                7,
                8,
                9,
                10,
                11,
                12
            ],
            "ROW_BIT": [
                17,
                18,
                19,
                20,
                21,
                22,
                23,
                24,
                25,
                26,
                27,
                28,
                29,
                30,
                31,
                32
            ]
        },
        "mcconfig": {
            "Arbiter": "Simple",
            "CmdMux": "Oldest",
            "MaxActiveTransactions": 128,
            "PagePolicy": "Open",
            "PowerDownPolicy": "NoPowerDown",
            "RefreshManagement": false,
            "RefreshMaxPostponed": 0,
            "RefreshMaxPulledin": 0,
            "RefreshPolicy": "AllBank",
            "RequestBufferSize": 8,
            "RespQueue": "Fifo",
            "Scheduler": "FrFcfs",
            "SchedulerBuffer": "Bankwise"
        },
        "memspec": {
            "memarchitecturespec": {
                "RAADEC": 16,
                "RAAIMT": 32,
                "RAAMMT": 96,
                "burstLength": 16,
                "cmdMode": 1,
                "dataRate": 2,
                "nbrOfBankGroups": 8,
                "nbrOfBanks": 16,
                "nbrOfChannels": 2,
                "nbrOfColumns": 2048,
                "nbrOfDIMMRanks": 1,
                "nbrOfDevices": 8,
                "nbrOfLogicalRanks": 1,
                "nbrOfPhysicalRanks": 1,
                "nbrOfRanks": 1,
                "nbrOfRows": 65536,
                "RefMode": 1,
                "width": 4,
                "maxBurstLength": 16
            },
            "memoryId": "JEDEC_2x8x2Gbx4_DDR5-3200A",
            "memoryType": "DDR5",
            "memtimingspec": {
                "ACTPDEN": 2,
                "CCD_L_WR2_slr": 16,
                "CCD_L_WR_slr": 32,
                "CCD_L_slr": 8,
                "CCD_M_WR_slr": 32,
                "CCD_M_slr": 8,
                "CCD_S_WR_slr": 8,
                "CCD_S_slr": 8,
                "CCD_WR_dlr": 0,
                "CCD_WR_dpr": 0,
                "CCD_dlr": 0,
                "CPDED": 8,
                "FAW_dlr": 0,
                "FAW_slr": 32,
                "PD": 12,
                "PPD": 2,
                "PRPDEN": 2,
                "RAS": 52,
                "RCD": 22,
                "RDDQS": 0,
                "REFI1": 6240,
                "REFI2": 3120,
                "REFISB": 1560,
                "REFPDEN": 2,
                "REFSBRD_dlr": 0,
                "REFSBRD_slr": 48,
                "RFC1_dlr": 0,
                "RFC1_dpr": 0,
                "RFC1_slr": 312,
                "RFC2_dlr": 0,
                "RFC2_dpr": 0,
                "RFC2_slr": 208,
                "RFCsb_dlr": 0,
                "RFCsb_slr": 184,
                "RL": 22,
                "RP": 22,
                "RPRE": 1,
                "RPST": 0,
                "RRD_L_slr": 8,
                "RRD_S_slr": 8,
                "RRD_dlr": 0,
                "RTP": 12,
                "RTRS": 2,
                "WL": 20,
                "WPRE": 2,
                "WPST": 0,
                "WR": 48,
                "WTR_L": 16,
                "WTR_M": 16,
                "WTR_S": 4,
                "XP": 12,
                "tCK": 625e-12
            },
            "mempowerspec": {
                "vdd": 0.0,
                "idd0": 0.0,
                "idd2n": 0.0,
                "idd3n": 0.0,
                "idd4r": 0.0,
                "idd4w": 0.0,
                "idd5c": 0.0,
                "idd6n": 0.0,
                "idd2p": 0.0,
                "idd3p": 0.0,
                "vpp": 0.0,
                "ipp0": 0.0,
                "ipp2n": 0.0,
                "ipp3n": 0.0,
                "ipp4r": 0.0,
                "ipp4w": 0.0,
                "ipp5c": 0.0,
                "ipp6n": 0.0,
                "ipp2p": 0.0,
                "ipp3p": 0.0,
                "idd5b": 0.0,
                "idd5f": 0.0,
                "ipp5b": 0.0,
                "ipp5f": 0.0,
                "vddq": 0.0,
                "iBeta_vdd": 0.0,
                "iBeta_vpp": 0.0
            },
            "bankwisespec": {
                "factRho": 1.0
            },
            "memimpedancespec": {
                "ck_termination": true,
                "ck_R_eq": 1e6,
                "ck_dyn_E": 1e-12,
          
                "ca_termination": true,
                "ca_R_eq": 1e6,
                "ca_dyn_E": 1e-12,
          
                "rdq_termination": true,
                "rdq_R_eq": 1e6,
                "rdq_dyn_E": 1e-12,
                "wdq_termination": true,
                "wdq_R_eq": 1e6,
                "wdq_dyn_E": 1e-12,
          
                "wdqs_termination": true,
                "wdqs_R_eq": 1e6,
                "wdqs_dyn_E": 1e-12,
                "rdqs_termination": true,
                "rdqs_R_eq": 1e6,
                "rdqs_dyn_E": 1e-12
            },
            "dataratespec": {
                "ca_bus_rate": 2,
                "dq_bus_rate": 2,
                "dqs_bus_rate": 2
            }
        },
        "simconfig": {
            "AddressOffset": 0,
            "CheckTLM2Protocol": false,
            "DatabaseRecording": true,
            "Debug": false,
            "EnableWindowing": false,
            "PowerAnalysis": false,
            "SimulationName": "ddr5",
            "SimulationProgressBar": true,
            "StoreMode": "NoStorage",
            "UseMalloc": false,
            "WindowSize": 1000
        },
        "simulationid": "ddr5-example",
        "tracesetup": [
            {
                "type": "player",
                "clkMhz": 1600,
                "dataLength": 64,
                "name": "traces/trace_test3.stl"
            }
        ]
    }
}