DRAMSys/DRAMSys/gem5/main.cpp

/*
 * Copyright (c) 2015, University of Kaiserslautern
 * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * 3. Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
 * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Matthias Jung
 *          Christian Menard
 *          Abdul Mutaal Ahmad
 */

#include <iostream>
#include <systemc>
#include <tlm>
#include <string>

#include "DRAMSys.h"
#include "TraceSetup.h"

#include "report_handler.hh"
#include "sc_target.hh"
#include "sim_control.hh"
#include "slave_transactor.hh"
#include "stats.hh"

using namespace std;

class Gem5SimControlDRAMsys: public Gem5SystemC::Gem5SimControl
{
public:
    Gem5SimControlDRAMsys(string configFile) :
        Gem5SystemC::Gem5SimControl("gem5",configFile,0,"MemoryAccess")
    {
    }

    void afterSimulate()
    {
        sc_stop();
    }
};


struct AddressOffset: sc_module
{
    private:
    unsigned long long int offset;

    public:
    tlm_utils::simple_target_socket<AddressOffset> t_socket;
    tlm_utils::simple_initiator_socket<AddressOffset> i_socket;

    AddressOffset(sc_module_name, unsigned long long int o) : offset(o),t_socket("t_socket"),i_socket("i_socket")
    {
        t_socket.register_nb_transport_fw(this,&AddressOffset::nb_transport_fw);
        t_socket.register_transport_dbg(this,&AddressOffset::transport_dbg);
        t_socket.register_b_transport(this,&AddressOffset::b_transport);
        i_socket.register_nb_transport_bw(this,&AddressOffset::nb_transport_bw);
    }

    //Forward Interface
    tlm::tlm_sync_enum nb_transport_fw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay)
    {
        //std::cout << "NB "<< this->name() <<": " << trans.get_address() << " -" << offset;
        trans.set_address(trans.get_address()-offset);
        //std::cout << " = " << trans.get_address() << std::endl;
        return i_socket->nb_transport_fw(trans,phase,delay);
    }

    unsigned int transport_dbg(tlm::tlm_generic_payload &trans)
    {
        // adjust address offset:
        //std::cout << "Debug "<< this->name() <<": " << trans.get_address() << " -" << offset;
        trans.set_address(trans.get_address()-offset);
        //std::cout << " = " << trans.get_address() << std::endl;
        return i_socket->transport_dbg(trans);
    }

    void b_transport(tlm::tlm_generic_payload &trans, sc_time &delay)
    {
        // adjust address offset:
        //std::cout << "B "<< this->name() <<": " << trans.get_address() << " -" << offset;
        trans.set_address(trans.get_address()-offset);
        //std::cout << " = " << trans.get_address() << std::endl;
        i_socket->b_transport(trans, delay);
    }

    //Backward Interface
    tlm::tlm_sync_enum nb_transport_bw(tlm_generic_payload &trans, tlm_phase &phase, sc_time &delay)
    {
        //trans.set_address(trans.get_address()+offset);
        return t_socket->nb_transport_bw(trans,phase,delay);
    }

};

string pathOfFile(string file)
{
    return file.substr(0, file.find_last_of('/'));
}

int sc_main(int argc, char **argv)
{
    SC_REPORT_INFO("sc_main", "Simulation Setup");

    string SimulationXML;
    string gem5ConfigFile;
    string resources;

    if(argc > 1)
    {
        // Get path of resources:
        resources = pathOfFile(argv[0])
                + string("/../../DRAMSys/simulator/resources/");

        SimulationXML = argv[1];
        gem5ConfigFile = argv[2];
    }
    else
    {
        SC_REPORT_FATAL("sc_main","Please provide configuration files");
    }

    // Instantiate DRAMSys:
    DRAMSys dramSys("DRAMSys", SimulationXML, resources);

    // Instantiate gem5:
    Gem5SimControlDRAMsys sim_control(gem5ConfigFile);
#define CHOICE1
//#define CHOICE2
//#define CHOICE3

#ifdef CHOICE1 //If only one gem5 port is used
    Gem5SystemC::Gem5SlaveTransactor transactor("transactor", "transactor");
    transactor.socket.bind(dramSys.tSocket);
    transactor.sim_control.bind(sim_control);
#endif

#ifdef CHOICE2
    // If there are two ports
    Gem5SystemC::Gem5SlaveTransactor transactor1("transactor1", "transactor1");
    Gem5SystemC::Gem5SlaveTransactor transactor2("transactor2", "transactor2");
    transactor1.socket.bind(dramSys.tSocket);
    transactor2.socket.bind(dramSys.tSocket);
    transactor1.sim_control.bind(sim_control);
    transactor2.sim_control.bind(sim_control);
#endif

#ifdef CHOICE3
    // If for example two gem5 ports are used (NVM and DRAM) with
    // crazy address offsets:
    Gem5SystemC::Gem5SlaveTransactor dramInterface("transactor1", "transactor1");
    Gem5SystemC::Gem5SlaveTransactor nvmInterface("transactor2", "transactor2");

    AddressOffset nvmOffset("nvmOffset",0);
    AddressOffset dramOffset("dramOffset", (2147483648-67108863));//+67108863);

    dramInterface.socket.bind(dramOffset.t_socket);
    dramOffset.i_socket.bind(dramSys.tSocket); // ID0
    nvmInterface.socket.bind(nvmOffset.t_socket);
    nvmOffset.i_socket.bind(dramSys.tSocket);

    dramInterface.sim_control.bind(sim_control);
    nvmInterface.sim_control.bind(sim_control);
#endif

    SC_REPORT_INFO("sc_main", "Start of Simulation");

    sc_core::sc_set_stop_mode(SC_STOP_FINISH_DELTA);
    sc_core::sc_start();

    if (!sc_core::sc_end_of_simulation_invoked())
    {
        SC_REPORT_INFO("sc_main","Simulation stopped without explicit sc_stop()");
        sc_core::sc_stop();
    }

    SC_REPORT_INFO("sc_main", "End of Simulation");

    return EXIT_SUCCESS;
}