Derek Christ
1ef2b3bd9c
Update the DRAMUtils version and fix all configs that now require DBI parameters for the memimpedance spec.
150 lines
3.9 KiB
JSON
150 lines
3.9 KiB
JSON
{
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"memspec": {
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"memarchitecturespec": {
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"burstLength": 16,
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"dataRate": 2,
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"nbrOfBanks": 8,
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"nbrOfColumns": 1024,
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"nbrOfRanks": 1,
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"nbrOfRows": 49152,
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"width": 16,
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"nbrOfDevices": 1,
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"nbrOfChannels": 1,
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"nbrOfBankGroups": 1,
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"maxBurstLength": 16
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},
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"memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A",
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"memoryType": "LPDDR4",
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"mempowerspec": {
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"idd01": 3.5e-3,
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"idd02": 45.0e-3,
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"idd0ql": 0.75e-3,
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"idd2n1": 2.0e-3,
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"idd2n2": 27.0e-3,
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"idd2nQ": 0.75e-3,
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"idd2ns1": 2.0e-3,
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"idd2ns2": 23.0e-3,
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"idd2nsq": 0.75e-3,
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"idd2p1": 1.2e-3,
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"idd2p2": 3.0e-3,
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"idd2pQ": 0.75e-3,
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"idd2ps1": 1.2e-3,
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"idd2ps2": 3.0e-3,
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"idd2psq": 0.75e-3,
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"idd3n1": 2.25e-3,
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"idd3n2": 30.0e-3,
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"idd3nQ": 0.75e-3,
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"idd3ns1": 2.25e-3,
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"idd3ns2": 30.0e-3,
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"idd3nsq": 0.75e-3,
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"idd3p1": 1.2e-3,
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"idd3p2": 9.0e-3,
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"idd3pQ": 0.75e-3,
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"idd3ps1": 1.2e-3,
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"idd3ps2": 9.0e-3,
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"idd3psq": 0.75e-3,
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"idd4r1": 2.25e-3,
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"idd4r2": 275.0e-3,
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"idd4rq": 150.0e-3,
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"idd4w1": 2.25e-3,
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"idd4w2": 210.0e-3,
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"idd4wq": 55.0e-3,
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"idd51": 10.0e-3,
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"idd52": 90.0e-3,
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"idd5ab1": 2.5e-3,
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"idd5ab2": 30.0e-3,
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"idd5abq": 0.75e-3,
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"idd5pb1": 2.5e-3,
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"idd5pb2": 30.0e-3,
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"idd5pbq": 0.75e-3,
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"idd5q": 0.75e-3,
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"idd61": 0.3e-3,
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"idd62": 0.5e-3,
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"idd6q": 0.1e-3,
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"vdd1": 1.8,
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"vdd2": 1.1,
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"vddq": 1.1,
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"iBeta_vdd1": 3.5e-3,
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"iBeta_vdd2": 45.0e-3
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},
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"memtimingspec": {
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"AL": 0,
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"CCD": 8,
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"CCDMW": 32,
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"CKE": 12,
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"CKESR": 24,
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"CL": 12,
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"DQSCK": 3,
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"ESCKE": 24,
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"FAW": 64,
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"PPD": 4,
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"RAS": 68,
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"RC": 97,
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"RCD": 29,
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"REFI": 6246,
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"REFIpb": 780,
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"RFCab": 448,
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"RFCpb": 224,
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"RL": 28,
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"RPab": 34,
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"RPpb": 29,
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"RRD": 16,
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"RTP": 12,
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"WL": 14,
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"WR": 29,
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"WTR": 16,
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"XP": 12,
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"XS": 458,
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"tCK": 625,
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"RCpb": 0,
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"RCab": 0,
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"RPST": 0,
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"DQSS": 0,
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"DQS2DQ": 0,
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"WPRE": 0,
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"SR": 0,
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"XSR": 0,
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"RTRS": 0,
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"CMDCKE": 0
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},
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"memimpedancespec": {
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"ck_termination": true,
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"ck_R_eq": 1e6,
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"ck_dyn_E": 1e-12,
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"ca_termination": true,
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"ca_R_eq": 1e6,
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"ca_dyn_E": 1e-12,
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"rdq_termination": true,
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"rdq_R_eq": 1e6,
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"rdq_dyn_E": 1e-12,
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"wdq_termination": true,
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"wdq_R_eq": 1e6,
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"wdq_dyn_E": 1e-12,
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"wdqs_termination": true,
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"wdqs_R_eq": 1e6,
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"wdqs_dyn_E": 1e-12,
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"rdqs_termination": true,
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"rdqs_R_eq": 1e6,
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"rdqs_dyn_E": 1e-12,
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"rdbi_termination": true,
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"rdbi_R_eq": 1e6,
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"rdbi_dyn_E": 1e-12,
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"wdbi_termination": true,
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"wdbi_R_eq": 1e6,
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"wdbi_dyn_E": 1e-12
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},
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"bankwisespec": {
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"factRho": 1,
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"factSigma": 1,
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"pasrMode": 0,
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"hasPASR": false
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}
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}
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}
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