{
    "memspec": {
        "memarchitecturespec": {
            "burstLength": 16,
            "dataRate": 2,
            "nbrOfBanks": 8,
            "nbrOfColumns": 1024,
            "nbrOfRanks": 1,
            "nbrOfRows": 49152,
            "width": 16,
            "nbrOfDevices": 1,
            "nbrOfChannels": 1,
            "nbrOfBankGroups": 1,
            "maxBurstLength": 16
        },
        "memoryId": "MICRON_6Gb_LPDDR3-3200_16bit_A",
        "memoryType": "LPDDR4",
        "mempowerspec": {
            "idd01": 3.5e-3,
            "idd02": 45.0e-3,
            "idd0ql": 0.75e-3,
            "idd2n1": 2.0e-3,
            "idd2n2": 27.0e-3,
            "idd2nQ": 0.75e-3,
            "idd2ns1": 2.0e-3,
            "idd2ns2": 23.0e-3,
            "idd2nsq": 0.75e-3,
            "idd2p1": 1.2e-3,
            "idd2p2": 3.0e-3,
            "idd2pQ": 0.75e-3,
            "idd2ps1": 1.2e-3,
            "idd2ps2": 3.0e-3,
            "idd2psq": 0.75e-3,
            "idd3n1": 2.25e-3,
            "idd3n2": 30.0e-3,
            "idd3nQ": 0.75e-3,
            "idd3ns1": 2.25e-3,
            "idd3ns2": 30.0e-3,
            "idd3nsq": 0.75e-3,
            "idd3p1": 1.2e-3,
            "idd3p2": 9.0e-3,
            "idd3pQ": 0.75e-3,
            "idd3ps1": 1.2e-3,
            "idd3ps2": 9.0e-3,
            "idd3psq": 0.75e-3,
            "idd4r1": 2.25e-3,
            "idd4r2": 275.0e-3,
            "idd4rq": 150.0e-3,
            "idd4w1": 2.25e-3,
            "idd4w2": 210.0e-3,
            "idd4wq": 55.0e-3,
            "idd51": 10.0e-3,
            "idd52": 90.0e-3,
            "idd5ab1": 2.5e-3,
            "idd5ab2": 30.0e-3,
            "idd5abq": 0.75e-3,
            "idd5pb1": 2.5e-3,
            "idd5pb2": 30.0e-3,
            "idd5pbq": 0.75e-3,
            "idd5q": 0.75e-3,
            "idd61": 0.3e-3,
            "idd62": 0.5e-3,
            "idd6q": 0.1e-3,
            "vdd1": 1.8,
            "vdd2": 1.1,
            "vddq": 1.1,

            "iBeta_vdd1": 3.5e-3,
            "iBeta_vdd2": 45.0e-3
        },
        "memtimingspec": {
            "AL": 0,
            "CCD": 8,
            "CCDMW": 32,
            "CKE": 12,
            "CKESR": 24,
            "CL": 12,
            "DQSCK": 3,
            "ESCKE": 24,
            "FAW": 64,
            "PPD": 4,
            "RAS": 68,
            "RC": 97,
            "RCD": 29,
            "REFI": 6246,
            "REFIpb": 780,
            "RFCab": 448,
            "RFCpb": 224,
            "RL": 28,
            "RPab": 34,
            "RPpb": 29,
            "RRD": 16,
            "RTP": 12,
            "WL": 14,
            "WR": 29,
            "WTR": 16,
            "XP": 12,
            "XS": 458,
            "tCK": 625,

            "RCpb": 0,
            "RCab": 0,
            "RPST": 0,
            "DQSS": 0,
            "DQS2DQ": 0,
            "WPRE": 0,
            "SR": 0,
            "XSR": 0,
            "RTRS": 0,
            "CMDCKE": 0
        },
        "memimpedancespec": {
            "ck_termination": true,
            "ck_R_eq": 1e6,
            "ck_dyn_E": 1e-12,

            "ca_termination": true,
            "ca_R_eq": 1e6,
            "ca_dyn_E": 1e-12,

            "rdq_termination": true,
            "rdq_R_eq": 1e6,
            "rdq_dyn_E": 1e-12,
            "wdq_termination": true,
            "wdq_R_eq": 1e6,
            "wdq_dyn_E": 1e-12,

            "wdqs_termination": true,
            "wdqs_R_eq": 1e6,
            "wdqs_dyn_E": 1e-12,
            "rdqs_termination": true,
            "rdqs_R_eq": 1e6,
            "rdqs_dyn_E": 1e-12,

            "rdbi_termination": true,
            "rdbi_R_eq": 1e6,
            "rdbi_dyn_E": 1e-12,
            "wdbi_termination": true,
            "wdbi_R_eq": 1e6,
            "wdbi_dyn_E": 1e-12
        },
        "bankwisespec": {
            "factRho": 1,
            "factSigma": 1,
            "pasrMode": 0,
            "hasPASR": false
        }
    }
}