Files
DRAMSys/configs/memspec/JEDEC_256Mb_WIDEIO-266_128bit.json
2025-05-09 16:45:54 +02:00

69 lines
1.7 KiB
JSON

{
"memspec": {
"memarchitecturespec": {
"burstLength": 4,
"dataRate": 1,
"nbrOfBanks": 4,
"nbrOfColumns": 128,
"nbrOfRanks": 1,
"nbrOfRows": 4096,
"width": 128,
"nbrOfDevices": 1,
"nbrOfChannels": 4,
"maxBurstLength": 4
},
"memoryId": "JEDEC_256Mb_WIDEIO_SDR-266_128bit",
"memoryType": "WIDEIO_SDR",
"mempowerspec": {
"idd0": 6.06e-3,
"idd02": 21.82e-3,
"idd2n": 0.16e-3,
"idd2n2": 4.76e-3,
"idd2p0": 0.05e-3,
"idd2p02": 0.17e-3,
"idd2p1": 0.05e-3,
"idd2p12": 0.17e-3,
"idd3n": 0.58e-3,
"idd3n2": 7.24e-3,
"idd3p0": 0.25e-3,
"idd3p02": 1.49e-3,
"idd3p1": 0.25e-3,
"idd3p12": 1.49e-3,
"idd4r": 1.82e-3,
"idd4r2": 111.22e-3,
"idd4w": 1.82e-3,
"idd4w2": 78.0e-3,
"idd5": 14.48e-3,
"idd52": 48.34e-3,
"idd6": 0.07e-3,
"idd62": 0.27e-3,
"vdd": 1.8,
"vdd2": 1.2
},
"memtimingspec": {
"AC": 1,
"CCD_R": 2,
"CCD_W": 1,
"CKE": 3,
"CKESR": 4,
"DQSCK": 1,
"RAS": 12,
"RC": 16,
"RCD": 5,
"REFI": 4160,
"RFC": 24,
"RL": 3,
"RP": 5,
"RRD": 3,
"TAW": 14,
"WL": 1,
"WR": 4,
"WTR": 4,
"XP": 3,
"XSR": 27,
"RTRS": 1,
"tCK": 3759e-12
}
}
}