Commit Graph

2648 Commits

Author SHA1 Message Date
ecf9127faa Fix some tests and refactor simulation script 2024-12-11 12:56:56 +01:00
Lukas Steiner
be1807e9b0 Merge branch 'fix/buffer_entries' into 'develop'
Fix/buffer entries

Closes #64

See merge request ems/astdm/modeling.dram/dram.sys.5!86
2024-11-29 10:34:09 +00:00
Lukas Steiner
01caf7875e Merge branch 'fix/bandwidth' into 'develop'
Fix for bandwidth calculations with pseudo-channels

See merge request ems/astdm/modeling.dram/dram.sys.5!87
2024-11-29 08:48:37 +00:00
e777b7e196 Merge branch 'fix/ta_performance' into 'develop'
Improve TA performance by increasing window of loaded transactions

See merge request ems/astdm/modeling.dram/dram.sys.5!88
2024-11-18 13:17:16 +00:00
8953d1054d Merge branch '38-bespiel-fur-alle-config-jsons-in-einem-file' into 'develop'
Resolve "Bespiel für alle Config JSONs in einem File"

Closes #38

See merge request ems/astdm/modeling.dram/dram.sys.5!89
2024-11-18 13:10:16 +00:00
007b273760 Add a DDR4 json example that defines everything in one single JSON 2024-11-18 14:05:52 +01:00
f960f499c6 Improve TA performance by increasing window of loaded transactions 2024-11-18 13:48:06 +01:00
e409bab47a Implement pseudo-channel and rank specific BW information 2024-11-18 13:18:33 +01:00
e74a617273 Crude fix for bandwidth calculations with pseudo-channels 2024-11-15 15:57:37 +01:00
18c00fc363 Pass a number of required buffer entries to hasBufferSpace() 2024-11-15 14:17:03 +01:00
ba0d0165e8 Merge branch 'think_delay' into 'develop'
Fix the data burst location when a think delay is set

See merge request ems/astdm/modeling.dram/dram.sys.5!84
2024-11-05 10:07:51 +00:00
ad1ea86d2e Fix the data burst location when a think delay is set 2024-11-05 11:04:24 +01:00
108aa7d68b Merge branch 'fix_gem5_build' into 'develop'
Don't set SYSTEM property for external SystemC

See merge request ems/astdm/modeling.dram/dram.sys.5!82
2024-10-28 08:04:12 +00:00
67d95edb25 Don't set SYSTEM property for external SystemC 2024-10-28 08:59:41 +01:00
484a3ccc58 Merge branch 'bmbf_logo' into 'develop'
Add BMBF Logo

See merge request ems/astdm/modeling.dram/dram.sys.5!77
2024-10-25 13:59:00 +00:00
d380d6039d Merge branch 'windows_fix' into 'develop'
Switch to <filesystem> remove operation

See merge request ems/astdm/modeling.dram/dram.sys.5!79
2024-10-25 13:58:21 +00:00
bca614f236 Merge branch 'fix/dead_link' into 'develop'
Fix broken DRAMSys link

See merge request ems/astdm/modeling.dram/dram.sys.5!80
2024-10-25 13:57:43 +00:00
88d58d997e Merge branch 'notice_versions' into 'develop'
Update NOTICE file with versions

See merge request ems/astdm/modeling.dram/dram.sys.5!81
2024-10-25 13:57:29 +00:00
978286edae Update NOTICE file with versions 2024-10-22 16:09:05 +02:00
f4341b160a Fix broken DRAMSys link 2024-10-07 12:50:38 +02:00
7a32613cb3 Switch to <filesystem> remove operation 2024-09-25 11:00:09 +02:00
a261506e95 Add BMBF Logo 2024-09-09 18:33:30 +02:00
0ebc83fc32 Merge branch 'fix_build_issue' into 'develop'
Fix compilation errors on some systems

See merge request ems/astdm/modeling.dram/dram.sys.5!76
2024-09-09 09:33:07 +00:00
e21b051fb5 Fix compilation errors on some systems 2024-09-09 11:29:39 +02:00
Lukas Steiner
f54fe362e4 Merge branch 'opensource-traceanalyzer' into 'develop'
Move Trace Analyzer to open source tree

See merge request ems/astdm/modeling.dram/dram.sys.5!73
2024-07-18 09:36:34 +00:00
0fdb846f3d Fix external SystemC and update Readme 2024-07-18 11:17:49 +02:00
Lukas Steiner
4d034300a5 Merge branch 'develop' into opensource-traceanalyzer
# Conflicts:
#	README.md
2024-07-18 10:30:40 +02:00
Lukas Steiner
94a05c636e Merge branch 'contact_info' into 'develop'
Update contact info

See merge request ems/astdm/modeling.dram/dram.sys.5!70
2024-07-18 08:22:33 +00:00
2465f06d14 Minor fixes in the Trace Analyzer 2024-07-18 10:16:36 +02:00
c893fe1663 Update README to feature the full version of Trace Analyzer 2024-07-18 10:16:35 +02:00
Lukas Steiner
52ebd1dfb8 Merge branch 'develop' into contact_info
# Conflicts:
#	README.md
2024-07-18 10:13:46 +02:00
82027bfa83 Move Trace Analyzer to open source tree
Move the code for the Trace Analyzer to the open source tree and only
keep the extensions behind a compiler flag.
2024-07-18 10:13:25 +02:00
Lukas Steiner
cfd980373b Merge branch 'third-party' into 'develop'
Add notice file for all used third party work

See merge request ems/astdm/modeling.dram/dram.sys.5!69
2024-07-18 07:52:26 +00:00
Lukas Steiner
317158b57a Merge branch 'update_readme' into 'develop'
Update the Readme in regards to CMake configuration

See merge request ems/astdm/modeling.dram/dram.sys.5!68
2024-07-18 07:50:47 +00:00
Lukas Steiner
3d9d12ea65 Merge branch 'buffer_warning' into 'develop'
Add a warning when RequestBufferSize is configured together with ReadWrite SchedulerBuffer

See merge request ems/astdm/modeling.dram/dram.sys.5!67
2024-07-18 07:49:40 +00:00
Lukas Steiner
9d2be300f6 Merge branch 'cmake_refactor' into 'develop'
Refactor CMakeLists and GitLab CI/CD pipeline

See merge request ems/astdm/modeling.dram/dram.sys.5!71
2024-07-11 12:32:00 +00:00
Lukas Steiner
24f8023d39 Merge branch 'bug/lp5_checker' into 'develop'
Fix wrong command dependency.

See merge request ems/astdm/modeling.dram/dram.sys.5!72
2024-07-05 11:04:09 +00:00
Lukas Steiner
5a90c017d9 Fix wrong command dependency. 2024-07-05 08:11:39 +00:00
f6ebf440fc Update the Readme in regards to CMake configuration 2024-06-28 11:20:40 +02:00
5dd7c22a74 Refactor CMakeLists and GitLab CI/CD pipeline
- Remove nested minimum required to supress warnings.
- Declare SystemC as system library to supress warnings in headers.
- Add a BUILD_SHARED_LIBS option
- Remove hardcoded STATIC in various add_library calls to honor the
  BUILD_SHARED_LIBS option
- Remove _deps/ directory from the build directory in GitLab pipeline
- Remove *.tdb files after test stage in pipeline
- Set Ninja as the default generator for the dev preset and re-enable
  colored diagnostics
2024-06-28 11:07:56 +02:00
Lukas Steiner
3159cf038b Merge branch 'fix/bugs' into 'develop'
Fix various bugs

See merge request ems/astdm/modeling.dram/dram.sys.5!66
2024-06-28 07:46:03 +00:00
96c0fde78f Update contact info 2024-06-21 13:56:12 +02:00
f70c813140 Add notice file for all used third party work 2024-06-20 11:48:54 +02:00
7274770a0f Add a warning when RequestBufferSize is configured together with ReadWrite SchedulerBuffer 2024-05-08 10:09:20 +02:00
12bfba1fb3 Fix various bugs
- Fix data race for some tests by disabling database recording
- Fix undefined behaviour in configuration test
- Port clkMhz to tCK for simulation script
- Port memUtil Python script to tCK with backwards compatibility
2024-02-26 09:58:19 +01:00
Lukas Steiner
41f683619d Merge branch 'simulationscript' into 'develop'
Introduce powerful simulation script and provide an example

See merge request ems/astdm/modeling.dram/dram.sys.5!65
2024-02-23 14:29:43 +00:00
Lukas Steiner
5b4ed9559d Merge branch 'config_refactor' into 'develop'
Configuration Refactoring

See merge request ems/astdm/modeling.dram/dram.sys.5!63
2024-02-23 14:29:06 +00:00
Lukas Steiner
d0c3c04098 Merge branch 'clock_period' into 'develop'
Migrate from clkMhz to tCK (in ps) in memspecs

Closes #28

See merge request ems/astdm/modeling.dram/dram.sys.5!62
2024-02-23 14:25:16 +00:00
539a525f3d Fix DDR3 regression
Using the new tCK entry in the memspecs, there was a small power deviation in the database
2024-02-23 12:04:29 +01:00
0ec6ea79ad Migrate from clkMhz to tCK entry in memspecs 2024-02-23 12:04:22 +01:00