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ba94d9fd84
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Have a one cycle END_RESP delay in the standard initiator
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2025-01-24 14:43:06 +01:00 |
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1225f6b044
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Fix tests after ThinkDelayFw
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2025-01-24 14:19:53 +01:00 |
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539a525f3d
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Fix DDR3 regression
Using the new tCK entry in the memspecs, there was a small power deviation in the database
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2024-02-23 12:04:29 +01:00 |
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0ec6ea79ad
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Migrate from clkMhz to tCK entry in memspecs
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2024-02-23 12:04:22 +01:00 |
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1ba63bd1f7
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Add support for more than two XOR bits
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2023-12-13 10:32:03 +01:00 |
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bd899a2104
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Integrate regression tests with CTest
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2023-03-10 13:32:55 +01:00 |
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Lukas Steiner
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823d473d97
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Fix path in CI script.
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2023-02-23 17:09:33 +01:00 |
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Lukas Steiner
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c4ca3d71d7
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Reorganize config files, remove unused config.
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2023-02-23 17:02:21 +01:00 |
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Lukas Steiner
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39b456d837
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Use one stage for all tests.
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2023-02-23 14:09:16 +01:00 |
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Lukas Steiner
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ac04ae66ce
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Retry CI needs with coverage.
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2023-02-23 13:56:15 +01:00 |
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Lukas Steiner
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661819f381
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Path fix for DDR3 test.
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2023-02-23 11:36:17 +01:00 |
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Lukas Steiner
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d736a2d25e
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Fix regression tests, add DRAMPower.
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2023-02-23 10:38:59 +01:00 |
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Lukas Steiner
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9760ffe5cc
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Add regression test files.
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2023-01-30 15:45:10 +01:00 |
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