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Author SHA1 Message Date
Lukas Steiner
9949c36f83 Use separate thread for database creation. 2021-06-01 11:11:40 +02:00
Lukas Steiner
d6b8e73827 Change type of command from enum to class. 2021-05-31 15:19:48 +02:00
Lukas Steiner
57c62ccc87 Terminate and record last transaction of simulation. 2021-05-31 14:15:07 +02:00
Lukas Steiner
834e10efde Code refactoring. 2021-05-28 16:01:22 +02:00
Lukas Steiner
d023ebf128 Merge branch 'DDR5_PD_prep' into 'develop' 
Prepare for DDR5 power down (2).

See merge request ems/astdm/dram.sys!287
 2021-05-27 12:10:50 +00:00
Lukas Steiner
3617c66ad1 Merge branch 'work/tracegenerator' into 'develop' 
Implement a more advanced TraceGenerator (2).

See merge request ems/astdm/dram.sys!284
 2021-05-27 08:28:07 +00:00
Lukas Steiner
dd5707ec3e Small bugfix in TrafficInitiator, code refactoring. 2021-05-27 10:20:37 +02:00
Lukas Steiner
38fbf9f63a Let power down manager check state of bank machines. 2021-05-20 18:24:04 +02:00
Lukas Steiner
c015a73e91 Code refactoring. 2021-05-20 17:42:12 +02:00
Lukas Steiner
2256d03c58 Code refactoring. 2021-05-20 16:19:31 +02:00
Lukas Steiner
1b58c916b0 Code refactoring. 2021-05-20 15:56:41 +02:00
Lukas Steiner
dda39ac4ef Revert changes from previous commit. 2021-05-19 15:34:14 +02:00
Derek Christ
73d767c6f0 Set dataLength in TrafficGenerator to bytesPerBurst MemSpec 2021-05-19 15:23:55 +02:00
Lukas Steiner
ff265a8a95 Trigger power down interruption outside of refresh manager. 2021-05-19 14:03:13 +02:00
Derek Christ
6d6c1f7699 Merge remote-tracking branch 'origin/develop' into work/tracegenerator 2021-05-19 11:53:11 +02:00
Derek Christ
1d5bd72c60 Apply minor changes to TrafficInitiator and TrafficGenerator 2021-05-19 11:37:05 +02:00
Lukas Steiner
49838ea7d8 Merge branch 'STT-MRAM' into 'develop' 
Add STT-MRAM standard.

See merge request ems/astdm/dram.sys!283
 2021-05-19 08:44:46 +00:00
Lukas Steiner
dbe76bd906 Remove comments from memspec file. 2021-05-19 09:41:45 +02:00
Lukas Steiner
d4609ff669 Rename copyright notice. 2021-05-19 09:34:30 +02:00
Lukas Steiner
4d8d5caf72 Add STT-MRAM copyright notice. 2021-05-19 09:32:32 +02:00
Lukas Steiner
cb4455710d Add config files for STT-MRAM. 2021-05-17 15:51:55 +02:00
Lukas Steiner
77b79aac13 Initial version of STT-MRAM. 2021-05-17 14:03:34 +02:00
Lukas Steiner
08f0331a06 Merge branch 'develop' into 'STT-MRAM' 
Merge latest updates.

See merge request ems/astdm/dram.sys!282
 2021-05-17 11:48:00 +00:00
Lukas Steiner
99694d37cd Merge branch 'BL32_OTF' into 'develop' 
Add OTF burst length selection for DDR5.

See merge request ems/astdm/dram.sys!281
 2021-05-17 11:45:02 +00:00
Derek Christ
fdacb97c9b Update authors in TrafficInitiator sources 2021-05-17 10:42:03 +02:00
Derek Christ
119c4b8929 Restructure class hierarchy for TrafficInitiators 
The hierarchy for all TrafficInitiators was reorganized into a
more general structure. All TracePlayers and TrafficGenerators
inherit from the TrafficInitiator class.
The classes TrafficGeneratorSequential and TrafficGeneratorRandom
both inherit from the TrafficGenerator class and the StlPlayer
inherits from the TracePlayer class.
 2021-05-17 10:41:56 +02:00
Derek Christ
1a7450386d Remove redundant TracePlayer member variables 2021-05-17 10:24:31 +02:00
Derek Christ
71551db4e3 Implement a more advanced TraceGenerator 
Implementation of a more advanced TraceGenerator that can be
configured using the Json config file.
The new TraceGenerator is capable of specifing the number of
requests to make, the ratio of read and write accesses, the
distribution of the addresses, the address increment value in
case of a sequential address distribution, a seed in case of
a random address distribution and the maximum number of
pending read or write requests.
The maximum number of pending requests was also implemented
for the StlPlayer.
 2021-05-17 10:21:19 +02:00
Lukas Steiner
d84a065087 Small improvements in DDR5 checker. 2021-05-12 16:10:04 +02:00
Lukas Steiner
7e05226f8c Add blocked interval for dummy CAS commands to DDR5 checker. 2021-05-11 17:33:46 +02:00
Lukas Steiner
ad6eb6c7a2 Adapt bandwidth calculation to OTF burst length selection. 2021-05-10 15:53:56 +02:00
Lukas Steiner
fabc686e8c Initial version of BL32 OTF. 2021-05-10 14:32:05 +02:00
Lukas Steiner
e38d0aae1f Introduce burst length parameter. 2021-05-05 17:10:08 +02:00
Lukas Steiner
add4cf1a66 Merge branch 'clock_sync' into 'develop' 
Fix clock sync in STL player.

See merge request ems/astdm/dram.sys!278
 2021-05-05 14:04:26 +00:00
Lukas Steiner
9b7e2611ef Fix clock sync in STL player. 2021-05-05 15:55:06 +02:00
Lukas Steiner
3c476f4925 Simpler clock sync calculation in arbiter. 2021-05-05 15:43:52 +02:00
Lukas Steiner
24ef997180 Link thread library in simulator. 2021-05-04 10:56:45 +02:00
Lukas Steiner
1b0e6b1d33 Bugfix: Earliest time for ready command has to be sc_time_stamp(). 2021-04-29 10:58:24 +02:00
Lukas Steiner
b82a446c60 Ignore vscode config folder. 2021-04-28 14:20:46 +02:00
Lukas Steiner
4f7ab8db09 Merge branch 'cmdmux_rascas' into 'develop' 
Add special command muxes for standards with separate RAS and CAS command buses (HBM).

See merge request ems/astdm/dram.sys!275
 2021-04-23 08:56:11 +00:00
Lukas Steiner
399a073912 Code formatting. 2021-04-23 10:51:35 +02:00
Lukas Steiner
fc44d319bb New strict cmd mux working. 2021-04-22 11:27:22 +02:00
Lukas Steiner
ae85f6cd83 New oldest cmd mux working. 2021-04-21 09:38:22 +02:00
Lukas Steiner
f4bf06219b Do not use scientific notation for metric results. 2021-04-20 15:27:31 +02:00
Lukas Steiner
0c51a4e1f8 First version of RasCas command mux, not working. 2021-03-24 09:10:12 +01:00
Lukas Steiner
81bbe066c8 Markdown formatting. 2021-03-23 09:34:49 +01:00
Lukas Steiner
ba3c09b2ad Updated readme, code formatting. 2021-03-23 09:31:06 +01:00
Lukas Steiner
4650951026 Update gem5 readme. 2021-02-09 15:27:25 +01:00
Lukas Steiner
28b2fee54c Fix wrong standard display. 2021-02-09 15:08:27 +01:00
Lukas Steiner
2143f7cbff Set payload extensions in arbiter at END_REQ. 2021-02-02 16:40:44 +01:00