derek/DRAMSys
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Code refactoring.

Browse Source
This commit is contained in:
Lukas Steiner
2021-05-20 16:19:31 +02:00
parent 1b58c916b0
commit 2256d03c58
33 changed files with 101 additions and 101 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
DRAMSys/library/src/controller/checker/CheckerDDR3.h
View File

@@ -45,8 +45,8 @@ class CheckerDDR3 final : public CheckerIF
{
public:
CheckerDDR3();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecDDR3 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerDDR4.h
View File

@@ -45,8 +45,8 @@ class CheckerDDR4 final : public CheckerIF
{
public:
CheckerDDR4();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecDDR4 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerDDR5.h
View File

@@ -46,8 +46,8 @@ class CheckerDDR5 final : public CheckerIF
{
public:
CheckerDDR5();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecDDR5 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerGDDR5.h
View File

@@ -45,8 +45,8 @@ class CheckerGDDR5 final : public CheckerIF
{
public:
CheckerGDDR5();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecGDDR5 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerGDDR5X.h
View File

@@ -45,8 +45,8 @@ class CheckerGDDR5X final : public CheckerIF
{
public:
CheckerGDDR5X();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecGDDR5X *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerGDDR6.h
View File

@@ -45,8 +45,8 @@ class CheckerGDDR6 final : public CheckerIF
{
public:
CheckerGDDR6();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecGDDR6 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerHBM2.h
View File

@@ -45,8 +45,8 @@ class CheckerHBM2 final : public CheckerIF
{
public:
CheckerHBM2();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecHBM2 *memSpec;

2
DRAMSys/library/src/controller/checker/CheckerIF.h
View File

@@ -44,7 +44,7 @@
class CheckerIF
{
public:
virtual ~CheckerIF() {}
virtual ~CheckerIF() = default;
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const = 0;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) = 0;

4
DRAMSys/library/src/controller/checker/CheckerLPDDR4.h
View File

@@ -45,8 +45,8 @@ class CheckerLPDDR4 final : public CheckerIF
{
public:
CheckerLPDDR4();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecLPDDR4 *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerSTTMRAM.h
View File

@@ -45,8 +45,8 @@ class CheckerSTTMRAM final : public CheckerIF
{
public:
CheckerSTTMRAM();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecSTTMRAM *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerWideIO.h
View File

@@ -45,8 +45,8 @@ class CheckerWideIO final : public CheckerIF
{
public:
CheckerWideIO();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecWideIO *memSpec;

4
DRAMSys/library/src/controller/checker/CheckerWideIO2.h
View File

@@ -45,8 +45,8 @@ class CheckerWideIO2 final : public CheckerIF
{
public:
CheckerWideIO2();
virtual sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
virtual void insert(Command command, tlm::tlm_generic_payload *payload) override;
sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecWideIO2 *memSpec;

2
DRAMSys/library/src/controller/cmdmux/CmdMuxIF.h
View File

@@ -44,7 +44,7 @@
class CmdMuxIF
{
public:
virtual ~CmdMuxIF() {}
virtual ~CmdMuxIF() = default;
virtual CommandTuple::Type selectCommand(const ReadyCommands &) = 0;
};

4
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.cpp
View File

@@ -71,7 +71,7 @@ CommandTuple::Type CmdMuxOldest::selectCommand(const ReadyCommands &readyCommand
std::get<CommandTuple::Timestamp>(*result) == sc_time_stamp())
return *result;
else
return CommandTuple::Type(Command::NOP, nullptr, sc_max_time());
return {Command::NOP, nullptr, sc_max_time()};
}
@@ -177,5 +177,5 @@ CommandTuple::Type CmdMuxOldestRasCas::selectCommand(const ReadyCommands &readyC
std::get<CommandTuple::Timestamp>(*result) == sc_time_stamp())
return *result;
else
return CommandTuple::Type(Command::NOP, nullptr, sc_max_time());
return {Command::NOP, nullptr, sc_max_time()};
}

4
DRAMSys/library/src/controller/cmdmux/CmdMuxOldest.h
View File

@@ -42,7 +42,7 @@ class CmdMuxOldest : public CmdMuxIF
{
public:
CmdMuxOldest();
virtual CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands &) override;
private:
const MemSpec *memSpec;
@@ -53,7 +53,7 @@ class CmdMuxOldestRasCas : public CmdMuxIF
{
public:
CmdMuxOldestRasCas();
virtual CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands &) override;
private:
const MemSpec *memSpec;

4
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.cpp
View File

@@ -81,7 +81,7 @@ CommandTuple::Type CmdMuxStrict::selectCommand(const ReadyCommands &readyCommand
return *result;
}
else
return CommandTuple::Type(Command::NOP, nullptr, sc_max_time());
return {Command::NOP, nullptr, sc_max_time()};
}
@@ -180,5 +180,5 @@ CommandTuple::Type CmdMuxStrictRasCas::selectCommand(const ReadyCommands &readyC
return *result;
}
else
return CommandTuple::Type(Command::NOP, nullptr, sc_max_time());
return {Command::NOP, nullptr, sc_max_time()};
}

4
DRAMSys/library/src/controller/cmdmux/CmdMuxStrict.h
View File

@@ -42,7 +42,7 @@ class CmdMuxStrict : public CmdMuxIF
{
public:
CmdMuxStrict();
virtual CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands &) override;
private:
uint64_t nextPayloadID = 1;
@@ -53,7 +53,7 @@ class CmdMuxStrictRasCas : public CmdMuxIF
{
public:
CmdMuxStrictRasCas();
virtual CommandTuple::Type selectCommand(const ReadyCommands &) override;
CommandTuple::Type selectCommand(const ReadyCommands &) override;
private:
uint64_t nextPayloadID = 1;

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.cpp
View File

@@ -38,7 +38,7 @@ using namespace tlm;
CommandTuple::Type PowerDownManagerDummy::getNextCommand()
{
return CommandTuple::Type(Command::NOP, nullptr, sc_max_time());
return {Command::NOP, nullptr, sc_max_time()};
}
sc_time PowerDownManagerDummy::start()

14
DRAMSys/library/src/controller/powerdown/PowerDownManagerDummy.h
View File

@@ -40,15 +40,15 @@
class PowerDownManagerDummy final : public PowerDownManagerIF
{
public:
PowerDownManagerDummy() {}
PowerDownManagerDummy() = default;
virtual void triggerEntry() override {}
virtual void triggerExit() override {}
virtual void triggerInterruption() override {}
void triggerEntry() override {}
void triggerExit() override {}
void triggerInterruption() override {}
virtual CommandTuple::Type getNextCommand() override;
virtual void updateState(Command) override {}
virtual sc_time start() override;
CommandTuple::Type getNextCommand() override;
void updateState(Command) override {}
sc_time start() override;
};
#endif // POWERDOWNMANAGERDUMMY_H

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerIF.h
View File

@@ -43,7 +43,7 @@
class PowerDownManagerIF
{
public:
virtual ~PowerDownManagerIF() {}
virtual ~PowerDownManagerIF() = default;
virtual void triggerEntry() = 0;
virtual void triggerExit() = 0;

2
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.cpp
View File

@@ -71,7 +71,7 @@ void PowerDownManagerStaggered::triggerInterruption()
CommandTuple::Type PowerDownManagerStaggered::getNextCommand()
{
return CommandTuple::Type(nextCommand, &powerDownPayload, std::max(timeToSchedule, sc_time_stamp()));
return {nextCommand, &powerDownPayload, std::max(timeToSchedule, sc_time_stamp())};
}
sc_time PowerDownManagerStaggered::start()

12
DRAMSys/library/src/controller/powerdown/PowerDownManagerStaggered.h
View File

@@ -44,13 +44,13 @@ class PowerDownManagerStaggered final : public PowerDownManagerIF
public:
PowerDownManagerStaggered(Rank, CheckerIF *);
virtual void triggerEntry() override;
virtual void triggerExit() override;
virtual void triggerInterruption() override;
void triggerEntry() override;
void triggerExit() override;
void triggerInterruption() override;
virtual CommandTuple::Type getNextCommand() override;
virtual void updateState(Command) override;
virtual sc_time start() override;
CommandTuple::Type getNextCommand() override;
void updateState(Command) override;
sc_time start() override;
private:
enum class State {Idle, ActivePdn, PrechargePdn, SelfRefresh, ExtraRefresh} state = State::Idle;

6
DRAMSys/library/src/controller/respqueue/RespQueueFifo.h
View File

@@ -44,9 +44,9 @@
class RespQueueFifo final : public RespQueueIF
{
public:
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
virtual tlm::tlm_generic_payload *nextPayload() override;
virtual sc_time getTriggerTime() const override;
void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
tlm::tlm_generic_payload *nextPayload() override;
sc_time getTriggerTime() const override;
private:
std::queue<std::pair<tlm::tlm_generic_payload *, sc_time>> buffer;

2
DRAMSys/library/src/controller/respqueue/RespQueueIF.h
View File

@@ -44,7 +44,7 @@ public:
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) = 0;
virtual tlm::tlm_generic_payload *nextPayload() = 0;
virtual sc_time getTriggerTime() const = 0;
virtual ~RespQueueIF() {}
virtual ~RespQueueIF() = default;
};
#endif // RESPQUEUEIF_H

6
DRAMSys/library/src/controller/respqueue/RespQueueReorder.h
View File

@@ -43,9 +43,9 @@
class RespQueueReorder final : public RespQueueIF
{
public:
virtual void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
virtual tlm::tlm_generic_payload *nextPayload() override;
virtual sc_time getTriggerTime() const override;
void insertPayload(tlm::tlm_generic_payload *, sc_time) override;
tlm::tlm_generic_payload *nextPayload() override;
sc_time getTriggerTime() const override;
private:
uint64_t nextPayloadID = 1;

8
DRAMSys/library/src/controller/scheduler/BufferCounterBankwise.h
View File

@@ -43,10 +43,10 @@ class BufferCounterBankwise final : public BufferCounterIF
{
public:
BufferCounterBankwise(unsigned requestBufferSize, unsigned numberOfBanks);
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *payload) override;
virtual void removeRequest(tlm::tlm_generic_payload *payload) override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload *payload) override;
void removeRequest(tlm::tlm_generic_payload *payload) override;
const std::vector<unsigned> &getBufferDepth() const override;
private:
const unsigned requestBufferSize;

10
DRAMSys/library/src/controller/scheduler/BufferCounterReadWrite.h
View File

@@ -40,11 +40,11 @@
class BufferCounterReadWrite final : public BufferCounterIF
{
public:
BufferCounterReadWrite(unsigned requestBufferSize);
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *payload) override;
virtual void removeRequest(tlm::tlm_generic_payload *payload) override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
explicit BufferCounterReadWrite(unsigned requestBufferSize);
bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload *payload) override;
void removeRequest(tlm::tlm_generic_payload *payload) override;
const std::vector<unsigned> &getBufferDepth() const override;
private:
const unsigned requestBufferSize;

10
DRAMSys/library/src/controller/scheduler/BufferCounterShared.h
View File

@@ -40,11 +40,11 @@
class BufferCounterShared final : public BufferCounterIF
{
public:
BufferCounterShared(unsigned requestBufferSize);
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *payload) override;
virtual void removeRequest(tlm::tlm_generic_payload *payload) override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
explicit BufferCounterShared(unsigned requestBufferSize);
bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload *payload) override;
void removeRequest(tlm::tlm_generic_payload *payload) override;
const std::vector<unsigned> &getBufferDepth() const override;
private:
const unsigned requestBufferSize;

16
DRAMSys/library/src/controller/scheduler/SchedulerFifo.h
View File

@@ -48,14 +48,14 @@ class SchedulerFifo final : public SchedulerIF
{
public:
SchedulerFifo();
virtual ~SchedulerFifo() override;
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *) override;
virtual void removeRequest(tlm::tlm_generic_payload *) override;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
virtual bool hasFurtherRowHit(Bank, Row) const override;
virtual bool hasFurtherRequest(Bank) const override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
~SchedulerFifo() override;
bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload *) override;
void removeRequest(tlm::tlm_generic_payload *) override;
tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
bool hasFurtherRowHit(Bank, Row) const override;
bool hasFurtherRequest(Bank) const override;
const std::vector<unsigned> &getBufferDepth() const override;
private:
std::vector<std::deque<tlm::tlm_generic_payload *>> buffer;

10
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.cpp
View File

@@ -92,10 +92,10 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) c
{
// Search for row hit
Row openRow = bankMachine->getOpenRow();
for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++)
for (auto it : buffer[bankID])
{
if (DramExtension::getRow(*it) == openRow)
return *it;
if (DramExtension::getRow(it) == openRow)
return it;
}
}
// No row hit found or bank precharged
@@ -107,9 +107,9 @@ tlm_generic_payload *SchedulerFrFcfs::getNextRequest(BankMachine *bankMachine) c
bool SchedulerFrFcfs::hasFurtherRowHit(Bank bank, Row row) const
{
unsigned rowHitCounter = 0;
for (auto it = buffer[bank.ID()].begin(); it != buffer[bank.ID()].end(); it++)
for (auto it : buffer[bank.ID()])
{
if (DramExtension::getRow(*it) == row)
if (DramExtension::getRow(it) == row)
{
rowHitCounter++;
if (rowHitCounter == 2)

16
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfs.h
View File

@@ -48,14 +48,14 @@ class SchedulerFrFcfs final : public SchedulerIF
{
public:
SchedulerFrFcfs();
virtual ~SchedulerFrFcfs() override;
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *) override;
virtual void removeRequest(tlm::tlm_generic_payload *) override;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
virtual bool hasFurtherRowHit(Bank, Row) const override;
virtual bool hasFurtherRequest(Bank) const override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
~SchedulerFrFcfs() override;
bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload *) override;
void removeRequest(tlm::tlm_generic_payload *) override;
tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
bool hasFurtherRowHit(Bank, Row) const override;
bool hasFurtherRequest(Bank) const override;
const std::vector<unsigned> &getBufferDepth() const override;
private:
std::vector<std::list<tlm::tlm_generic_payload *>> buffer;

6
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.cpp
View File

@@ -94,10 +94,10 @@ tlm_generic_payload *SchedulerFrFcfsGrp::getNextRequest(BankMachine *bankMachine
// Filter all row hits
Row openRow = bankMachine->getOpenRow();
std::list<tlm_generic_payload *> rowHits;
for (auto it = buffer[bankID].begin(); it != buffer[bankID].end(); it++)
for (auto it : buffer[bankID])
{
if (DramExtension::getRow(*it) == openRow)
rowHits.push_back(*it);
if (DramExtension::getRow(it) == openRow)
rowHits.push_back(it);
}
if (!rowHits.empty())

16
DRAMSys/library/src/controller/scheduler/SchedulerFrFcfsGrp.h
View File

@@ -48,14 +48,14 @@ class SchedulerFrFcfsGrp final : public SchedulerIF
{
public:
SchedulerFrFcfsGrp();
virtual ~SchedulerFrFcfsGrp() override;
virtual bool hasBufferSpace() const override;
virtual void storeRequest(tlm::tlm_generic_payload *) override;
virtual void removeRequest(tlm::tlm_generic_payload *) override;
virtual tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
virtual bool hasFurtherRowHit(Bank, Row) const override;
virtual bool hasFurtherRequest(Bank) const override;
virtual const std::vector<unsigned> &getBufferDepth() const override;
~SchedulerFrFcfsGrp() override;
bool hasBufferSpace() const override;
void storeRequest(tlm::tlm_generic_payload *) override;
void removeRequest(tlm::tlm_generic_payload *) override;
tlm::tlm_generic_payload *getNextRequest(BankMachine *) const override;
bool hasFurtherRowHit(Bank, Row) const override;
bool hasFurtherRequest(Bank) const override;
const std::vector<unsigned> &getBufferDepth() const override;
private:
std::vector<std::list<tlm::tlm_generic_payload *>> buffer;