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581794b970
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Allow responses to be sent back-to-back
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2025-01-24 14:58:06 +01:00 |
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ba94d9fd84
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Have a one cycle END_RESP delay in the standard initiator
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2025-01-24 14:43:06 +01:00 |
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1225f6b044
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Fix tests after ThinkDelayFw
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2025-01-24 14:19:53 +01:00 |
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a82efdbb3a
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Fix HBM3 regression test
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2025-01-13 10:24:09 +01:00 |
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aba5ba6e2e
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Switch to Open page policy for HBM3 regression test
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2025-01-10 16:42:42 +01:00 |
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0ec6ea79ad
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Migrate from clkMhz to tCK entry in memspecs
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2024-02-23 12:04:22 +01:00 |
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a4342f7104
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Update expected traces for DDR5 and HBM3
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2023-08-15 11:28:03 +02:00 |
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b988544be2
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Enable PerBank refresh in HBM2,HBM3 regression test
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2023-08-15 10:58:10 +02:00 |
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81eaccf3d6
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Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3
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2023-08-15 10:58:10 +02:00 |
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599761c341
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Add regression test for DDR5
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2023-08-15 10:58:10 +02:00 |
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42d1caa372
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Add HBM3 regression test
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2023-08-15 10:58:10 +02:00 |
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