18 Commits

Author SHA1 Message Date
565e725cf6 Make dataLength parameter required for initiators 2025-08-06 09:37:12 +02:00
8c861d81c9 Decouple initiator clock from memory responses
Previously, the initiators were implicitly coupled to the responses of
the memory, calculating each new initiator clock relatively based on the
time of the BEGIN_RESP phase. This lead to an implicit coupling as
same rounding error of the initiator clock to the memory clock was
applied each time again.

Now, initiators are in itself self-clocked and only send requests based
on backpressure.
2025-08-06 09:35:07 +02:00
marcomoerz
bc8274433a Deserialize std::variant without throwing exception 2025-05-09 16:45:54 +02:00
marcomoerz
4120e9c35b Integrate DRAMUtils and new DRAMPower 2025-05-09 16:45:54 +02:00
939fc90f98 Remove hard-coded subdirectory paths for configs
Previously, the subdirectories in which the sub-json files were searched
in were hardcoded. Now, DRAMSys simply searches in the directory of the
base config, making this approach more flexible.
2025-04-15 14:56:35 +02:00
Lukas Steiner
f223e6c500 Merge branch 'feat/hbm3_sid' into 'develop'
Feat/hbm3 sid

See merge request ems/astdm/modeling.dram/dram.sys.5!96
2025-01-28 09:04:16 +00:00
581794b970 Allow responses to be sent back-to-back 2025-01-24 14:58:06 +01:00
ba94d9fd84 Have a one cycle END_RESP delay in the standard initiator 2025-01-24 14:43:06 +01:00
1225f6b044 Fix tests after ThinkDelayFw 2025-01-24 14:19:53 +01:00
7a8633d36e Implement stack ID for HBM3 2025-01-13 15:36:05 +01:00
a82efdbb3a Fix HBM3 regression test 2025-01-13 10:24:09 +01:00
aba5ba6e2e Switch to Open page policy for HBM3 regression test 2025-01-10 16:42:42 +01:00
0ec6ea79ad Migrate from clkMhz to tCK entry in memspecs 2024-02-23 12:04:22 +01:00
a4342f7104 Update expected traces for DDR5 and HBM3 2023-08-15 11:28:03 +02:00
b988544be2 Enable PerBank refresh in HBM2,HBM3 regression test 2023-08-15 10:58:10 +02:00
81eaccf3d6 Add lastCommandOn{C,R}asBus != scMaxTime check for HBM2 and HBM3 2023-08-15 10:58:10 +02:00
599761c341 Add regression test for DDR5 2023-08-15 10:58:10 +02:00
42d1caa372 Add HBM3 regression test 2023-08-15 10:58:10 +02:00