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Use smart pointers.

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This commit is contained in:
Lukas Steiner
2022-02-15 09:39:06 +01:00
parent f6cc09e82d
commit fcdd96c19e
20 changed files with 95 additions and 228 deletions
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3
DRAMSys/library/src/common/TlmRecorder.cpp
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@@ -34,6 +34,7 @@
* Robert Gernhardt
* Matthias Jung
* Eder F. Zulian
* Lukas Steiner
*/
#include <fstream>
@@ -69,7 +70,7 @@ TlmRecorder::TlmRecorder(const std::string &name, const std::string &dbName) :
PRINTDEBUGMESSAGE(name, "Starting new database transaction");
}
TlmRecorder::~TlmRecorder()
void TlmRecorder::finalize()
{
if (db)
closeConnection();

7
DRAMSys/library/src/common/TlmRecorder.h
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@@ -34,6 +34,7 @@
* Robert Gernhardt
* Matthias Jung
* Eder F. Zulian
* Lukas Steiner
*/
#ifndef TLMRECORDER_H
@@ -54,7 +55,8 @@ class TlmRecorder
{
public:
TlmRecorder(const std::string &name, const std::string &dbName);
~TlmRecorder();
TlmRecorder(const TlmRecorder&) = delete;
TlmRecorder(TlmRecorder&&) = default;
void recordMcConfig(std::string _mcconfig)
{
@@ -78,7 +80,7 @@ public:
void recordDebugMessage(const std::string &message, const sc_core::sc_time &time);
void updateDataStrobe(const sc_core::sc_time &begin, const sc_core::sc_time &end,
tlm::tlm_generic_payload &trans);
void closeConnection();
void finalize();
private:
struct Transaction
@@ -113,6 +115,7 @@ private:
static void executeSqlStatement(sqlite3_stmt *statement);
void openDB(const std::string &dbName);
void closeConnection();
void introduceTransactionSystem(tlm::tlm_generic_payload &trans);
void removeTransactionFromSystem(tlm::tlm_generic_payload &trans);

10
DRAMSys/library/src/controller/ControllerRecordable.cpp
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@@ -39,7 +39,7 @@
using namespace sc_core;
using namespace tlm;
ControllerRecordable::ControllerRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder)
ControllerRecordable::ControllerRecordable(const sc_module_name &name, TlmRecorder& tlmRecorder)
: Controller(name), tlmRecorder(tlmRecorder)
{
if (Configuration::getInstance().enableWindowing)
@@ -78,7 +78,7 @@ void ControllerRecordable::sendToDram(Command command, tlm_generic_payload *payl
if (command.isCasCommand())
{
TimeInterval dataStrobe = Configuration::getInstance().memSpec->getIntervalOnDataStrobe(command, *payload);
tlmRecorder->updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start,
tlmRecorder.updateDataStrobe(sc_time_stamp() + delay + dataStrobe.start,
sc_time_stamp() + delay + dataStrobe.end, *payload);
}
tlm_phase phase = command.toPhase();
@@ -103,7 +103,7 @@ void ControllerRecordable::recordPhase(tlm_generic_payload &trans, const tlm_pha
bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " +
std::to_string(col) + " id " + std::to_string(id) + " at " + recTime.to_string());
tlmRecorder->recordPhase(trans, phase, recTime);
tlmRecorder.recordPhase(trans, phase, recTime);
}
void ControllerRecordable::controllerMethod()
@@ -128,7 +128,7 @@ void ControllerRecordable::controllerMethod()
slidingAverageBufferDepth[index] = SC_ZERO_TIME;
}
tlmRecorder->recordBufferDepth(sc_time_stamp().to_seconds(), windowAverageBufferDepth);
tlmRecorder.recordBufferDepth(sc_time_stamp().to_seconds(), windowAverageBufferDepth);
Controller::controllerMethod();
@@ -136,7 +136,7 @@ void ControllerRecordable::controllerMethod()
lastNumberOfBeatsServed = numberOfBeatsServed;
sc_time windowActiveTime = activeTimeMultiplier * static_cast<double>(windowNumberOfBeatsServed);
double windowAverageBandwidth = windowActiveTime / windowSizeTime;
tlmRecorder->recordBandwidth(sc_time_stamp().to_seconds(), windowAverageBandwidth);
tlmRecorder.recordBandwidth(sc_time_stamp().to_seconds(), windowAverageBandwidth);
}
else
{

4
DRAMSys/library/src/controller/ControllerRecordable.h
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@@ -43,7 +43,7 @@
class ControllerRecordable final : public Controller
{
public:
ControllerRecordable(const sc_core::sc_module_name &name, TlmRecorder *tlmRecorder);
ControllerRecordable(const sc_core::sc_module_name &name, TlmRecorder& tlmRecorder);
~ControllerRecordable() override = default;
protected:
@@ -59,7 +59,7 @@ protected:
private:
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay);
TlmRecorder *tlmRecorder;
TlmRecorder& tlmRecorder;
sc_core::sc_event windowEvent;
sc_core::sc_time windowSizeTime;

77
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -116,23 +116,6 @@ DRAMSys::DRAMSys(const sc_core::sc_module_name &name,
}
}
DRAMSys::~DRAMSys()
{
delete arbiter;
for (auto dram : drams)
delete dram;
for (auto controller : controllers)
delete controller;
for (auto tlmChecker : playersTlmCheckers)
delete tlmChecker;
for (auto tlmChecker : controllersTlmCheckers)
delete tlmChecker;
}
void DRAMSys::logo()
{
#define GREENTXT(s) std::string(("\u001b[38;5;28m"+std::string((s))+"\033[0m"))
@@ -179,57 +162,45 @@ void DRAMSys::instantiateModules(const std::string &pathToResources,
// Create arbiter
if (config.arbiter == Configuration::Arbiter::Simple)
arbiter = new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
arbiter = std::unique_ptr<Arbiter>(new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig));
else if (config.arbiter == Configuration::Arbiter::Fifo)
arbiter = new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
arbiter = std::unique_ptr<Arbiter>(new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig));
else if (config.arbiter == Configuration::Arbiter::Reorder)
arbiter = new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
arbiter = std::unique_ptr<Arbiter>(new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig));
// Create controllers and DRAMs
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
std::string str = "controller" + std::to_string(i);
ControllerIF *controller = new Controller(str.c_str());
controllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram;
controllers.emplace_back(new Controller(("controller" + std::to_string(i)).c_str()));
if (memoryType == MemSpec::MemoryType::DDR3)
dram = new DramDDR3(str.c_str());
drams.emplace_back(new DramDDR3(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::DDR4)
dram = new DramDDR4(str.c_str());
drams.emplace_back(new DramDDR4(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::DDR5)
dram = new DramDDR5(str.c_str());
drams.emplace_back(new DramDDR5(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::WideIO)
dram = new DramWideIO(str.c_str());
drams.emplace_back(new DramWideIO(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
dram = new DramLPDDR4(str.c_str());
drams.emplace_back(new DramLPDDR4(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::LPDDR5)
dram = new DramLPDDR5(str.c_str());
drams.emplace_back(new DramLPDDR5(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::WideIO2)
dram = new DramWideIO2(str.c_str());
drams.emplace_back(new DramWideIO2(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::HBM2)
dram = new DramHBM2(str.c_str());
drams.emplace_back(new DramHBM2(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::GDDR5)
dram = new DramGDDR5(str.c_str());
drams.emplace_back(new DramGDDR5(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::GDDR5X)
dram = new DramGDDR5X(str.c_str());
drams.emplace_back(new DramGDDR5X(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::GDDR6)
dram = new DramGDDR6(str.c_str());
drams.emplace_back(new DramGDDR6(("dram" + std::to_string(i)).c_str()));
else if (memoryType == MemSpec::MemoryType::STTMRAM)
dram = new DramSTTMRAM(str.c_str());
drams.emplace_back(new DramSTTMRAM(("dram" + std::to_string(i)).c_str()));
drams.push_back(dram);
if (Configuration::getInstance().checkTLM2Protocol)
{
str = "TLMCheckerController" + std::to_string(i);
auto* controllerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
controllersTlmCheckers.push_back(controllerTlmChecker);
}
if (config.checkTLM2Protocol)
controllersTlmCheckers.push_back(new tlm_utils::tlm2_base_protocol_checker<>(("TlmCheckerController" + std::to_string(i)).c_str()));
}
}
@@ -239,22 +210,18 @@ void DRAMSys::bindSockets()
tSocket.bind(arbiter->tSocket);
if (config.checkTLM2Protocol)
for (unsigned i = 0; i < config.memSpec->numberOfChannels; i++)
{
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
if (config.checkTLM2Protocol)
{
arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
else
{
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
else
{
arbiter->iSocket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}

20
DRAMSys/library/src/simulation/DRAMSys.h
View File

@@ -41,6 +41,8 @@
#define DRAMSYS_H
#include <string>
#include <list>
#include <memory>
#include <systemc>
#include "dram/Dram.h"
@@ -57,16 +59,11 @@ class DRAMSys : public sc_core::sc_module
public:
tlm_utils::multi_passthrough_target_socket<DRAMSys> tSocket;
std::vector<tlm_utils::tlm2_base_protocol_checker<>*>
playersTlmCheckers;
SC_HAS_PROCESS(DRAMSys);
DRAMSys(const sc_core::sc_module_name &name,
const std::string &simulationToRun,
const std::string &pathToResources);
~DRAMSys() override;
protected:
DRAMSys(const sc_core::sc_module_name &name,
const std::string &simulationToRun,
@@ -74,29 +71,28 @@ protected:
bool initAndBind);
//TLM 2.0 Protocol Checkers
std::vector<tlm_utils::tlm2_base_protocol_checker<>*>
controllersTlmCheckers;
std::vector<tlm_utils::tlm2_base_protocol_checker<>*> controllersTlmCheckers;
// TODO: Each DRAM has a reorder buffer (check this!)
ReorderBuffer *reorder;
std::unique_ptr<ReorderBuffer> reorder;
// All transactions pass through the same arbiter
Arbiter *arbiter;
std::unique_ptr<Arbiter> arbiter;
// Each DRAM unit has a controller
std::vector<ControllerIF *> controllers;
std::vector<std::unique_ptr<ControllerIF>> controllers;
// DRAM units
std::vector<Dram *> drams;
std::vector<std::unique_ptr<Dram>> drams;
void report(const std::string &message);
void bindSockets();
private:
static void logo();
void instantiateModules(const std::string &pathToResources,
const std::string &amconfig);
void bindSockets();
static void setupDebugManager(const std::string &traceName);
};

93
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
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@@ -80,17 +80,17 @@ DRAMSysRecordable::DRAMSysRecordable(const sc_module_name &name,
report(headline);
}
DRAMSysRecordable::~DRAMSysRecordable()
void DRAMSysRecordable::end_of_simulation()
{
// Report power before TLM recorders are deleted
if (Configuration::getInstance().powerAnalysis)
{
for (auto dram : drams)
for (auto& dram : drams)
dram->reportPower();
}
for (auto rec : tlmRecorders)
delete rec;
for (auto& tlmRecorder : tlmRecorders)
tlmRecorder.finalize();
}
void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName)
@@ -99,17 +99,12 @@ void DRAMSysRecordable::setupTlmRecorders(const std::string &traceName)
for (std::size_t i = 0; i < Configuration::getInstance().memSpec->numberOfChannels; i++)
{
std::string dbName = traceName + std::string("_ch") + std::to_string(i) + ".tdb";
std::string recorderName = "tlmRecorder" + std::to_string(i);
auto* tlmRecorder = new TlmRecorder(recorderName, dbName);
tlmRecorder->recordMcConfig(Configuration::mcconfigUri);
tlmRecorder->recordMemspec(Configuration::memspecUri);
std::string traceNames = Configuration::getInstance().simulationName;
tlmRecorder->recordTraceNames(traceNames);
tlmRecorders.push_back(tlmRecorder);
tlmRecorders.emplace_back(recorderName, dbName);
tlmRecorders.back().recordMcConfig(Configuration::mcconfigUri);
tlmRecorders.back().recordMemspec(Configuration::memspecUri);
tlmRecorders.back().recordTraceNames(Configuration::getInstance().simulationName);
}
}
@@ -129,81 +124,45 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
// Create arbiter
if (config.arbiter == Configuration::Arbiter::Simple)
arbiter = new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
arbiter = std::unique_ptr<Arbiter>(new ArbiterSimple("arbiter", pathToResources + "configs/amconfigs/" + amconfig));
else if (config.arbiter == Configuration::Arbiter::Fifo)
arbiter = new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
arbiter = std::unique_ptr<Arbiter>(new ArbiterFifo("arbiter", pathToResources + "configs/amconfigs/" + amconfig));
else if (config.arbiter == Configuration::Arbiter::Reorder)
arbiter = new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig);
arbiter = std::unique_ptr<Arbiter>(new ArbiterReorder("arbiter", pathToResources + "configs/amconfigs/" + amconfig));
// Create controllers and DRAMs
MemSpec::MemoryType memoryType = config.memSpec->memoryType;
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
std::string str = "controller" + std::to_string(i);
ControllerIF *controller = new ControllerRecordable(str.c_str(), tlmRecorders[i]);
controllers.push_back(controller);
str = "dram" + std::to_string(i);
Dram *dram;
controllers.emplace_back(new ControllerRecordable(("controller" + std::to_string(i)).c_str(), tlmRecorders[i]));
if (memoryType == MemSpec::MemoryType::DDR3)
dram = new DramRecordable<DramDDR3>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramDDR3>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::DDR4)
dram = new DramRecordable<DramDDR4>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramDDR4>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::DDR5)
dram = new DramRecordable<DramDDR5>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramDDR5>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO)
dram = new DramRecordable<DramWideIO>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramWideIO>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR4)
dram = new DramRecordable<DramLPDDR4>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramLPDDR4>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::LPDDR5)
dram = new DramRecordable<DramLPDDR5>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramLPDDR5>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::WideIO2)
dram = new DramRecordable<DramWideIO2>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramWideIO2>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::HBM2)
dram = new DramRecordable<DramHBM2>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramHBM2>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR5)
dram = new DramRecordable<DramGDDR5>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramGDDR5>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR5X)
dram = new DramRecordable<DramGDDR5X>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramGDDR5X>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::GDDR6)
dram = new DramRecordable<DramGDDR6>(str.c_str(), tlmRecorders[i]);
drams.emplace_back(new DramRecordable<DramGDDR6>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
else if (memoryType == MemSpec::MemoryType::STTMRAM)
dram = new DramRecordable<DramSTTMRAM>(str.c_str(), tlmRecorders[i]);
drams.push_back(dram);
drams.emplace_back(new DramRecordable<DramSTTMRAM>(("dram" + std::to_string(i)).c_str(), tlmRecorders[i]));
if (config.checkTLM2Protocol)
{
str = "TLMCheckerController" + std::to_string(i);
auto* controllerTlmChecker = new tlm_utils::tlm2_base_protocol_checker<>(str.c_str());
controllersTlmCheckers.push_back(controllerTlmChecker);
}
}
}
void DRAMSysRecordable::bindSockets()
{
Configuration &config = Configuration::getInstance();
tSocket.bind(arbiter->tSocket);
if (config.checkTLM2Protocol)
{
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
arbiter->iSocket.bind(controllersTlmCheckers[i]->target_socket);
controllersTlmCheckers[i]->initiator_socket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
}
else
{
for (std::size_t i = 0; i < config.memSpec->numberOfChannels; i++)
{
arbiter->iSocket.bind(controllers[i]->tSocket);
controllers[i]->iSocket.bind(drams[i]->tSocket);
}
controllersTlmCheckers.emplace_back(new tlm_utils::tlm2_base_protocol_checker<>(("TLMCheckerController"
+ std::to_string(i)).c_str()));
}
}

8
DRAMSys/library/src/simulation/DRAMSysRecordable.h
View File

@@ -46,20 +46,18 @@ public:
const std::string &simulationToRun,
const std::string &pathToResources);
~DRAMSysRecordable() override;
private:
// Transaction Recorders (one per channel).
// They generate the output databases.
std::vector<TlmRecorder *> tlmRecorders;
std::vector<TlmRecorder> tlmRecorders;
void end_of_simulation() override;
void setupTlmRecorders(const std::string &traceName);
void instantiateModules(const std::string &traceName,
const std::string &pathToResources,
const std::string &amconfig);
void bindSockets();
};
#endif // DRAMSYSRECORDABLE_H

0
DRAMSys/simulator/LengthConverter.cpp → DRAMSys/library/src/simulation/LengthConverter.cpp
View File

0
DRAMSys/simulator/LengthConverter.h → DRAMSys/library/src/simulation/LengthConverter.h
View File

10
DRAMSys/library/src/simulation/dram/DramRecordable.cpp
View File

@@ -55,7 +55,7 @@ using namespace sc_core;
using namespace tlm;
template<class BaseDram>
DramRecordable<BaseDram>::DramRecordable(const sc_module_name &name, TlmRecorder *tlmRecorder)
DramRecordable<BaseDram>::DramRecordable(const sc_module_name &name, TlmRecorder& tlmRecorder)
: BaseDram(name), tlmRecorder(tlmRecorder)
{
// Create a thread that is triggered every $powerWindowSize
@@ -68,7 +68,7 @@ template<class BaseDram>
void DramRecordable<BaseDram>::reportPower()
{
BaseDram::reportPower();
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
tlmRecorder.recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().memSpec->numberOfDevices);
}
@@ -103,12 +103,12 @@ void DramRecordable<BaseDram>::recordPhase(tlm_generic_payload &trans, const tlm
bg) + " bank " + std::to_string(bank) + " row " + std::to_string(row) + " column " +
std::to_string(col) + " at " + recTime.to_string());
tlmRecorder->recordPhase(trans, phase, recTime);
tlmRecorder.recordPhase(trans, phase, recTime);
if (phaseNeedsEnd(phase))
{
recTime += this->memSpec->getExecutionTime(Command(phase), trans);
tlmRecorder->recordPhase(trans, getEndPhase(phase), recTime);
tlmRecorder.recordPhase(trans, getEndPhase(phase), recTime);
}
}
@@ -134,7 +134,7 @@ void DramRecordable<BaseDram>::powerWindow()
assert(!isEqual(this->DRAMPower->getEnergy().window_energy, 0.0));
// Store the time (in seconds) and the current average power (in mW) into the database
tlmRecorder->recordPower(sc_time_stamp().to_seconds(),
tlmRecorder.recordPower(sc_time_stamp().to_seconds(),
this->DRAMPower->getPower().window_average_power
* Configuration::getInstance().memSpec->numberOfDevices);

4
DRAMSys/library/src/simulation/dram/DramRecordable.h
View File

@@ -46,7 +46,7 @@ template<class BaseDram>
class DramRecordable final : public BaseDram
{
public:
DramRecordable(const sc_core::sc_module_name &name, TlmRecorder *);
DramRecordable(const sc_core::sc_module_name &name, TlmRecorder& tlmRecorder);
SC_HAS_PROCESS(DramRecordable);
void reportPower() override;
@@ -57,7 +57,7 @@ private:
void recordPhase(tlm::tlm_generic_payload &trans, const tlm::tlm_phase &phase, const sc_core::sc_time &delay);
TlmRecorder *tlmRecorder;
TlmRecorder& tlmRecorder;
sc_core::sc_time powerWindowSize = Configuration::getInstance().memSpec->tCK *
Configuration::getInstance().windowSize;

3
DRAMSys/simulator/StlPlayer.cpp
View File

@@ -48,10 +48,9 @@ StlPlayer::StlPlayer(const sc_module_name &name,
const sc_time &playerClk,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
TraceSetup *setup,
bool relative) :
TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests, needsLengthConverter),
TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests),
file(pathToTrace), relative(relative), playerClk(playerClk)
{
currentBuffer = &lineContents[0];

1
DRAMSys/simulator/StlPlayer.h
View File

@@ -69,7 +69,6 @@ public:
const sc_core::sc_time &playerClk,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
TraceSetup *setup,
bool relative);

15
DRAMSys/simulator/TraceSetup.cpp
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@@ -83,11 +83,6 @@ TraceSetup::TraceSetup(const std::string &uri,
if (value["maxPendingWriteRequests"].is_number_unsigned())
maxPendingWriteRequests = value["maxPendingWriteRequests"];
bool needsLengthConverter = false;
if (value["needsLengthConverter"].is_boolean())
needsLengthConverter = value["needsLengthConverter"];
std::string type;
// Defaulting to type "player" when not specified
@@ -117,12 +112,10 @@ TraceSetup::TraceSetup(const std::string &uri,
StlPlayer *player;
if (ext == "stl")
player = new StlPlayer(moduleName.c_str(), stlFile, playerClk,
maxPendingReadRequests, maxPendingWriteRequests, needsLengthConverter,
this, false);
maxPendingReadRequests, maxPendingWriteRequests, this, false);
else if (ext == "rstl")
player = new StlPlayer(moduleName.c_str(), stlFile, playerClk,
maxPendingReadRequests, maxPendingWriteRequests, needsLengthConverter,
this, true);
maxPendingReadRequests, maxPendingWriteRequests, this, true);
else
throw std::runtime_error("Unsupported file extension in " + name);
@@ -196,13 +189,13 @@ TraceSetup::TraceSetup(const std::string &uri,
players.push_back(std::unique_ptr<TrafficInitiator>(new TrafficGeneratorSequential(name.c_str(),
playerClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests,
needsLengthConverter, minAddress, maxAddress, rwRatio, addressIncrement, seed, this)));
minAddress, maxAddress, rwRatio, addressIncrement, seed, this)));
}
else
{
players.push_back(std::unique_ptr<TrafficInitiator>(new TrafficGeneratorRandom(name.c_str(),
playerClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests,
needsLengthConverter, minAddress, maxAddress, rwRatio, seed, this)));
minAddress, maxAddress, rwRatio, seed, this)));
}
totalTransactions += numRequests;

11
DRAMSys/simulator/TrafficGenerator.cpp
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@@ -46,11 +46,10 @@ TrafficGenerator::TrafficGenerator(const sc_module_name &name,
uint64_t numRequests,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
float rwRatio,
unsigned int seed,
TraceSetup *setup) :
TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests, needsLengthConverter),
TrafficInitiator(name, setup, maxPendingReadRequests, maxPendingWriteRequests),
generatorClk(generatorClk), numRequests(numRequests), rwRatio(rwRatio)
{
defaultDataLength = Configuration::getInstance().memSpec->bytesPerBurst;
@@ -110,14 +109,13 @@ TrafficGeneratorRandom::TrafficGeneratorRandom(const sc_core::sc_module_name &na
uint64_t numRequests,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
uint64_t minAddress,
uint64_t maxAddress,
float rwRatio,
unsigned int seed,
TraceSetup *setup) :
TrafficGenerator(name, generatorClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests,
needsLengthConverter, rwRatio, seed, setup)
rwRatio, seed, setup)
{
randomAddressDistribution = std::uniform_int_distribution<uint64_t> (minAddress, maxAddress);
}
@@ -132,7 +130,6 @@ TrafficGeneratorSequential::TrafficGeneratorSequential(const sc_core::sc_module_
uint64_t numRequests,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
uint64_t minAddress,
uint64_t maxAddress,
float rwRatio,
@@ -140,7 +137,7 @@ TrafficGeneratorSequential::TrafficGeneratorSequential(const sc_core::sc_module_
unsigned int seed,
TraceSetup *setup) :
TrafficGenerator(name, generatorClk, numRequests, maxPendingReadRequests, maxPendingWriteRequests,
needsLengthConverter, rwRatio, seed, setup),
rwRatio, seed, setup),
minAddress(minAddress), maxAddress(maxAddress), addressIncrement(addressIncrement),
currentAddress(minAddress)
{
@@ -161,7 +158,7 @@ TrafficGeneratorHammer::TrafficGeneratorHammer(const sc_core::sc_module_name &na
uint64_t numRequests,
uint64_t rowIncrement,
TraceSetup *setup) :
TrafficGenerator(name, generatorClk, numRequests, 1, 1, false, 1.0f, 1, setup), rowIncrement(rowIncrement)
TrafficGenerator(name, generatorClk, numRequests, 1, 1, 1.0f, 1, setup), rowIncrement(rowIncrement)
{
}

3
DRAMSys/simulator/TrafficGenerator.h
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@@ -52,7 +52,6 @@ protected:
uint64_t numRequests,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
float rwRatio,
unsigned int seed,
TraceSetup *setup);
@@ -79,7 +78,6 @@ public:
uint64_t numRequests,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
uint64_t minAddress,
uint64_t maxAddress,
float rwRatio,
@@ -100,7 +98,6 @@ public:
uint64_t numRequests,
unsigned int maxPendingReadRequests,
unsigned int maxPendingWriteRequests,
bool needsLengthConverter,
uint64_t minAddress,
uint64_t maxAddress,
float rwRatio,

10
DRAMSys/simulator/TrafficInitiator.cpp
View File

@@ -44,11 +44,10 @@ using namespace sc_core;
using namespace tlm;
TrafficInitiator::TrafficInitiator(const sc_module_name &name, TraceSetup *setup,
unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, bool needsLengthConverter) :
unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests) :
sc_module(name), payloadEventQueue(this, &TrafficInitiator::peqCallback),
setup(setup),
maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests),
mNeedsLengthConverter(needsLengthConverter)
maxPendingReadRequests(maxPendingReadRequests), maxPendingWriteRequests(maxPendingWriteRequests)
{
SC_METHOD(sendNextPayload);
iSocket.register_nb_transport_bw(this, &TrafficInitiator::nb_transport_bw);
@@ -130,8 +129,3 @@ bool TrafficInitiator::nextPayloadSendable() const
else
return true;
}
bool TrafficInitiator::needsLengthConverter() const
{
return mNeedsLengthConverter;
}

4
DRAMSys/simulator/TrafficInitiator.h
View File

@@ -57,10 +57,9 @@ class TrafficInitiator : public sc_core::sc_module
public:
tlm_utils::simple_initiator_socket<TrafficInitiator> iSocket;
TrafficInitiator(const sc_core::sc_module_name &name, TraceSetup *setup,
unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests, bool needsLengthConverter);
unsigned int maxPendingReadRequests, unsigned int maxPendingWriteRequests);
SC_HAS_PROCESS(TrafficInitiator);
virtual void sendNextPayload() = 0;
bool needsLengthConverter() const;
protected:
tlm_utils::peq_with_cb_and_phase<TrafficInitiator> payloadEventQueue;
@@ -76,7 +75,6 @@ protected:
unsigned int pendingWriteRequests = 0;
const unsigned int maxPendingReadRequests = 0;
const unsigned int maxPendingWriteRequests = 0;
const bool mNeedsLengthConverter = false;
bool payloadPostponed = false;
bool finished = false;

40
DRAMSys/simulator/main.cpp
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@@ -48,7 +48,6 @@
#include "simulation/DRAMSys.h"
#include "TraceSetup.h"
#include "TrafficInitiator.h"
#include "LengthConverter.h"
#ifdef RECORDING
#include "simulation/DRAMSysRecordable.h"
@@ -99,7 +98,6 @@ int sc_main(int argc, char **argv)
}
std::vector<std::unique_ptr<TrafficInitiator>> players;
std::list<LengthConverter> lengthConverters;
// Instantiate DRAMSys:
std::unique_ptr<DRAMSys> dramSys;
@@ -114,44 +112,12 @@ int sc_main(int argc, char **argv)
#endif
dramSys = std::unique_ptr<DRAMSys>(new DRAMSys("DRAMSys", simulationJson, resources));
// Instantiate STL Players:
// Instantiate STL Players (config of DRAMSys required!):
TraceSetup setup(simulationJson, resources, players);
// Bind STL Players with DRAMSys:
for (size_t i = 0; i < players.size(); i++)
{
if (Configuration::getInstance().checkTLM2Protocol)
{
std::string str = "TLMCheckerPlayer" + std::to_string(i);
auto* playerTlmChecker =
new tlm_utils::tlm2_base_protocol_checker<>(("TLMCheckerPlayer" + std::to_string(i)).c_str());
dramSys->playersTlmCheckers.push_back(playerTlmChecker);
if (players[i]->needsLengthConverter())
{
lengthConverters.emplace_back(("LengthConverter" + std::to_string(i)).c_str(), 64, false);
players[i]->iSocket.bind(lengthConverters.back().tSocket);
lengthConverters.back().iSocket.bind(dramSys->playersTlmCheckers.back()->target_socket);
}
else
{
players[i]->iSocket.bind(dramSys->playersTlmCheckers[i]->target_socket);
}
dramSys->playersTlmCheckers.back()->initiator_socket.bind(dramSys->tSocket);
}
else
{
if (players[i]->needsLengthConverter())
{
lengthConverters.emplace_back(("LengthConverter" + std::to_string(i)).c_str(), 64, false);
players[i]->iSocket.bind(lengthConverters.back().tSocket);
lengthConverters.back().iSocket.bind(dramSys->tSocket);
}
else
{
players[i]->iSocket.bind(dramSys->tSocket);
}
}
}
for (auto& player : players)
player->iSocket.bind(dramSys->tSocket);
// Store the starting of the simulation in wallclock time:
auto start = std::chrono::high_resolution_clock::now();