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Updated Readme. Reverted changes in ddr3_example.xml

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Johannes Feldmann
2018-12-12 11:12:20 +01:00
parent f389a649c4
commit fcbe8ecd5c
2 changed files with 45 additions and 59 deletions
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2
DRAMSys/library/resources/simulations/ddr3-example.xml
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@@ -8,7 +8,7 @@
<!-- Memory Device Specification: Which Device is on the DDR3 DIMM -->
<memspec src="MICRON_1Gb_DDR3-1600_8bit_G.xml"></memspec>
<!-- Addressmapping Configuration of the Memory Controller -->
<addressmapping src="ConGenTest.xml"></addressmapping>
<addressmapping src="am_ddr3_8x1Gbx8_dimm_p1KB_brc.xml"></addressmapping>
<!-- Memory Controller Configuration: -->
<mcconfig src="fifoStrict.xml"/>
<!--

102
README.md
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@@ -547,9 +547,9 @@ Below, the sub-configurations are listed and explained.
- **Address Mapping**
There are currently two different file formats to describe the address mapping. This software automatically chooses the correct interpreter using the file extension as selection criterion. So please make sure that all files have the correct extension.
There are currently two different file formats to describe the address mapping. This software automatically chooses the correct interpreter using the name of the xml root node as selection criterion.
- **XML file format**
- **Standard XML file format**
XML files describe the address mapping to be used in the simulation.
@@ -616,69 +616,55 @@ Below, the sub-configurations are listed and explained.
![Address Mapping Sample 2](DRAMSys/docs/images/am_wideio_brc.png)
- **JSON file format**
- **ConGen XML file format**
This file format is generated by ConGen. It does not have an unambiguous assignment of the address lines.
This file format is generated by ConGen.
The format delivers more information than needed for an address mapping.
Unused data:
- Block "Config": Gives you information about the ConGen configuration
- Key "Name": Name of the trace file which was used by ConGen
- All items of the array "Solutions" but the first one: Alternative solution with same result.
- Key "costs": Number of row misses which this configuration produces while playing the trace.
- "NAME": Name of the trace file which was used by ConGen
- "COSTS": Number of row misses which this configuration produces while playing the trace.
Used data:
- First item of array "Solution":
- "XOR": Array of row and bank bits which are connected with an xor. Order of the bit: bank1, bank2, ..., row1, row2, ...
- "bank_bits": Number of the addres bits which are connected to a bank bit
- "row_bits": Number of the addres bits which are connected to a row bit
- "CONFIG": Gives you information about the ConGen configuration
- "SOLUTION":
- Attribute "ID": Unique identifier for this solution. It is used to specify a certain solution.
- "XOR": Defines an xor connection of a bank and row bit
- "BANK_BIT": Number of an address bit which is connected to a bank bit
- "ROW_BIT": Number of an address bit which is connected to a row bit
```json
{
"Config": {
"numberOfBankBits": 3,
"numberOfRowBits": 14,
"numberOfColumnBits": 10,
"numberOfByteBits": 3,
"numberOfBLBits": 3
},
"Name": "trace_name",
"Solutions": [
{
"XOR": [
],
"Banks Rows": [
{
"bank_bits": [
27,
28,
29
],
"rows": {
"row_bits": [
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
],
"costs": 477468
},
"costs": 477468
}
]
}
]
}
```xml
<CONGEN>
<NAME>test</NAME>
<COSTS>84</COSTS>
<CONFIG>
<NUM_BANK_BITS>3</NUM_BANK_BITS>
<NUM_ROW_BITS>14</NUM_ROW_BITS>
<NUM_COLUMN_BITS>10</NUM_COLUMN_BITS>
<NUM_BL_BITS>3</NUM_BL_BITS>
<NUM_BYTE_BITS>3</NUM_BYTE_BITS>
</CONFIG>
<SOLUTION ID="0">
<XOR BANK="29" ROW="16"/>
<BANK_BIT>28</BANK_BIT>
<BANK_BIT>27</BANK_BIT>
<BANK_BIT>29</BANK_BIT>
<ROW_BIT>16</ROW_BIT>
<ROW_BIT>11</ROW_BIT>
<ROW_BIT>14</ROW_BIT>
<ROW_BIT>15</ROW_BIT>
<ROW_BIT>25</ROW_BIT>
<ROW_BIT>26</ROW_BIT>
<ROW_BIT>22</ROW_BIT>
<ROW_BIT>24</ROW_BIT>
<ROW_BIT>23</ROW_BIT>
<ROW_BIT>21</ROW_BIT>
<ROW_BIT>20</ROW_BIT>
<ROW_BIT>19</ROW_BIT>
<ROW_BIT>18</ROW_BIT>
<ROW_BIT>17</ROW_BIT>
</SOLUTION>
</CONGEN>
```