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Merge branch 'new_commands' into 'develop'

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Merge LPDDR5 into develop (corrected)

See merge request ems/astdm/modeling.dram/dram.sys!334
This commit is contained in:
Lukas Steiner
2021-12-14 08:02:29 +00:00
parent b67b1a19e5 c708be375f
commit eba6d4fd43
103 changed files with 5990 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
DRAMSys/library/CMakeLists.txt
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@@ -91,6 +91,7 @@ add_library(DRAMSysLibrary
src/configuration/memspec/MemSpecDDR4.cpp
src/configuration/memspec/MemSpecDDR5.cpp
src/configuration/memspec/MemSpecLPDDR4.cpp
src/configuration/memspec/MemSpecLPDDR5.cpp
src/configuration/memspec/MemSpecWideIO.cpp
src/configuration/memspec/MemSpecWideIO2.cpp
src/configuration/memspec/MemSpecGDDR5.cpp
@@ -109,6 +110,7 @@ add_library(DRAMSysLibrary
src/controller/checker/CheckerDDR4.cpp
src/controller/checker/CheckerDDR5.cpp
src/controller/checker/CheckerLPDDR4.cpp
src/controller/checker/CheckerLPDDR5.cpp
src/controller/checker/CheckerWideIO.cpp
src/controller/checker/CheckerWideIO2.cpp
src/controller/checker/CheckerGDDR5.cpp
@@ -129,6 +131,7 @@ add_library(DRAMSysLibrary
src/controller/refresh/RefreshManagerDummy.cpp
src/controller/refresh/RefreshManagerAllBank.cpp
src/controller/refresh/RefreshManagerPerBank.cpp
src/controller/refresh/RefreshManagerPer2Bank.cpp
src/controller/refresh/RefreshManagerSameBank.cpp
src/controller/respqueue/RespQueueIF.h
@@ -164,6 +167,7 @@ add_library(DRAMSysLibrary
src/simulation/dram/DramDDR4.cpp
src/simulation/dram/DramDDR5.cpp
src/simulation/dram/DramLPDDR4.cpp
src/simulation/dram/DramLPDDR5.cpp
src/simulation/dram/DramWideIO.cpp
src/simulation/dram/DramWideIO2.cpp
src/simulation/dram/DramGDDR5.cpp

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_1Gbx16_baroco.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
28,
29,
30
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_1Gbx16_robaco.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_1Gbx16_rocoba.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
8,
9,
10,
11,
12,
13
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_512Mbx16_baroco.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
27,
28,
29
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_512Mbx16_robaco.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
11,
12,
13
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr4_512Mbx16_rocoba.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BANK_BIT": [
5,
6,
7
],
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
8,
9,
10,
11,
12,
13
],
"ROW_BIT": [
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_1Gbx16_16B_robaco.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"BANK_BIT": [
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_1Gbx16_16B_rocoba.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
5,
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_1Gbx16_8B_robaco.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"BANK_BIT": [
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

43
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_1Gbx16_8B_rocoba.json Normal file
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@@ -0,0 +1,43 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_1Gbx16_BG_robacobg.json Normal file
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@@ -0,0 +1,45 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

45
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_1Gbx16_BG_rocobabg.json Normal file
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@@ -0,0 +1,45 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_512Mbx16_16B_robaco.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10
],
"BANK_BIT": [
11,
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_512Mbx16_16B_rocoba.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
5,
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_512Mbx16_8B_robaco.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11
],
"BANK_BIT": [
12,
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

42
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_512Mbx16_8B_rocoba.json Normal file
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@@ -0,0 +1,42 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
5,
9,
10,
11,
12,
13,
14
],
"BANK_BIT": [
6,
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

44
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_512Mbx16_BG_robacobg.json Normal file
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@@ -0,0 +1,44 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
7,
8,
9,
10,
11,
12
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
13,
14
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

44
DRAMSys/library/resources/configs/amconfigs/am_lpddr5_512Mbx16_BG_rocobabg.json Normal file
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@@ -0,0 +1,44 @@
{
"CONGEN": {
"BYTE_BIT": [
0
],
"COLUMN_BIT": [
1,
2,
3,
4,
9,
10,
11,
12,
13,
14
],
"BANKGROUP_BIT": [
5,
6
],
"BANK_BIT": [
7,
8
],
"ROW_BIT": [
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29
]
}
}

17
DRAMSys/library/resources/configs/mcconfigs/fr_fcfs_refp2b.json Normal file
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@@ -0,0 +1,17 @@
{
"mcconfig": {
"PagePolicy": "Open",
"Scheduler": "FrFcfs",
"SchedulerBuffer": "Bankwise",
"RequestBufferSize": 8,
"CmdMux": "Oldest",
"RespQueue": "Fifo",
"RefreshPolicy": "Per2Bank",
"RefreshMaxPostponed": 0,
"RefreshMaxPulledin": 0,
"PowerDownPolicy": "NoPowerDown",
"Arbiter": "Simple",
"MaxActiveTransactions": 128,
"RefreshManagement": false
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-0533.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-0533",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 3,
"PPD": 2,
"RPab": 3,
"RPpb": 3,
"RAS": 6,
"RCab": 9,
"RCpb": 8,
"FAW": 3,
"RRD": 2,
"RL": 6,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 5,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 520,
"REFIpb": 65,
"RFCab": 38,
"RFCpb": 19,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 1,
"pbR2pbR": 12,
"clkMhz": 133
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-1067.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-1067",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 5,
"PPD": 2,
"RPab": 6,
"RPpb": 5,
"RAS": 12,
"RCab": 17,
"RCpb": 16,
"FAW": 6,
"RRD": 2,
"RL": 8,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 10,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1041,
"REFIpb": 130,
"RFCab": 75,
"RFCpb": 38,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 2,
"pbR2pbR": 24,
"clkMhz": 267
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-1600.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-1600",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 8,
"PPD": 2,
"RPab": 9,
"RPpb": 8,
"RAS": 17,
"RCab": 26,
"RCpb": 24,
"FAW": 8,
"RRD": 2,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 14,
"WTR_L": 5,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1562,
"REFIpb": 195,
"RFCab": 112,
"RFCpb": 56,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 3,
"pbR2pbR": 36,
"clkMhz": 400
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-2133.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-2133",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 11,
"RRD": 3,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 4,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-2750.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-2750",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 14,
"RRD": 4,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_16B_LPDDR5-3200.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_16B_LPDDR5-3200",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 16,
"RRD": 4,
"RL": 18,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 10,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-0533.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-0533",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 3,
"PPD": 2,
"RPab": 3,
"RPpb": 3,
"RAS": 6,
"RCab": 9,
"RCpb": 8,
"FAW": 6,
"RRD": 2,
"RL": 6,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 5,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 520,
"REFIpb": 65,
"RFCab": 38,
"RFCpb": 19,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 2,
"pbR2pbR": 12,
"clkMhz": 133
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-1067.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-1067",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 5,
"PPD": 2,
"RPab": 6,
"RPpb": 5,
"RAS": 12,
"RCab": 17,
"RCpb": 16,
"FAW": 11,
"RRD": 3,
"RL": 8,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 10,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1041,
"REFIpb": 130,
"RFCab": 75,
"RFCpb": 38,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 3,
"pbR2pbR": 24,
"clkMhz": 267
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-1600.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-1600",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 8,
"PPD": 2,
"RPab": 9,
"RPpb": 8,
"RAS": 17,
"RCab": 26,
"RCpb": 24,
"FAW": 16,
"RRD": 4,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 14,
"WTR_L": 5,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1562,
"REFIpb": 195,
"RFCab": 112,
"RFCpb": 56,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 4,
"pbR2pbR": 36,
"clkMhz": 400
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-2133.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-2133",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 22,
"RRD": 6,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-2750.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-2750",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 28,
"RRD": 7,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 7,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-3200.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-3200",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 32,
"RRD": 8,
"RL": 18,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 10,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 8,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-3733.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-3733",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 9,
"PPD": 2,
"RPab": 10,
"RPpb": 9,
"RAS": 20,
"RCab": 30,
"RCpb": 28,
"FAW": 19,
"RRD": 5,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 16,
"WTR_L": 6,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1816,
"REFIpb": 226,
"RFCab": 131,
"RFCpb": 66,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 5,
"pbR2pbR": 42,
"clkMhz": 467
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-4267.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-4267",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 22,
"RRD": 6,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 6,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-4800.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-4800",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 11,
"PPD": 2,
"RPab": 13,
"RPpb": 11,
"RAS": 26,
"RCab": 38,
"RCpb": 36,
"FAW": 24,
"RRD": 6,
"RL": 13,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 3,
"RPRE": 0,
"RPST": 0,
"WL": 7,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 21,
"WTR_L": 8,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2343,
"REFIpb": 292,
"RFCab": 168,
"RFCpb": 84,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 6,
"pbR2pbR": 54,
"clkMhz": 600
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-5500.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-5500",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 28,
"RRD": 7,
"RL": 15,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 7,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-6000.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-6000",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 14,
"PPD": 2,
"RPab": 16,
"RPpb": 14,
"RAS": 32,
"RCab": 48,
"RCpb": 46,
"FAW": 31,
"RRD": 8,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 26,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2930,
"REFIpb": 366,
"RFCab": 211,
"RFCpb": 106,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 8,
"pbR2pbR": 68,
"clkMhz": 750
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_8B_LPDDR5-6400.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_8B_LPDDR5-6400",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 32,
"RRD": 8,
"RL": 17,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 8,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_BG_LPDDR5-3733.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-3733",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 9,
"PPD": 2,
"RPab": 10,
"RPpb": 9,
"RAS": 20,
"RCab": 30,
"RCpb": 28,
"FAW": 10,
"RRD": 3,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 16,
"WTR_L": 6,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1816,
"REFIpb": 226,
"RFCab": 131,
"RFCpb": 66,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 4,
"pbR2pbR": 42,
"clkMhz": 467
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_BG_LPDDR5-4267.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-4267",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 11,
"RRD": 3,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 150,
"RFCpb": 75,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 4,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_BG_LPDDR5-4800.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-4800",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 11,
"PPD": 2,
"RPab": 13,
"RPpb": 11,
"RAS": 26,
"RCab": 38,
"RCpb": 36,
"FAW": 12,
"RRD": 3,
"RL": 13,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 3,
"RPRE": 0,
"RPST": 0,
"WL": 7,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 21,
"WTR_L": 8,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2343,
"REFIpb": 292,
"RFCab": 168,
"RFCpb": 84,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 5,
"pbR2pbR": 54,
"clkMhz": 600
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_BG_LPDDR5-5500.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-5500",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 14,
"RRD": 4,
"RL": 15,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 193,
"RFCpb": 97,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_BG_LPDDR5-6000.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6000",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 14,
"PPD": 2,
"RPab": 16,
"RPpb": 14,
"RAS": 32,
"RCab": 48,
"RCpb": 46,
"FAW": 16,
"RRD": 4,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 26,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2930,
"REFIpb": 366,
"RFCab": 211,
"RFCpb": 106,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 68,
"clkMhz": 750
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_BG_LPDDR5-6400.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 65536,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_1Gbx16_BG_LPDDR5-6400",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 16,
"RRD": 4,
"RL": 17,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 224,
"RFCpb": 112,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-0533.json Normal file
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{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-0533",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 4,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 1,
"DQSS": 0,
"ESCKE": 3,
"FAW": 11,
"PPD": 4,
"RCD": 5,
"REFI": 1041,
"REFIPB": 130,
"RFCAB": 102,
"RFCPB": 51,
"RL": 6,
"RAS": 12,
"RPAB": 6,
"RPPB": 5,
"RCAB": 18,
"RCPB": 17,
"RPST": 0,
"RRD": 4,
"RTP": 8,
"SR": 4,
"WL": 4,
"WPRE": 2,
"WR": 6,
"WTR": 8,
"XP": 5,
"XSR": 104,
"RTRS": 1,
"clkMhz": 266
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-1066.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-1066",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 4,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 1,
"DQSS": 0,
"ESCKE": 3,
"FAW": 22,
"PPD": 4,
"RCD": 10,
"REFI": 2082,
"REFIPB": 260,
"RFCAB": 203,
"RFCPB": 102,
"RL": 10,
"RAS": 23,
"RPAB": 12,
"RPPB": 10,
"RCAB": 35,
"RCPB": 33,
"RPST": 0,
"RRD": 6,
"RTP": 8,
"SR": 8,
"WL": 6,
"WPRE": 2,
"WR": 10,
"WTR": 8,
"XP": 5,
"XSR": 207,
"RTRS": 1,
"clkMhz": 533
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-1600.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-1600",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 6,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 32,
"PPD": 4,
"RCD": 15,
"REFI": 3123,
"REFIPB": 390,
"RFCAB": 304,
"RFCPB": 152,
"RL": 14,
"RAS": 34,
"RPAB": 17,
"RPPB": 15,
"RCAB": 51,
"RCPB": 49,
"RPST": 0,
"RRD": 8,
"RTP": 8,
"SR": 12,
"WL": 8,
"WPRE": 2,
"WR": 15,
"WTR": 8,
"XP": 6,
"XSR": 310,
"RTRS": 1,
"clkMhz": 800
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-2133.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-2133",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 9,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 43,
"PPD": 4,
"RCD": 20,
"REFI": 4166,
"REFIPB": 520,
"RFCAB": 406,
"RFCPB": 203,
"RL": 20,
"RAS": 45,
"RPAB": 23,
"RPPB": 20,
"RCAB": 68,
"RCPB": 65,
"RPST": 0,
"RRD": 11,
"RTP": 9,
"SR": 17,
"WL": 10,
"WPRE": 2,
"WR": 20,
"WTR": 11,
"XP": 9,
"XSR": 414,
"RTRS": 1,
"clkMhz": 1066
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-2666.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-2666",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 10,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 54,
"PPD": 4,
"RCD": 24,
"REFI": 5205,
"REFIPB": 650,
"RFCAB": 507,
"RFCPB": 254,
"RL": 24,
"RAS": 56,
"RPAB": 28,
"RPPB": 24,
"RCAB": 84,
"RCPB": 80,
"RPST": 0,
"RRD": 14,
"RTP": 10,
"SR": 20,
"WL": 12,
"WPRE": 2,
"WR": 24,
"WTR": 14,
"XP": 10,
"XSR": 517,
"RTRS": 1,
"clkMhz": 1333
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-3200.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-3200",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 12,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 3,
"DQSS": 0,
"ESCKE": 3,
"FAW": 64,
"PPD": 4,
"RCD": 29,
"REFI": 6246,
"REFIPB": 780,
"RFCAB": 608,
"RFCPB": 304,
"RL": 28,
"RAS": 68,
"RPAB": 34,
"RPPB": 29,
"RCAB": 102,
"RCPB": 97,
"RPST": 0,
"RRD": 16,
"RTP": 12,
"SR": 24,
"WL": 14,
"WPRE": 2,
"WR": 29,
"WTR": 16,
"XP": 12,
"XSR": 460,
"RTRS": 1,
"clkMhz": 1600
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-3733.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-3733",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 15,
"CMDCKE": 4,
"DQS2DQ": 0,
"DQSCK": 3,
"DQSS": 0,
"ESCKE": 4,
"FAW": 75,
"PPD": 4,
"RCD": 34,
"REFI": 7297,
"REFIPB": 912,
"RFCAB": 711,
"RFCPB": 356,
"RL": 32,
"RAS": 79,
"RPAB": 40,
"RPPB": 34,
"RCAB": 119,
"RCPB": 113,
"RPST": 0,
"RRD": 19,
"RTP": 15,
"SR": 29,
"WL": 16,
"WPRE": 2,
"WR": 34,
"WTR": 19,
"XP": 15,
"XSR": 725,
"RTRS": 1,
"clkMhz": 1866
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_1Gbx16_LPDDR4-4266.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 131072,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_1Gbx16_LPDDR4-4266",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 17,
"CMDCKE": 4,
"DQS2DQ": 0,
"DQSCK": 4,
"DQSS": 0,
"ESCKE": 4,
"FAW": 86,
"PPD": 4,
"RCD": 39,
"REFI": 8341,
"REFIPB": 1042,
"RFCAB": 812,
"RFCPB": 406,
"RL": 36,
"RAS": 90,
"RPAB": 45,
"RPPB": 39,
"RCAB": 135,
"RCPB": 129,
"RPST": 0,
"RRD": 22,
"RTP": 17,
"SR": 33,
"WL": 18,
"WPRE": 2,
"WR": 39,
"WTR": 22,
"XP": 17,
"XSR": 828,
"RTRS": 1,
"clkMhz": 2133
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_16B_LPDDR5-0533.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_16B_LPDDR5-0533",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 3,
"PPD": 2,
"RPab": 3,
"RPpb": 3,
"RAS": 6,
"RCab": 9,
"RCpb": 8,
"FAW": 3,
"RRD": 2,
"RL": 6,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 5,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 520,
"REFIpb": 65,
"RFCab": 28,
"RFCpb": 16,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 1,
"pbR2pbR": 12,
"clkMhz": 133
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_16B_LPDDR5-1067.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_16B_LPDDR5-1067",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 5,
"PPD": 2,
"RPab": 6,
"RPpb": 5,
"RAS": 12,
"RCab": 17,
"RCpb": 16,
"FAW": 6,
"RRD": 2,
"RL": 8,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 10,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1041,
"REFIpb": 130,
"RFCab": 56,
"RFCpb": 32,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 2,
"pbR2pbR": 24,
"clkMhz": 267
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_16B_LPDDR5-1600.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_16B_LPDDR5-1600",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 8,
"PPD": 2,
"RPab": 9,
"RPpb": 8,
"RAS": 17,
"RCab": 26,
"RCpb": 24,
"FAW": 8,
"RRD": 2,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 14,
"WTR_L": 5,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1562,
"REFIpb": 195,
"RFCab": 84,
"RFCpb": 48,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 3,
"pbR2pbR": 36,
"clkMhz": 400
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_16B_LPDDR5-2133.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_16B_LPDDR5-2133",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 11,
"RRD": 3,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 112,
"RFCpb": 64,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 4,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_16B_LPDDR5-2750.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_16B_LPDDR5-2750",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 14,
"RRD": 4,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 145,
"RFCpb": 83,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_16B_LPDDR5-3200.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_16B_LPDDR5-3200",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 16,
"RRD": 4,
"RL": 18,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 10,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 168,
"RFCpb": 96,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-0533.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-0533",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 3,
"PPD": 2,
"RPab": 3,
"RPpb": 3,
"RAS": 6,
"RCab": 9,
"RCpb": 8,
"FAW": 6,
"RRD": 2,
"RL": 6,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 5,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 520,
"REFIpb": 65,
"RFCab": 28,
"RFCpb": 16,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 2,
"pbR2pbR": 12,
"clkMhz": 133
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-1067.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-1067",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 5,
"PPD": 2,
"RPab": 6,
"RPpb": 5,
"RAS": 12,
"RCab": 17,
"RCpb": 16,
"FAW": 11,
"RRD": 3,
"RL": 8,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 4,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 10,
"WTR_L": 4,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1041,
"REFIpb": 130,
"RFCab": 56,
"RFCpb": 32,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 3,
"pbR2pbR": 24,
"clkMhz": 267
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-1600.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-1600",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 8,
"PPD": 2,
"RPab": 9,
"RPpb": 8,
"RAS": 17,
"RCab": 26,
"RCpb": 24,
"FAW": 16,
"RRD": 4,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 14,
"WTR_L": 5,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1562,
"REFIpb": 195,
"RFCab": 84,
"RFCpb": 48,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 4,
"pbR2pbR": 36,
"clkMhz": 400
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-2133.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-2133",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 22,
"RRD": 6,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 0,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 112,
"RFCpb": 64,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 6,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-2750.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-2750",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 28,
"RRD": 7,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 145,
"RFCpb": 83,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 7,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-3200.json Normal file
View File

@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 4,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-3200",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 32,
"RRD": 8,
"RL": 18,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 10,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 168,
"RFCpb": 96,
"RTRS": 1,
"BL_n_min_16": 8,
"BL_n_max_16": 8,
"BL_n_L_16": 8,
"BL_n_S_16": 8,
"BL_n_min_32": 8,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 8,
"pbR2act": 8,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-3733.json Normal file
View File

@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-3733",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 9,
"PPD": 2,
"RPab": 10,
"RPpb": 9,
"RAS": 20,
"RCab": 30,
"RCpb": 28,
"FAW": 19,
"RRD": 5,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 16,
"WTR_L": 6,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1816,
"REFIpb": 226,
"RFCab": 98,
"RFCpb": 56,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 5,
"pbR2pbR": 42,
"clkMhz": 467
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-4267.json Normal file
View File

@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-4267",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 22,
"RRD": 6,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 112,
"RFCpb": 64,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 6,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-4800.json Normal file
View File

@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-4800",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 11,
"PPD": 2,
"RPab": 13,
"RPpb": 11,
"RAS": 26,
"RCab": 38,
"RCpb": 36,
"FAW": 24,
"RRD": 6,
"RL": 13,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 3,
"RPRE": 0,
"RPST": 0,
"WL": 7,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 21,
"WTR_L": 8,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2343,
"REFIpb": 292,
"RFCab": 126,
"RFCpb": 72,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 6,
"pbR2pbR": 54,
"clkMhz": 600
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-5500.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-5500",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 28,
"RRD": 7,
"RL": 15,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 145,
"RFCpb": 83,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 7,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-6000.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-6000",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 14,
"PPD": 2,
"RPab": 16,
"RPpb": 14,
"RAS": 32,
"RCab": 48,
"RCpb": 46,
"FAW": 31,
"RRD": 8,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 26,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2930,
"REFIpb": 366,
"RFCab": 158,
"RFCpb": 91,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 8,
"pbR2pbR": 68,
"clkMhz": 750
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_8B_LPDDR5-6400.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 32,
"dataRate": 8,
"nbrOfBankGroups": 1,
"nbrOfBanks": 8,
"nbrOfColumns": 2048,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_8B_LPDDR5-6400",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 32,
"RRD": 8,
"RL": 17,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 168,
"RFCpb": 96,
"RTRS": 1,
"BL_n_min_16": 4,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 4,
"BL_n_min_32": 4,
"BL_n_max_32": 4,
"BL_n_L_32": 4,
"BL_n_S_32": 4,
"pbR2act": 8,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_BG_LPDDR5-3733.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_BG_LPDDR5-3733",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 9,
"PPD": 2,
"RPab": 10,
"RPpb": 9,
"RAS": 20,
"RCab": 30,
"RCpb": 28,
"FAW": 10,
"RRD": 3,
"RL": 10,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 16,
"WTR_L": 6,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 1816,
"REFIpb": 226,
"RFCab": 98,
"RFCpb": 56,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 4,
"pbR2pbR": 42,
"clkMhz": 467
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_BG_LPDDR5-4267.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_BG_LPDDR5-4267",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 10,
"PPD": 2,
"RPab": 12,
"RPpb": 10,
"RAS": 23,
"RCab": 34,
"RCpb": 32,
"FAW": 11,
"RRD": 3,
"RL": 12,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 2,
"RPRE": 0,
"RPST": 0,
"WL": 6,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 19,
"WTR_L": 7,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2083,
"REFIpb": 260,
"RFCab": 112,
"RFCpb": 64,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 4,
"pbR2pbR": 48,
"clkMhz": 533
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_BG_LPDDR5-4800.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_BG_LPDDR5-4800",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 11,
"PPD": 2,
"RPab": 13,
"RPpb": 11,
"RAS": 26,
"RCab": 38,
"RCpb": 36,
"FAW": 12,
"RRD": 3,
"RL": 13,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 3,
"RPRE": 0,
"RPST": 0,
"WL": 7,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 21,
"WTR_L": 8,
"WTR_S": 4,
"CCDMW": 16,
"REFI": 2343,
"REFIpb": 292,
"RFCab": 126,
"RFCpb": 72,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 5,
"pbR2pbR": 54,
"clkMhz": 600
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_BG_LPDDR5-5500.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_BG_LPDDR5-5500",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 13,
"PPD": 2,
"RPab": 15,
"RPpb": 13,
"RAS": 29,
"RCab": 44,
"RCpb": 42,
"FAW": 14,
"RRD": 4,
"RL": 15,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 8,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 24,
"WTR_L": 9,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2688,
"REFIpb": 335,
"RFCab": 145,
"RFCpb": 83,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 62,
"clkMhz": 688
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_BG_LPDDR5-6000.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_BG_LPDDR5-6000",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 14,
"PPD": 2,
"RPab": 16,
"RPpb": 14,
"RAS": 32,
"RCab": 48,
"RCpb": 46,
"FAW": 16,
"RRD": 4,
"RL": 16,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 26,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 2930,
"REFIpb": 366,
"RFCab": 158,
"RFCpb": 91,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 68,
"clkMhz": 750
}
}
}

59
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_BG_LPDDR5-6400.json Normal file
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@@ -0,0 +1,59 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 8,
"nbrOfBankGroups": 4,
"nbrOfBanks": 16,
"nbrOfColumns": 1024,
"nbrOfRows": 32768,
"nbrOfRanks": 1,
"nbrOfChannels": 1,
"width": 16,
"per2BankOffset": 8
},
"memoryId": "JEDEC_512Mbx16_BG_LPDDR5-6400",
"memoryType": "LPDDR5",
"memtimingspec": {
"RCD": 15,
"PPD": 2,
"RPab": 17,
"RPpb": 15,
"RAS": 34,
"RCab": 51,
"RCpb": 48,
"FAW": 16,
"RRD": 4,
"RL": 17,
"WCK2CK": 0,
"WCK2DQO": 1,
"RBTP": 4,
"RPRE": 0,
"RPST": 0,
"WL": 9,
"WCK2DQI": 0,
"WPRE": 0,
"WPST": 0,
"WR": 28,
"WTR_L": 10,
"WTR_S": 5,
"CCDMW": 16,
"REFI": 3124,
"REFIpb": 390,
"RFCab": 168,
"RFCpb": 96,
"RTRS": 1,
"BL_n_min_16": 2,
"BL_n_max_16": 4,
"BL_n_L_16": 4,
"BL_n_S_16": 2,
"BL_n_min_32": 6,
"BL_n_max_32": 8,
"BL_n_L_32": 8,
"BL_n_S_32": 2,
"pbR2act": 6,
"pbR2pbR": 72,
"clkMhz": 800
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-0533.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-0533",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 4,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 1,
"DQSS": 0,
"ESCKE": 3,
"FAW": 11,
"PPD": 4,
"RCD": 5,
"REFI": 1041,
"REFIPB": 130,
"RFCAB": 75,
"RFCPB": 38,
"RL": 6,
"RAS": 12,
"RPAB": 6,
"RPPB": 5,
"RCAB": 18,
"RCPB": 17,
"RPST": 0,
"RRD": 4,
"RTP": 8,
"SR": 4,
"WL": 4,
"WPRE": 2,
"WR": 6,
"WTR": 8,
"XP": 5,
"XSR": 77,
"RTRS": 1,
"clkMhz": 266
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-1066.json Normal file
View File

@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-1066",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 4,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 1,
"DQSS": 0,
"ESCKE": 3,
"FAW": 22,
"PPD": 4,
"RCD": 10,
"REFI": 2082,
"REFIPB": 260,
"RFCAB": 150,
"RFCPB": 75,
"RL": 10,
"RAS": 23,
"RPAB": 12,
"RPPB": 10,
"RCAB": 35,
"RCPB": 33,
"RPST": 0,
"RRD": 6,
"RTP": 8,
"SR": 8,
"WL": 6,
"WPRE": 2,
"WR": 10,
"WTR": 8,
"XP": 5,
"XSR": 154,
"RTRS": 1,
"clkMhz": 533
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-1600.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-1600",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 6,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 32,
"PPD": 4,
"RCD": 15,
"REFI": 3123,
"REFIPB": 390,
"RFCAB": 224,
"RFCPB": 112,
"RL": 14,
"RAS": 34,
"RPAB": 17,
"RPPB": 15,
"RCAB": 51,
"RCPB": 49,
"RPST": 0,
"RRD": 8,
"RTP": 8,
"SR": 12,
"WL": 8,
"WPRE": 2,
"WR": 15,
"WTR": 8,
"XP": 6,
"XSR": 230,
"RTRS": 1,
"clkMhz": 800
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-2133.json Normal file
View File

@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-2133",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 9,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 43,
"PPD": 4,
"RCD": 20,
"REFI": 4166,
"REFIPB": 520,
"RFCAB": 299,
"RFCPB": 150,
"RL": 20,
"RAS": 45,
"RPAB": 23,
"RPPB": 20,
"RCAB": 68,
"RCPB": 65,
"RPST": 0,
"RRD": 11,
"RTP": 9,
"SR": 17,
"WL": 10,
"WPRE": 2,
"WR": 20,
"WTR": 11,
"XP": 9,
"XSR": 307,
"RTRS": 1,
"clkMhz": 1066
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-2666.json Normal file
View File

@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-2666",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 10,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 2,
"DQSS": 0,
"ESCKE": 3,
"FAW": 54,
"PPD": 4,
"RCD": 24,
"REFI": 5205,
"REFIPB": 650,
"RFCAB": 374,
"RFCPB": 187,
"RL": 24,
"RAS": 56,
"RPAB": 28,
"RPPB": 24,
"RCAB": 84,
"RCPB": 80,
"RPST": 0,
"RRD": 14,
"RTP": 10,
"SR": 20,
"WL": 12,
"WPRE": 2,
"WR": 24,
"WTR": 14,
"XP": 10,
"XSR": 384,
"RTRS": 1,
"clkMhz": 1333
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-3200.json Normal file
View File

@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-3200",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 12,
"CMDCKE": 3,
"DQS2DQ": 0,
"DQSCK": 3,
"DQSS": 0,
"ESCKE": 3,
"FAW": 64,
"PPD": 4,
"RCD": 29,
"REFI": 6246,
"REFIPB": 780,
"RFCAB": 448,
"RFCPB": 224,
"RL": 28,
"RAS": 68,
"RPAB": 34,
"RPPB": 29,
"RCAB": 102,
"RCPB": 97,
"RPST": 0,
"RRD": 16,
"RTP": 12,
"SR": 24,
"WL": 14,
"WPRE": 2,
"WR": 29,
"WTR": 16,
"XP": 12,
"XSR": 460,
"RTRS": 1,
"clkMhz": 1600
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-3733.json Normal file
View File

@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-3733",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 15,
"CMDCKE": 4,
"DQS2DQ": 0,
"DQSCK": 3,
"DQSS": 0,
"ESCKE": 4,
"FAW": 75,
"PPD": 4,
"RCD": 34,
"REFI": 7297,
"REFIPB": 912,
"RFCAB": 524,
"RFCPB": 262,
"RL": 32,
"RAS": 79,
"RPAB": 40,
"RPPB": 34,
"RCAB": 119,
"RCPB": 113,
"RPST": 0,
"RRD": 19,
"RTP": 15,
"SR": 29,
"WL": 16,
"WPRE": 2,
"WR": 34,
"WTR": 19,
"XP": 15,
"XSR": 538,
"RTRS": 1,
"clkMhz": 1866
}
}
}

50
DRAMSys/library/resources/configs/memspecs/JEDEC_512Mbx16_LPDDR4-4266.json Normal file
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@@ -0,0 +1,50 @@
{
"memspec": {
"memarchitecturespec": {
"burstLength": 16,
"dataRate": 2,
"nbrOfBanks": 8,
"nbrOfColumns": 1024,
"nbrOfRanks": 1,
"nbrOfRows": 65536,
"width": 16,
"nbrOfChannels": 1
},
"memoryId": "JEDEC_512Mbx16_LPDDR4-4266",
"memoryType": "LPDDR4",
"memtimingspec": {
"CCD": 8,
"CKE": 17,
"CMDCKE": 4,
"DQS2DQ": 0,
"DQSCK": 4,
"DQSS": 0,
"ESCKE": 4,
"FAW": 86,
"PPD": 4,
"RCD": 39,
"REFI": 8341,
"REFIPB": 1042,
"RFCAB": 599,
"RFCPB": 300,
"RL": 36,
"RAS": 90,
"RPAB": 45,
"RPPB": 39,
"RCAB": 135,
"RCPB": 129,
"RPST": 0,
"RRD": 22,
"RTP": 17,
"SR": 33,
"WL": 18,
"WPRE": 2,
"WR": 39,
"WTR": 22,
"XP": 17,
"XSR": 615,
"RTRS": 1,
"clkMhz": 2133
}
}
}

19
DRAMSys/library/resources/configs/simulator/example.json Normal file
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@@ -0,0 +1,19 @@
{
"simconfig": {
"AddressOffset": 0,
"CheckTLM2Protocol": false,
"DatabaseRecording": true,
"Debug": false,
"ECCControllerMode": "Disabled",
"EnableWindowing": false,
"ErrorCSVFile": "",
"ErrorChipSeed": 42,
"PowerAnalysis": false,
"SimulationName": "example",
"SimulationProgressBar": true,
"StoreMode": "NoStorage",
"ThermalSimulation": false,
"UseMalloc": false,
"WindowSize": 1000
}
}

16
DRAMSys/library/resources/simulations/lpddr5-example.json Normal file
View File

@@ -0,0 +1,16 @@
{
"simulation": {
"addressmapping": "am_lpddr5_1Gbx16_BG_rocobabg.json",
"mcconfig": "fr_fcfs_refp2b.json",
"memspec": "JEDEC_1Gbx16_BG_LPDDR5-6400.json",
"simconfig": "example.json",
"simulationid": "lpddr5-example",
"thermalconfig": "config.json",
"tracesetup": [
{
"clkMhz": 200,
"name": "ddr3_example.stl"
}
]
}
}

5
DRAMSys/library/src/configuration/Configuration.cpp
View File

@@ -46,6 +46,7 @@
#include "memspec/MemSpecDDR5.h"
#include "memspec/MemSpecWideIO.h"
#include "memspec/MemSpecLPDDR4.h"
#include "memspec/MemSpecLPDDR5.h"
#include "memspec/MemSpecWideIO2.h"
#include "memspec/MemSpecHBM2.h"
#include "memspec/MemSpecGDDR5.h"
@@ -161,6 +162,8 @@ void Configuration::setParameter(const std::string &name, const nlohmann::json &
refreshPolicy = RefreshPolicy::AllBank;
else if (value == "PerBank" || value == "Bankwise")
refreshPolicy = RefreshPolicy::PerBank;
else if (value == "Per2Bank")
refreshPolicy = RefreshPolicy::Per2Bank;
else if (value == "SameBank" || value == "Groupwise")
refreshPolicy = RefreshPolicy::SameBank;
else
@@ -348,6 +351,8 @@ void Configuration::loadMemSpec(Configuration &config, const std::string &_memsp
memSpec = new MemSpecDDR5(jMemSpec);
else if (memoryType == "LPDDR4")
memSpec = new MemSpecLPDDR4(jMemSpec);
else if (memoryType == "LPDDR5")
memSpec = new MemSpecLPDDR5(jMemSpec);
else if (memoryType == "WIDEIO_SDR")
memSpec = new MemSpecWideIO(jMemSpec);
else if (memoryType == "WIDEIO2")

2
DRAMSys/library/src/configuration/Configuration.h
View File

@@ -73,7 +73,7 @@ public:
enum class RespQueue {Fifo, Reorder} respQueue = RespQueue::Fifo;
enum class Arbiter {Simple, Fifo, Reorder} arbiter = Arbiter::Simple;
unsigned int requestBufferSize = 8;
enum class RefreshPolicy {NoRefresh, AllBank, PerBank, SameBank} refreshPolicy = RefreshPolicy::AllBank;
enum class RefreshPolicy {NoRefresh, PerBank, Per2Bank, SameBank, AllBank} refreshPolicy = RefreshPolicy::AllBank;
unsigned int refreshMaxPostponed = 0;
unsigned int refreshMaxPulledin = 0;
enum class PowerDownPolicy {NoPowerDown, Staggered} powerDownPolicy = PowerDownPolicy::NoPowerDown;

2
DRAMSys/library/src/configuration/memspec/MemSpec.h
View File

@@ -71,7 +71,7 @@ public:
const sc_core::sc_time tCK;
const std::string memoryId;
const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, WideIO,
const enum class MemoryType {DDR3, DDR4, DDR5, LPDDR4, LPDDR5, WideIO,
WideIO2, GDDR5, GDDR5X, GDDR6, HBM2, STTMRAM} memoryType;
virtual ~MemSpec() = default;

184
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.cpp Normal file
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@@ -0,0 +1,184 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include <iostream>
#include "../../common/utils.h"
#include "MemSpecLPDDR5.h"
using namespace sc_core;
using namespace tlm;
using json = nlohmann::json;
MemSpecLPDDR5::MemSpecLPDDR5(json &memspec)
: MemSpec(memspec, MemoryType::LPDDR5,
parseUint(memspec["memarchitecturespec"],"nbrOfChannels"),
parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"],"nbrOfBanks"),
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
/ parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups"),
parseUint(memspec["memarchitecturespec"],"nbrOfBanks")
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
parseUint(memspec["memarchitecturespec"], "nbrOfBankGroups")
* parseUint(memspec["memarchitecturespec"],"nbrOfRanks"),
1),
per2BankOffset(parseUint(memspec["memarchitecturespec"], "per2BankOffset")),
tREFI (tCK * parseUint(memspec["memtimingspec"], "REFI")),
tREFIpb (tCK * parseUint(memspec["memtimingspec"], "REFIpb")),
tRFCab (tCK * parseUint(memspec["memtimingspec"], "RFCab")),
tRFCpb (tCK * parseUint(memspec["memtimingspec"], "RFCpb")),
tRPab (tCK * parseUint(memspec["memtimingspec"], "RPab")),
tRPpb (tCK * parseUint(memspec["memtimingspec"], "RPpb")),
tRCab (tCK * parseUint(memspec["memtimingspec"], "RCab")),
tRCpb (tCK * parseUint(memspec["memtimingspec"], "RCpb")),
tPPD (tCK * parseUint(memspec["memtimingspec"], "PPD")),
tRAS (tCK * parseUint(memspec["memtimingspec"], "RAS")),
tRCD (tCK * parseUint(memspec["memtimingspec"], "RCD")),
tFAW (tCK * parseUint(memspec["memtimingspec"], "FAW")),
tRRD (tCK * parseUint(memspec["memtimingspec"], "RRD")),
//tCCD (tCK * parseUint(memspec["memtimingspec"], "CCD")),
tRL (tCK * parseUint(memspec["memtimingspec"], "RL")),
//tRPST (tCK * parseUint(memspec["memtimingspec"], "RPST")),
//tDQSCK (tCK * parseUint(memspec["memtimingspec"], "DQSCK")),
tRBTP (tCK * parseUint(memspec["memtimingspec"], "RBTP")),
tWL (tCK * parseUint(memspec["memtimingspec"], "WL")),
//tDQSS (tCK * parseUint(memspec["memtimingspec"], "DQSS")),
//tDQS2DQ (tCK * parseUint(memspec["memtimingspec"], "DQS2DQ")),
tWR (tCK * parseUint(memspec["memtimingspec"], "WR")),
//tWPRE (tCK * parseUint(memspec["memtimingspec"], "WPRE")),
//tWTR (tCK * parseUint(memspec["memtimingspec"], "WTR")),
//tXP (tCK * parseUint(memspec["memtimingspec"] "XP")),
//tSR (tCK * parseUint(memspec["memtimingspec"], "SR")),
//tXSR (tCK * parseUint(memspec["memtimingspec"], "XSR")),
//tESCKE (tCK * parseUint(memspec["memtimingspec"], "ESCKE")),
//tCKE (tCK * parseUint(memspec["memtimingspec"], "CKE")),
//tCMDCKE (tCK * parseUint(memspec["memtimingspec"], "CMDCKE")),
BL_n_min_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_min_16")),
BL_n_max_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_max_16")),
BL_n_L_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_L_16")),
BL_n_S_16(tCK * parseUint(memspec["memtimingspec"], "BL_n_S_16")),
BL_n_min_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_min_32")),
BL_n_max_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_max_32")),
BL_n_L_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_L_32")),
BL_n_S_32(tCK * parseUint(memspec["memtimingspec"], "BL_n_S_32")),
tWTR_L (tCK * parseUint(memspec["memtimingspec"], "WTR_L")),
tWTR_S (tCK * parseUint(memspec["memtimingspec"], "WTR_S")),
tWCK2DQO(tCK * parseUint(memspec["memtimingspec"], "WCK2DQO")),
tpbR2act(tCK * parseUint(memspec["memtimingspec"], "pbR2act")),
tpbR2pbR(tCK * parseUint(memspec["memtimingspec"], "tpbR2pbR")),
tRTRS (tCK * parseUint(memspec["memtimingspec"], "RTRS"))
{
commandLengthInCycles[Command::ACT] = 2;
uint64_t deviceSizeBits = static_cast<uint64_t>(banksPerRank) * numberOfRows * numberOfColumns * bitWidth;
uint64_t deviceSizeBytes = deviceSizeBits / 8;
memorySizeBytes = deviceSizeBytes * numberOfRanks * numberOfChannels;
std::cout << headline << std::endl;
std::cout << "Memory Configuration:" << std::endl << std::endl;
std::cout << " Memory type: " << "LPDDR5" << std::endl;
std::cout << " Memory size in bytes: " << memorySizeBytes << std::endl;
std::cout << " Channels: " << numberOfChannels << std::endl;
std::cout << " Ranks per channel: " << numberOfRanks << std::endl;
std::cout << " Banks per rank: " << banksPerRank << std::endl;
std::cout << " Rows per bank: " << numberOfRows << std::endl;
std::cout << " Columns per row: " << numberOfColumns << std::endl;
std::cout << " Device width in bits: " << bitWidth << std::endl;
std::cout << " Device size in bits: " << deviceSizeBits << std::endl;
std::cout << " Device size in bytes: " << deviceSizeBytes << std::endl;
std::cout << std::endl;
}
sc_time MemSpecLPDDR5::getRefreshIntervalAB() const
{
return tREFI;
}
sc_time MemSpecLPDDR5::getRefreshIntervalPB() const
{
return tREFIpb;
}
sc_time MemSpecLPDDR5::getRefreshIntervalP2B() const
{
return tREFIpb;
}
unsigned MemSpecLPDDR5::getPer2BankOffset() const
{
return per2BankOffset;
}
sc_time MemSpecLPDDR5::getExecutionTime(Command command, const tlm_generic_payload &) const
{
if (command == Command::PREPB)
return tRPpb;
else if (command == Command::PREAB)
return tRPab;
else if (command == Command::ACT)
return tRCD + tCK;
else if (command == Command::RD)
return tRL + burstDuration;
else if (command == Command::RDA)
return burstDuration + tRBTP + tRPpb;
else if (command == Command::WR)
return tWL + burstDuration;
else if (command == Command::WRA)
return tWL + burstDuration + tWR + tRPpb;
else if (command == Command::REFAB)
return tRFCab;
else if (command == Command::REFPB || command == Command::REFP2B)
return tRFCpb;
else
{
SC_REPORT_FATAL("getExecutionTime",
"command not known or command doesn't have a fixed execution time");
return SC_ZERO_TIME;
}
}
TimeInterval MemSpecLPDDR5::getIntervalOnDataStrobe(Command command, const tlm_generic_payload &) const
{
if (command == Command::RD || command == Command::RDA)
return {tRL, tRL + burstDuration};
else if (command == Command::WR || command == Command::WRA)
return {tWL, tWL + burstDuration};
else
{
SC_REPORT_FATAL("MemSpecLPDDR5", "Method was called with invalid argument");
return {};
}
}

114
DRAMSys/library/src/configuration/memspec/MemSpecLPDDR5.h Normal file
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@@ -0,0 +1,114 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#ifndef MEMSPECLPDDR5_H
#define MEMSPECLPDDR5_H
#include <systemc>
#include "MemSpec.h"
#include "../../common/third_party/nlohmann/single_include/nlohmann/json.hpp"
class MemSpecLPDDR5 final : public MemSpec
{
public:
explicit MemSpecLPDDR5(nlohmann::json &memspec);
// Memspec Variables:
const sc_core::sc_time tREFI;
const sc_core::sc_time tREFIpb;
const sc_core::sc_time tRFCab;
const sc_core::sc_time tRFCpb;
const sc_core::sc_time tRAS;
const sc_core::sc_time tRPab;
const sc_core::sc_time tRPpb;
const sc_core::sc_time tRCpb;
const sc_core::sc_time tRCab;
const sc_core::sc_time tPPD;
const sc_core::sc_time tRCD;
const sc_core::sc_time tFAW;
const sc_core::sc_time tRRD;
//const sc_core::sc_time tCCD;
const sc_core::sc_time tRL;
//const sc_core::sc_time tRPST;
//const sc_core::sc_time tDQSCK;
const sc_core::sc_time tRBTP;
const sc_core::sc_time tWL;
//const sc_core::sc_time tDQSS;
//const sc_core::sc_time tDQS2DQ;
const sc_core::sc_time tWR;
//const sc_core::sc_time tWPRE;
//const sc_core::sc_time tWTR;
//const sc_core::sc_time tXP;
//const sc_core::sc_time tSR;
//const sc_core::sc_time tXSR;
//const sc_core::sc_time tESCKE;
//const sc_core::sc_time tCKE;
//const sc_core::sc_time tCMDCKE;
const sc_core::sc_time tRTRS;
const sc_core::sc_time BL_n_min_16;
const sc_core::sc_time BL_n_max_16;
const sc_core::sc_time BL_n_L_16;
const sc_core::sc_time BL_n_S_16;
const sc_core::sc_time BL_n_min_32;
const sc_core::sc_time BL_n_max_32;
const sc_core::sc_time BL_n_L_32;
const sc_core::sc_time BL_n_S_32;
const sc_core::sc_time tWTR_L;
const sc_core::sc_time tWTR_S;
const sc_core::sc_time tWCK2DQO;
const sc_core::sc_time tpbR2act;
const sc_core::sc_time tpbR2pbR;
// Currents and Voltages:
// TODO: to be completed
sc_core::sc_time getRefreshIntervalAB() const override;
sc_core::sc_time getRefreshIntervalPB() const override;
sc_core::sc_time getRefreshIntervalP2B() const override;
unsigned getPer2BankOffset() const override;
sc_core::sc_time getExecutionTime(Command command, const tlm::tlm_generic_payload &payload) const override;
TimeInterval getIntervalOnDataStrobe(Command command, const tlm::tlm_generic_payload &payload) const override;
private:
unsigned per2BankOffset;
};
#endif // MEMSPECLPDDR5_H

19
DRAMSys/library/src/controller/Controller.cpp
View File

@@ -42,6 +42,7 @@
#include "checker/CheckerDDR5.h"
#include "checker/CheckerWideIO.h"
#include "checker/CheckerLPDDR4.h"
#include "checker/CheckerLPDDR5.h"
#include "checker/CheckerWideIO2.h"
#include "checker/CheckerHBM2.h"
#include "checker/CheckerGDDR5.h"
@@ -58,6 +59,7 @@
#include "refresh/RefreshManagerDummy.h"
#include "refresh/RefreshManagerAllBank.h"
#include "refresh/RefreshManagerPerBank.h"
#include "refresh/RefreshManagerPer2Bank.h"
#include "refresh/RefreshManagerSameBank.h"
#include "powerdown/PowerDownManagerStaggered.h"
#include "powerdown/PowerDownManagerDummy.h"
@@ -94,6 +96,8 @@ Controller::Controller(const sc_module_name &name) :
checker = new CheckerWideIO();
else if (memSpec->memoryType == MemSpec::MemoryType::LPDDR4)
checker = new CheckerLPDDR4();
else if (memSpec->memoryType == MemSpec::MemoryType::LPDDR5)
checker = new CheckerLPDDR5();
else if (memSpec->memoryType == MemSpec::MemoryType::WideIO2)
checker = new CheckerWideIO2();
else if (memSpec->memoryType == MemSpec::MemoryType::HBM2)
@@ -216,6 +220,16 @@ Controller::Controller(const sc_module_name &name) :
refreshManagers.push_back(manager);
}
}
else if (config.refreshPolicy == Configuration::RefreshPolicy::Per2Bank)
{
for (unsigned rankID = 0; rankID < memSpec->numberOfRanks; rankID++)
{
// TODO: remove bankMachines in constructor
RefreshManagerIF *manager = new RefreshManagerPer2Bank
(bankMachinesOnRank[rankID], powerDownManagers[rankID], Rank(rankID), checker);
refreshManagers.push_back(manager);
}
}
else
SC_REPORT_FATAL("Controller", "Selected refresh mode not supported!");
@@ -303,6 +317,11 @@ void Controller::controllerMethod()
bankID < memSpec->banksPerRank; bankID += memSpec->banksPerGroup)
bankMachinesOnRank[rank.ID()][bankID]->updateState(command);
}
else if (command.is2BankCommand())
{
bankMachines[bank.ID()]->updateState(command);
bankMachines[bank.ID() + memSpec->getPer2BankOffset()]->updateState(command);
}
else // if (isBankCommand(command))
bankMachines[bank.ID()]->updateState(command);

8
DRAMSys/library/src/controller/checker/CheckerDDR5.cpp
View File

@@ -124,14 +124,15 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo
BankGroup bankGroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
Bank bankInGroup = Bank(logicalRank.ID() * memSpec->banksPerGroup + bank.ID() % memSpec->banksPerGroup);
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(burstLength == 32) || (memSpec->bitWidth == 4));
sc_time lastCommandStart;
sc_time earliestTimeToStart = sc_time_stamp();
if (command == Command::RD || command == Command::RDA)
{
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(burstLength == 32) || (memSpec->bitWidth == 4));
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);
@@ -314,6 +315,9 @@ sc_time CheckerDDR5::timeToSatisfyConstraints(Command command, tlm_generic_paylo
}
else if (command == Command::WR || command == Command::WRA)
{
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(burstLength == 32) || (memSpec->bitWidth == 4));
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD);

673
DRAMSys/library/src/controller/checker/CheckerLPDDR5.cpp Normal file
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@@ -0,0 +1,673 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#include <algorithm>
#include "CheckerLPDDR5.h"
using namespace sc_core;
using namespace tlm;
CheckerLPDDR5::CheckerLPDDR5()
{
Configuration &config = Configuration::getInstance();
memSpec = dynamic_cast<const MemSpecLPDDR5 *>(config.memSpec);
if (memSpec == nullptr)
SC_REPORT_FATAL("CheckerLPDDR5", "Wrong MemSpec chosen");
else
{
lastScheduledByCommandAndRank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfRanks, sc_max_time()));
lastScheduledByCommandAndBankGroup = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBankGroups, sc_max_time()));
lastScheduledByCommandAndBank = std::vector<std::vector<sc_time>>
(Command::numberOfCommands(), std::vector<sc_time>(memSpec->numberOfBanks, sc_max_time()));
lastScheduledByCommand = std::vector<sc_time>(Command::numberOfCommands(), sc_max_time());
lastCommandOnBus = sc_max_time();
last4Activates = std::vector<std::queue<sc_time>>(memSpec->numberOfRanks);
lastBurstLengthByCommandAndRank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfRanks));
lastBurstLengthByCommandAndBankGroup = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfBankGroups));
lastBurstLengthByCommandAndBank = std::vector<std::vector<uint8_t>>
(Command::WRA + 1, std::vector<uint8_t>(memSpec->numberOfBanks));
lastBurstLengthByCommand = std::vector<uint8_t>(Command::WRA + 1);
tBURST16 = 16 / memSpec->dataRate * memSpec->tCK;
tBURST32 = 32 / memSpec->dataRate * memSpec->tCK;
}
}
sc_time CheckerLPDDR5::timeToSatisfyConstraints(Command command, tlm_generic_payload *payload) const
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
sc_time lastCommandStart;
sc_time earliestTimeToStart = sc_time_stamp();
if (command == Command::RD || command == Command::RDA)
{
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32
assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_16);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RD][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_16);
}
lastCommandStart = lastScheduledByCommand[Command::RD] != lastScheduledByCommandAndRank[Command::RD][rank.ID()] ?
lastScheduledByCommand[Command::RD] : sc_max_time();
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommand[Command::RD] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32 + memSpec->tRTRS);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tRTRS);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_16);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RDA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_16);
}
lastCommandStart = lastScheduledByCommand[Command::RDA] != lastScheduledByCommandAndRank[Command::RDA][rank.ID()] ?
lastScheduledByCommand[Command::RDA] : sc_max_time();
if (lastCommandStart != sc_max_time())
{
// TODO: BG mode with BL32
if (lastBurstLengthByCommand[Command::RDA] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32 + memSpec->tRTRS);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tRTRS);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_max_32 + memSpec->tWTR_L);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_max_16 + memSpec->tWTR_L);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WR][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tWTR_S);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tWTR_S);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_max_32 + memSpec->tWTR_L);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_max_16 + memSpec->tWTR_L);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WRA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tWTR_S);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tWTR_S);
}
}
else if (command == Command::WR || command == Command::WRA)
{
unsigned burstLength = DramExtension::getBurstLength(payload);
assert(!(memSpec->bitWidth == 8) || (burstLength == 32)); // x8 device -> BL32
assert(!(memSpec->groupsPerRank > 1) || (burstLength == 16)); // BG mode -> BL16
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RD][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::RD][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_max_32 + memSpec->tWCK2DQO - memSpec->tWL);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_max_16 + memSpec->tWCK2DQO - memSpec->tWL);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RD][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_min_32 + memSpec->tWCK2DQO - memSpec->tWL);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_min_16 + memSpec->tWCK2DQO - memSpec->tWL);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::RDA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::RDA][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_max_32 + memSpec->tWCK2DQO - memSpec->tWL);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_max_16 + memSpec->tWCK2DQO - memSpec->tWL);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RDA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_min_32 + memSpec->tWCK2DQO - memSpec->tWL);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRL
+ memSpec->BL_n_min_16 + memSpec->tWCK2DQO - memSpec->tWL);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WR][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WR][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_16);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WR][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_16);
}
lastCommandStart = lastScheduledByCommand[Command::WR] != lastScheduledByCommandAndRank[Command::WR][rank.ID()] ?
lastScheduledByCommand[Command::WR] : sc_max_time();
if (lastCommandStart != sc_max_time())
{
// TODO: BG mode with BL32
if (lastBurstLengthByCommand[Command::WR] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32 + memSpec->tRTRS);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tRTRS);
}
lastCommandStart = lastScheduledByCommandAndBankGroup[Command::WRA][bankGroup.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBankGroup[Command::WRA][bankGroup.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_L_16);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WRA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_32);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_S_16);
}
lastCommandStart = lastScheduledByCommand[Command::WRA] != lastScheduledByCommandAndRank[Command::WRA][rank.ID()] ?
lastScheduledByCommand[Command::WRA] : sc_max_time();
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommand[Command::WRA] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST32 + memSpec->tRTRS);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + tBURST16 + memSpec->tRTRS);
}
}
else if (command == Command::ACT)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::RDA][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP + memSpec->tRPpb - memSpec->tCK);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP + memSpec->tRPpb - memSpec->tCK);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::RDA][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb - memSpec->tCK);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb - memSpec->tCK);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tpbR2act - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFP2B][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tpbR2act - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFP2B][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb - memSpec->tCK);
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW - memSpec->tCK);
}
else if (command == Command::PREPB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RD][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::RD][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::WR][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::WR][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
}
else if (command == Command::PREAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRAS + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RD][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RD][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RDA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WR][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WR][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WRA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tPPD);
}
else if (command == Command::REFAB)
{
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::RDA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::RDA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::WRA][rank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndRank[Command::WRA][rank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndRank[Command::PREPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCab);
}
else if (command == Command::REFPB)
{
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::RDA][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFPB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tpbR2pbR);
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW);
}
else if (command == Command::REFP2B)
{
Bank secondBank = Bank(bank.ID() + memSpec->getPer2BankOffset());
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::ACT][secondBank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRCpb + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndRank[Command::ACT][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRRD + memSpec->tCK);
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::RDA][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::RDA][secondBank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::RDA][secondBank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_32
+ memSpec->tRBTP + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->BL_n_min_16
+ memSpec->tRBTP + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][bank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::WRA][bank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::WRA][secondBank.ID()];
if (lastCommandStart != sc_max_time())
{
if (lastBurstLengthByCommandAndBank[Command::WRA][secondBank.ID()] == 32)
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_32 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
else
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tWL
+ memSpec->BL_n_min_16 + memSpec->tCK + memSpec->tWR + memSpec->tRPpb);
}
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndBank[Command::PREPB][secondBank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::PREAB][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRPab);
lastCommandStart = lastScheduledByCommandAndBank[Command::REFP2B][bank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tRFCpb);
lastCommandStart = lastScheduledByCommandAndRank[Command::REFP2B][rank.ID()];
if (lastCommandStart != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandStart + memSpec->tpbR2pbR);
if (last4Activates[rank.ID()].size() >= 4)
earliestTimeToStart = std::max(earliestTimeToStart, last4Activates[rank.ID()].front() + memSpec->tFAW);
}
else
SC_REPORT_FATAL("CheckerLPDDR5", "Unknown command!");
// Check if command bus is free
if (lastCommandOnBus != sc_max_time())
earliestTimeToStart = std::max(earliestTimeToStart, lastCommandOnBus + memSpec->tCK);
return earliestTimeToStart;
}
void CheckerLPDDR5::insert(Command command, tlm_generic_payload *payload)
{
Rank rank = DramExtension::getRank(payload);
BankGroup bankGroup = DramExtension::getBankGroup(payload);
Bank bank = DramExtension::getBank(payload);
unsigned burstLength = DramExtension::getBurstLength(payload);
PRINTDEBUGMESSAGE("CheckerLPDDR5", "Changing state on bank " + std::to_string(bank.ID())
+ " command is " + command.toString());
lastScheduledByCommandAndRank[command][rank.ID()] = sc_time_stamp();
lastScheduledByCommandAndBankGroup[command][bankGroup.ID()] = sc_time_stamp();
lastScheduledByCommandAndBank[command][bank.ID()] = sc_time_stamp();
lastScheduledByCommand[command] = sc_time_stamp();
if (command.isCasCommand())
{
lastBurstLengthByCommandAndRank[command][rank.ID()] = burstLength;
lastBurstLengthByCommandAndBankGroup[command][bankGroup.ID()] = burstLength;
lastBurstLengthByCommandAndBank[command][bank.ID()] = burstLength;
lastBurstLengthByCommand[command] = burstLength;
}
if (command == Command::REFP2B)
lastScheduledByCommandAndBank[command][bank.ID() + memSpec->getPer2BankOffset()] = sc_time_stamp();
lastCommandOnBus = sc_time_stamp() + memSpec->getCommandLength(command) - memSpec->tCK;
if (command == Command::ACT || command == Command::REFPB || command == Command::REFP2B
|| command == Command::RFMPB || command == Command::RFMP2B)
{
if (last4Activates[rank.ID()].size() == 4)
last4Activates[rank.ID()].pop();
last4Activates[rank.ID()].push(lastCommandOnBus);
}
}

83
DRAMSys/library/src/controller/checker/CheckerLPDDR5.h Normal file
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@@ -0,0 +1,83 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#ifndef CHECKERLPDDR5_H
#define CHECKERLPDDR5_H
#include <queue>
#include <vector>
#include "CheckerIF.h"
#include "../../configuration/memspec/MemSpecLPDDR5.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
class CheckerLPDDR5 final : public CheckerIF
{
public:
CheckerLPDDR5();
sc_core::sc_time timeToSatisfyConstraints(Command command, tlm::tlm_generic_payload *payload) const override;
void insert(Command command, tlm::tlm_generic_payload *payload) override;
private:
const MemSpecLPDDR5 *memSpec;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndRank;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBankGroup;
std::vector<std::vector<sc_core::sc_time>> lastScheduledByCommandAndBank;
std::vector<sc_core::sc_time> lastScheduledByCommand;
sc_core::sc_time lastCommandOnBus;
std::vector<std::queue<sc_core::sc_time>> last4Activates;
std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndRank;
std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndBankGroup;
std::vector<std::vector<uint8_t>> lastBurstLengthByCommandAndBank;
std::vector<uint8_t> lastBurstLengthByCommand;
sc_core::sc_time tBURST16;
sc_core::sc_time tBURST32;
sc_core::sc_time tRDWR;
sc_core::sc_time tRDWR_R;
sc_core::sc_time tWRRD_S;
sc_core::sc_time tWRRD_L;
sc_core::sc_time tWRRD_R;
sc_core::sc_time tRDAACT;
sc_core::sc_time tWRPRE;
sc_core::sc_time tWRAACT;
sc_core::sc_time tRDPDEN;
sc_core::sc_time tWRPDEN;
sc_core::sc_time tWRAPDEN;
};
#endif // CHECKERLPDDR5_H

253
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.cpp Normal file
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@@ -0,0 +1,253 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#include "RefreshManagerPer2Bank.h"
#include "../../configuration/Configuration.h"
#include "../../common/utils.h"
#include "../../common/dramExtensions.h"
using namespace sc_core;
using namespace tlm;
RefreshManagerPer2Bank::RefreshManagerPer2Bank(std::vector<BankMachine *> &bankMachinesOnRank,
PowerDownManagerIF *powerDownManager, Rank rank, CheckerIF *checker)
: powerDownManager(powerDownManager), checker(checker)
{
Configuration &config = Configuration::getInstance();
memSpec = config.memSpec;
timeForNextTrigger = getTimeForFirstTrigger(memSpec->getRefreshIntervalP2B(),
rank, memSpec->numberOfRanks);
// each bank pair has one payload (e.g. 0-8, 1-9, 2-10, 3-11, ...)
for (unsigned outerID = 0; outerID < memSpec->banksPerRank; outerID += (memSpec->getPer2BankOffset() * 2))
{
for (unsigned bankID = outerID; bankID < (outerID + memSpec->getPer2BankOffset()); bankID++)
{
unsigned bankID2 = bankID + memSpec->getPer2BankOffset();
setUpDummy(refreshPayloads[bankMachinesOnRank[bankID]], 0, rank,
bankMachinesOnRank[bankID]->getBankGroup(), bankMachinesOnRank[bankID]->getBank());
setUpDummy(refreshPayloads[bankMachinesOnRank[bankID2]], 0, rank,
bankMachinesOnRank[bankID2]->getBankGroup(), bankMachinesOnRank[bankID2]->getBank());
allBankMachines.push_back({bankMachinesOnRank[bankID], bankMachinesOnRank[bankID2]});
}
}
remainingBankMachines = allBankMachines;
currentIterator = remainingBankMachines.begin();
currentRefreshPayload = &refreshPayloads[currentIterator->front()];
maxPostponed = static_cast<int>(config.refreshMaxPostponed * memSpec->banksPerRank / 2);
maxPulledin = -static_cast<int>(config.refreshMaxPulledin * memSpec->banksPerRank / 2);
}
CommandTuple::Type RefreshManagerPer2Bank::getNextCommand()
{
return {nextCommand, currentRefreshPayload, std::max(timeToSchedule, sc_time_stamp())};
}
sc_time RefreshManagerPer2Bank::start()
{
timeToSchedule = sc_max_time();
nextCommand = Command::NOP;
if (sc_time_stamp() >= timeForNextTrigger)
{
powerDownManager->triggerInterruption();
if (sleeping)
return timeToSchedule;
if (sc_time_stamp() >= timeForNextTrigger + memSpec->getRefreshIntervalP2B())
{
timeForNextTrigger += memSpec->getRefreshIntervalP2B();
state = State::Regular;
}
if (state == State::Regular)
{
bool forcedRefresh = (flexibilityCounter == maxPostponed);
bool allBankPairsBusy = true;
if (!skipSelection)
{
currentIterator = remainingBankMachines.begin();
for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++)
{
bool pairIsBusy = false;
for (auto pairIt : *bankIt)
{
if (!pairIt->isIdle())
{
pairIsBusy = true;
break;
}
}
if (!pairIsBusy)
{
allBankPairsBusy = false;
currentIterator = bankIt;
break;
}
}
}
if (allBankPairsBusy && !forcedRefresh)
{
flexibilityCounter++;
timeForNextTrigger += memSpec->getRefreshIntervalP2B();
return timeForNextTrigger;
}
else
{
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads[currentIterator->front()];
for (auto it : *currentIterator)
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads[it];
break;
}
}
// TODO: banks should already be blocked for precharge and selection should be skipped
if (nextCommand == Command::REFP2B && forcedRefresh)
{
for (auto it : *currentIterator)
it->block();
skipSelection = true;
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentRefreshPayload);
return timeToSchedule;
}
}
else // if (state == RmState::Pulledin)
{
bool allBankPairsBusy = true;
currentIterator = remainingBankMachines.begin();
for (auto bankIt = remainingBankMachines.begin(); bankIt != remainingBankMachines.end(); bankIt++)
{
bool pairIsBusy = false;
for (auto pairIt : *bankIt)
{
if (!pairIt->isIdle())
{
pairIsBusy = true;
break;
}
}
if (!pairIsBusy)
{
allBankPairsBusy = false;
currentIterator = bankIt;
break;
}
}
if (allBankPairsBusy)
{
state = State::Regular;
timeForNextTrigger += memSpec->getRefreshIntervalP2B();
return timeForNextTrigger;
}
else
{
nextCommand = Command::REFP2B;
currentRefreshPayload = &refreshPayloads[currentIterator->front()];
for (auto it : *currentIterator)
{
if (it->isActivated())
{
nextCommand = Command::PREPB;
currentRefreshPayload = &refreshPayloads[it];
break;
}
}
timeToSchedule = checker->timeToSatisfyConstraints(nextCommand, currentRefreshPayload);
return timeToSchedule;
}
}
}
else
return timeForNextTrigger;
}
void RefreshManagerPer2Bank::updateState(Command command)
{
switch (command)
{
case Command::REFP2B:
skipSelection = false;
remainingBankMachines.erase(currentIterator);
if (remainingBankMachines.empty())
remainingBankMachines = allBankMachines;
currentIterator = remainingBankMachines.begin();
if (state == State::Pulledin)
flexibilityCounter--;
else
state = State::Pulledin;
if (flexibilityCounter == maxPulledin)
{
state = State::Regular;
timeForNextTrigger += memSpec->getRefreshIntervalP2B();
}
break;
case Command::REFAB:
// Refresh command after SREFEX
state = State::Regular; // TODO: check if this assignment is necessary
timeForNextTrigger = sc_time_stamp() + memSpec->getRefreshIntervalP2B();
sleeping = false;
remainingBankMachines = allBankMachines;
currentIterator = remainingBankMachines.begin();
skipSelection = false;
break;
case Command::PDEA: case Command::PDEP:
sleeping = true;
break;
case Command::SREFEN:
sleeping = true;
timeForNextTrigger = sc_max_time();
break;
case Command::PDXA: case Command::PDXP:
sleeping = false;
break;
default:
break;
}
}

81
DRAMSys/library/src/controller/refresh/RefreshManagerPer2Bank.h Normal file
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@@ -0,0 +1,81 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Author: Lukas Steiner
*/
#ifndef REFRESHMANAGERPER2BANK_H
#define REFRESHMANAGERPER2BANK_H
#include <vector>
#include <list>
#include <unordered_map>
#include <systemc>
#include <tlm>
#include "RefreshManagerIF.h"
#include "../../configuration/memspec/MemSpec.h"
#include "../BankMachine.h"
#include "../powerdown/PowerDownManagerIF.h"
class RefreshManagerPer2Bank final : public RefreshManagerIF
{
public:
RefreshManagerPer2Bank(std::vector<BankMachine *> &, PowerDownManagerIF *, Rank, CheckerIF *);
CommandTuple::Type getNextCommand() override;
sc_core::sc_time start() override;
void updateState(Command) override;
private:
enum class State {Regular, Pulledin} state = State::Regular;
const MemSpec *memSpec;
PowerDownManagerIF *powerDownManager;
std::unordered_map<BankMachine *, tlm::tlm_generic_payload> refreshPayloads;
tlm::tlm_generic_payload *currentRefreshPayload;
sc_core::sc_time timeForNextTrigger = sc_core::sc_max_time();
sc_core::sc_time timeToSchedule = sc_core::sc_max_time();
CheckerIF *checker;
Command nextCommand = Command::NOP;
std::list<std::vector<BankMachine *>> remainingBankMachines;
std::list<std::vector<BankMachine *>> allBankMachines;
std::list<std::vector<BankMachine *>>::iterator currentIterator;
int flexibilityCounter = 0;
int maxPostponed = 0;
int maxPulledin = 0;
bool sleeping = false;
bool skipSelection = false;
};
#endif // REFRESHMANAGERPER2BANK_H

3
DRAMSys/library/src/simulation/DRAMSys.cpp
View File

@@ -53,6 +53,7 @@
#include "dram/DramDDR5.h"
#include "dram/DramWideIO.h"
#include "dram/DramLPDDR4.h"
#include "dram/DramLPDDR5.h"
#include "dram/DramWideIO2.h"
#include "dram/DramHBM2.h"
#include "dram/DramGDDR5.h"
@@ -220,6 +221,8 @@ void DRAMSys::instantiateModules(const std::string &pathToResources,
dram = new DramWideIO(str.c_str());
else if (memoryType == MemSpec::MemoryType::LPDDR4)
dram = new DramLPDDR4(str.c_str());
else if (memoryType == MemSpec::MemoryType::LPDDR5)
dram = new DramLPDDR5(str.c_str());
else if (memoryType == MemSpec::MemoryType::WideIO2)
dram = new DramWideIO2(str.c_str());
else if (memoryType == MemSpec::MemoryType::HBM2)

3
DRAMSys/library/src/simulation/DRAMSysRecordable.cpp
View File

@@ -41,6 +41,7 @@
#include "dram/DramDDR5.h"
#include "dram/DramWideIO.h"
#include "dram/DramLPDDR4.h"
#include "dram/DramLPDDR5.h"
#include "dram/DramWideIO2.h"
#include "dram/DramHBM2.h"
#include "dram/DramGDDR5.h"
@@ -166,6 +167,8 @@ void DRAMSysRecordable::instantiateModules(const std::string &traceName,
dram = new DramRecordable<DramWideIO>(str.c_str(), tlmRecorders[i]);
else if (memoryType == MemSpec::MemoryType::LPDDR4)
dram = new DramRecordable<DramLPDDR4>(str.c_str(), tlmRecorders[i]);
else if (memoryType == MemSpec::MemoryType::LPDDR5)
dram = new DramRecordable<DramLPDDR5>(str.c_str(), tlmRecorders[i]);
else if (memoryType == MemSpec::MemoryType::WideIO2)
dram = new DramRecordable<DramWideIO2>(str.c_str(), tlmRecorders[i]);
else if (memoryType == MemSpec::MemoryType::HBM2)

50
DRAMSys/library/src/simulation/dram/DramLPDDR5.cpp Normal file
View File

@@ -0,0 +1,50 @@
/*
* Copyright (c) 2021, Technische Universität Kaiserslautern
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors:
* Lukas Steiner
*/
#include "DramLPDDR5.h"
#include "Dram.h"
#include "../../configuration/Configuration.h"
#include "../../common/third_party/DRAMPower/src/libdrampower/LibDRAMPower.h"
#include "../../configuration/memspec/MemSpecLPDDR5.h"
DramLPDDR5::DramLPDDR5(const sc_module_name &name) : Dram(name)
{
if (storeMode == Configuration::StoreMode::ErrorModel)
SC_REPORT_FATAL("DramLPDDR5", "Error Model not supported for LPDDR5");
if (Configuration::getInstance().powerAnalysis)
SC_REPORT_FATAL("DramLPDDR5", "DRAMPower does not support LPDDR5");
}

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